WO2003021668A1 - Tableau de connexions, dispositif a semi-conducteur et leur procede de production - Google Patents

Tableau de connexions, dispositif a semi-conducteur et leur procede de production Download PDF

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Publication number
WO2003021668A1
WO2003021668A1 PCT/JP2001/007555 JP0107555W WO03021668A1 WO 2003021668 A1 WO2003021668 A1 WO 2003021668A1 JP 0107555 W JP0107555 W JP 0107555W WO 03021668 A1 WO03021668 A1 WO 03021668A1
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WO
WIPO (PCT)
Prior art keywords
wiring board
producing
semiconductor device
basic material
insulating basic
Prior art date
Application number
PCT/JP2001/007555
Other languages
English (en)
Japanese (ja)
Inventor
Naoki Fukutomi
Kazuhisa Suzuki
Osamu Shimada
Kazumasa Takeuchi
Yoshiaki Wakashima
Susumu Okikawa
Original Assignee
Hitachi Chemical Co.,Ltd.
Hitachi Metals Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co.,Ltd., Hitachi Metals Ltd. filed Critical Hitachi Chemical Co.,Ltd.
Priority to JP2003525905A priority Critical patent/JPWO2003021668A1/ja
Priority to PCT/JP2001/007555 priority patent/WO2003021668A1/fr
Publication of WO2003021668A1 publication Critical patent/WO2003021668A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H05K1/111—Pads for surface mounting, e.g. lay-out
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Abstract

L'invention concerne un tableau de connexions comprenant un matériau de base isolant, un câblage installé sur l'une des surfaces avant ou arrière dudit tableau de connexions et un élément conducteur enterré dans le matériau de base isolant. L'élément conducteur possède une extrémité exposée à la surface du matériau de base isolant et reliée au câblage, l'autre extrémité étant enterrée dans ledit matériau de base isolant. L'invention concerne également un dispositif à semi-conducteur utilisant le tableau de connexions et le procédé de production de ces deux dispositifs.
PCT/JP2001/007555 2001-08-31 2001-08-31 Tableau de connexions, dispositif a semi-conducteur et leur procede de production WO2003021668A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003525905A JPWO2003021668A1 (ja) 2001-08-31 2001-08-31 配線基板、半導体装置及びそれらの製造方法
PCT/JP2001/007555 WO2003021668A1 (fr) 2001-08-31 2001-08-31 Tableau de connexions, dispositif a semi-conducteur et leur procede de production

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JP2005159354A (ja) * 2003-11-25 2005-06-16 Internatl Business Mach Corp <Ibm> 高性能チップ・キャリア基板
JP2007506279A (ja) * 2003-09-18 2007-03-15 クリー　インコーポレイテッド 成形チップの製造方法および装置
JP2008172268A (ja) * 2008-02-28 2008-07-24 Nippon Mektron Ltd 多層回路基板の製造方法および回路基材
JP2010232524A (ja) * 2009-03-27 2010-10-14 Nitto Denko Corp 半導体装置の製造方法
US7897980B2 (en) 2006-11-09 2011-03-01 Cree, Inc. Expandable LED array interconnect
US8637883B2 (en) 2008-03-19 2014-01-28 Cree, Inc. Low index spacer layer in LED devices
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US9024349B2 (en) 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
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US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US10295147B2 (en) 2006-11-09 2019-05-21 Cree, Inc. LED array and method for fabricating same
US10505083B2 (en) 2007-07-11 2019-12-10 Cree, Inc. Coating method utilizing phosphor containment structure and devices fabricated using same
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JP2007506279A (ja) * 2003-09-18 2007-03-15 クリー　インコーポレイテッド 成形チップの製造方法および装置
US10546978B2 (en) 2003-09-18 2020-01-28 Cree, Inc. Molded chip fabrication method and apparatus
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JP2005159354A (ja) * 2003-11-25 2005-06-16 Internatl Business Mach Corp <Ibm> 高性能チップ・キャリア基板
JP4528098B2 (ja) * 2003-11-25 2010-08-18 インターナショナル・ビジネス・マシーンズ・コーポレーション 高性能チップ・キャリア基板
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US8969908B2 (en) 2006-04-04 2015-03-03 Cree, Inc. Uniform emission LED package
US7897980B2 (en) 2006-11-09 2011-03-01 Cree, Inc. Expandable LED array interconnect
US10295147B2 (en) 2006-11-09 2019-05-21 Cree, Inc. LED array and method for fabricating same
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9024349B2 (en) 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US10505083B2 (en) 2007-07-11 2019-12-10 Cree, Inc. Coating method utilizing phosphor containment structure and devices fabricated using same
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8878219B2 (en) 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
JP2008172268A (ja) * 2008-02-28 2008-07-24 Nippon Mektron Ltd 多層回路基板の製造方法および回路基材
US8637883B2 (en) 2008-03-19 2014-01-28 Cree, Inc. Low index spacer layer in LED devices
JP2010232524A (ja) * 2009-03-27 2010-10-14 Nitto Denko Corp 半導体装置の製造方法
US10546846B2 (en) 2010-07-23 2020-01-28 Cree, Inc. Light transmission control for masking appearance of solid state light sources
KR101631934B1 (ko) 2013-11-13 2016-06-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 그 제작 방법
KR20150055673A (ko) * 2013-11-13 2015-05-22 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 그 제작 방법

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