WO2003017490A1 - Method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit - Google Patents

Method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit Download PDF

Info

Publication number
WO2003017490A1
WO2003017490A1 PCT/US2002/025849 US0225849W WO03017490A1 WO 2003017490 A1 WO2003017490 A1 WO 2003017490A1 US 0225849 W US0225849 W US 0225849W WO 03017490 A1 WO03017490 A1 WO 03017490A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
stage
current
signal
last
Prior art date
Application number
PCT/US2002/025849
Other languages
French (fr)
Other versions
WO2003017490A8 (en
Inventor
Claude R. Gauthier
Tyler J. Thorp
Richard L. Wheeler
Brian W. Amick
Original Assignee
Sun Microsystems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/930,373 external-priority patent/US6871290B2/en
Priority claimed from US09/930,030 external-priority patent/US20030034817A1/en
Application filed by Sun Microsystems, Inc. filed Critical Sun Microsystems, Inc.
Priority to EP02761371A priority Critical patent/EP1421691A1/en
Publication of WO2003017490A1 publication Critical patent/WO2003017490A1/en
Publication of WO2003017490A8 publication Critical patent/WO2003017490A8/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
    • H03K17/164—Soft switching using parallel switching arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Definitions

  • microprocessor also known in the art as a "central processing unit” or “CPU”
  • CPU central processing unit
  • the microprocessor must be powered down to avoid microprocessor malfunction or damage. For example, if a microprocessor's cooling system fails, the microprocessor must be shut down quickly in order to avoid overheating. Similarly, if a microprocessor is drawing power in a manner that adversely affects other computer chip components, the microprocessor must be powered down to avoid undesirable effects.
  • Equation 1 shows the relationship between voltage, change in time, and change in current:
  • V Z * ⁇ (1)
  • V represents voltage
  • Z represents impedance
  • i current
  • Figure 1 shows a typical relationship (10) between current and time when power to a microprocessor, or other integrated circuit, is decreased instantly to a desired level. Particularly, Figure 1 shows the rate of current change, Ai/At, when current is reduced from 10 amps to 5 amps.
  • an apparatus for reducing a magnitude of a rate of current change of an integrated circuit comprises a control stage that generates a control signal dependent on whether power consumption by the integrated circuit needs to be reduced, and a counter stage that inputs the control signal and generates a plurality of sequential signals to a plurality of transistors, where the plurality of transistors source current from a power supply.
  • a circuit for reducing a rate of current change of a microprocessor comprises a control stage that is connected to a power terminal and a ground terminal, where the control stage generates a control signal, and a counter stage that inputs the control signal and a clock signal, where the counter stage generates a first signal to a gate terminal of a first transistor.
  • a method for reducing a magnitude of a rate of current change for an integrated circuit comprises determining when power consumption by the integrated circuit needs to be reduced and gradually reducing an amount of current sourced by a power supply based on the determination.
  • a method for reducing a magnitude of a rate of current change for an integrated circuit comprises a step of determining when power consumption by the integrated circuit needs to be reduced and a step of gradually reducing an amount of current sourced by a power supply based on the determination.
  • Figure 1 shows a typical relationship between current and time when power is reduced.
  • Figure 2a shows a diagram of a circuit in accordance with an embodiment of the present invention.
  • Figure 2b shows a relationship between current and time in accordance with the embodiment shown in Figure 2a.
  • the present invention relates to a method and apparatus for reducing a magnitude of a rate of current change of a microprocessor or other integrated circuit. Further, the present invention relates to a method and apparatus for powering down a microprocessor or other integrated circuit. Further, the present invention relates to a method and apparatus for cooling down a microprocessor or other integrated circuit.
  • Figure 2a shows a diagram of an exemplary circuit in accordance with an embodiment of the present invention.
  • Figure 2a shows a micro-architectural block (also referred to as "micro-architectural stage”) (30) that generates a signal, m_out, to control a counter block (also referred to as "counter stage”) (32), where the counter block (32) may include a finite state machine such as a counter (not shown).
  • the counter block (32) which inputs a clock signal, CLK, for timing and counting purposes, generates signals, C 0 , C ⁇ 5 C 2, and C 3 , to a first transistor (34), a second transistor (36), a third transistor (38), and a fourth transistor (40), respectively.
  • the counter block (32) When a particular transistor shown in Figure 2a is 'on,' i.e., enabled, that particular transistor behaves as a current source in that it sources current from V DD (42) to Vss (44). When a particular transistor is 'off,' i.e., is disabled, the current sourced through that particular transistor is decreased. [0015]
  • the counter block (32) generates a low signal successively on C 0 , C ⁇ > C 2) and C 3 on positive edges of CLK. However, those skilled in the art will appreciate that in other embodiments, the counter block (32) may be designed differently.
  • the micro-architectural block (30) may be a thermal sensor that is used to power down a microprocessor when the microprocessor is about to or begins to overheat.
  • Figure 2b shows a relationship (46) between current and time based on the signals and circuit shown in Figure 2a.
  • the counter block (32) When m out is high (48), the counter block (32) generates high values on C 0 , C 1) C 2; and C 3 , where, in turn, the first, second, third, and last transistors (34, 36, 38, 40) are all switched 'on.' In this case, the transistors (34, 36, 38, 40) collectively source 10 amps from V DD (42) to N ss (44).
  • the counter block (32) When m_out goes low (50), the counter block (32) generates low values on C 0 , C ⁇ ⁇ C 2) and C 3 successively at positive edges on CLK. Thus, at the first positive edge on CLK after m_out goes low (50), the counter block (32) generates a low value on C 0 (52), which, in turn, causes the first transistor (34) to switch 'off,' effectively reducing the collective current sourced by the transistors (34, 36, 38, 40) from V DD (42) to V ss (44).
  • the counter block (32) At the next positive edge on CLK, the counter block (32) generates a low value on Ci (54), which, in turn, causes the second transistor (36) to switch 'off,' effectively reducing the collective current sourced by the transistors (34, 36, 38, 40) from V DD (42) to Vss (44).
  • the counter block (32) At the next positive edge on CLK, the counter block (32) generates a low value on C 2 (56), which, in turn, causes the third transistor (38) to switch 'off,' effectively reducing the collective current sourced by the transistors (34, 36, 38, 40) from N DD (42) to N ss (44).
  • the counter block (32) At the next positive edge on CLK after m_out goes low (50), the counter block (32) generates a low value on C 3 (58), which, in turn, causes the last transistor (40) to switch 'off,' effectively reducing the collective current sourced by the transistors (34, 36, 38, 40) from N DD (42) to V ss (44).
  • Advantages of the present invention may include one or more of the following.
  • a magnitude of a rate of current change of a microprocessor is reduced, and the microprocessor runs quieter, i.e., less noise, than when only one transistor is used to reduce power consumption.

Abstract

A method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit are provided. The apparatus uses a counter stage (32) controlled by a control stage (30) to sequentially disable a plurality of transistors (34, 36, 38, 40) that are used to source current from a power supply. By sequentially disabling the plurality of transistors, a reduction of an amount of current occurs gradually, effectively reducing the magnitude of the rate of current change. Further, the method uses a plurality of transistors controlled by a finite state machine, such as a counter, to gradually reduce current sourced from a power supply. The finite state machine is controlled by a micro-architectural stage that determines when the integrated circuit needs to be powered down.

Description

METHOD AND APPARATUS FORREDUCINGAMAGNITUDE OFA RATE OF CURRENT CHANGE OFANINTEGRATED CIRCUIT
Background of Invention
[0001] As technology improves, integrated circuits, such as microprocessors, continue to become faster and more powerful. However, the benefits of increased speed and higher data throughput must be balanced with the costs of increased power consumption and higher operating temperatures.
[0002] When a microprocessor (also known in the art as a "central processing unit" or "CPU") approaches or exceeds a certain power or temperature threshold, the microprocessor must be powered down to avoid microprocessor malfunction or damage. For example, if a microprocessor's cooling system fails, the microprocessor must be shut down quickly in order to avoid overheating. Similarly, if a microprocessor is drawing power in a manner that adversely affects other computer chip components, the microprocessor must be powered down to avoid undesirable effects.
[0003] However, the high-power nature of a microprocessor makes it difficult to power the microprocessor down instantly because doing so might cause damage to a computer chip's power supplies. The magnitude of such an instant change in current would be so high that a large change in voltage might result potentially damaging not only power supplies, but also computer chip components. Equation 1 shows the relationship between voltage, change in time, and change in current:
V = Z * Ϊ (1) where V represents voltage, Z represents impedance, and- i represents current. Thus, it follows that when i is instantly decreased, V decreases at a rate that a typical computer chip cannot sustain.
[0004] Figure 1 shows a typical relationship (10) between current and time when power to a microprocessor, or other integrated circuit, is decreased instantly to a desired level. Particularly, Figure 1 shows the rate of current change, Ai/At, when current is reduced from 10 amps to 5 amps.
Summary of the Invention
[0005] According to one aspect of the present invention, an apparatus for reducing a magnitude of a rate of current change of an integrated circuit comprises a control stage that generates a control signal dependent on whether power consumption by the integrated circuit needs to be reduced, and a counter stage that inputs the control signal and generates a plurality of sequential signals to a plurality of transistors, where the plurality of transistors source current from a power supply.
[0006] According to another aspect, a circuit for reducing a rate of current change of a microprocessor comprises a control stage that is connected to a power terminal and a ground terminal, where the control stage generates a control signal, and a counter stage that inputs the control signal and a clock signal, where the counter stage generates a first signal to a gate terminal of a first transistor.
[0007] According to another aspect, a method for reducing a magnitude of a rate of current change for an integrated circuit comprises determining when power consumption by the integrated circuit needs to be reduced and gradually reducing an amount of current sourced by a power supply based on the determination.
[0008] According to another aspect, a method for reducing a magnitude of a rate of current change for an integrated circuit comprises a step of determining when power consumption by the integrated circuit needs to be reduced and a step of gradually reducing an amount of current sourced by a power supply based on the determination.
[0009] Other aspects and advantages of the invention will be apparent from the following description and the appended claims. Brief Description of Drawings
[0010] Figure 1 shows a typical relationship between current and time when power is reduced.
[0011] Figure 2a shows a diagram of a circuit in accordance with an embodiment of the present invention.
[0012] Figure 2b shows a relationship between current and time in accordance with the embodiment shown in Figure 2a.
Detailed Description
[0013] The present invention relates to a method and apparatus for reducing a magnitude of a rate of current change of a microprocessor or other integrated circuit. Further, the present invention relates to a method and apparatus for powering down a microprocessor or other integrated circuit. Further, the present invention relates to a method and apparatus for cooling down a microprocessor or other integrated circuit.
[0014] Figure 2a shows a diagram of an exemplary circuit in accordance with an embodiment of the present invention. Particularly, Figure 2a shows a micro-architectural block (also referred to as "micro-architectural stage") (30) that generates a signal, m_out, to control a counter block (also referred to as "counter stage") (32), where the counter block (32) may include a finite state machine such as a counter (not shown). The counter block (32), which inputs a clock signal, CLK, for timing and counting purposes, generates signals, C0, Cχ5 C2, and C3, to a first transistor (34), a second transistor (36), a third transistor (38), and a fourth transistor (40), respectively. When a particular transistor shown in Figure 2a is 'on,' i.e., enabled, that particular transistor behaves as a current source in that it sources current from VDD (42) to Vss (44). When a particular transistor is 'off,' i.e., is disabled, the current sourced through that particular transistor is decreased. [0015] The counter block (32) generates a low signal successively on C0, Cχ> C2) and C3 on positive edges of CLK. However, those skilled in the art will appreciate that in other embodiments, the counter block (32) may be designed differently.
[0016] Those skilled in the art will also appreciate that in other embodiments, a different amount of signals generated by the counter block (32) may be used. Further, those skilled in the art will appreciate that in other embodiments, a • different amount of transistors may be used. Further, those skilled in the art will appreciate that the micro-architectural block (30) may be a thermal sensor that is used to power down a microprocessor when the microprocessor is about to or begins to overheat.
[0017] Figure 2b shows a relationship (46) between current and time based on the signals and circuit shown in Figure 2a. When m out is high (48), the counter block (32) generates high values on C0, C1) C2; and C3, where, in turn, the first, second, third, and last transistors (34, 36, 38, 40) are all switched 'on.' In this case, the transistors (34, 36, 38, 40) collectively source 10 amps from VDD (42) to Nss (44).
[0018] When m_out goes low (50), the counter block (32) generates low values on C0, Cχι C2) and C3 successively at positive edges on CLK. Thus, at the first positive edge on CLK after m_out goes low (50), the counter block (32) generates a low value on C0 (52), which, in turn, causes the first transistor (34) to switch 'off,' effectively reducing the collective current sourced by the transistors (34, 36, 38, 40) from VDD (42) to Vss (44). At the next positive edge on CLK, the counter block (32) generates a low value on Ci (54), which, in turn, causes the second transistor (36) to switch 'off,' effectively reducing the collective current sourced by the transistors (34, 36, 38, 40) from VDD (42) to Vss (44). At the next positive edge on CLK, the counter block (32) generates a low value on C2 (56), which, in turn, causes the third transistor (38) to switch 'off,' effectively reducing the collective current sourced by the transistors (34, 36, 38, 40) from NDD (42) to Nss (44). At the next positive edge on CLK after m_out goes low (50), the counter block (32) generates a low value on C3 (58), which, in turn, causes the last transistor (40) to switch 'off,' effectively reducing the collective current sourced by the transistors (34, 36, 38, 40) from NDD (42) to Vss (44).
[0019] Those skilled in the art will appreciate that whenever a transistor is disabled, the amount of reduction of current sourced from VDD (42) to VSs (44) is less than in the case where only one transistor is used to source current from NDD (42) to Vss (44). Thus, by gradually reducing the current sourced from NDD (42) to Nss (44), the magnitude of the rate of current change, or Ail At, is less than in the case where the current reduction is effected by simply instantly reducing the current to a desired level.
[0020] Advantages of the present invention may include one or more of the following. In some embodiments, because a plurality of transistors are used to reduce power consumption, a magnitude of a rate of current change of a microprocessor is reduced, and the microprocessor runs quieter, i.e., less noise, than when only one transistor is used to reduce power consumption.
[0021] In some embodiments, because a magnitude of a rate of current change of a microprocessor is reduced gradually as opposed to suddenly, the microprocessor operates faster.
[0022] In some embodiments, because a magnitude of a rate of current change of a microprocessor is reduced gradually instead of suddenly, the chance of power supply damage is reduced.
[0023] In some embodiments, because a magnitude of a rate of current change of a microprocessor is reduced gradually as opposed to suddenly, the effect on average power consumption is reduced.
[0024] While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.

Claims

What is claimed is:
[cl] An apparatus for reducing a magnitude of a rate of current change of an integrated circuit, comprising: a control stage that generates a control signal dependent on whether power consumption by the integrated circuit needs to be reduced; and a counter stage that inputs the control signal and generates a plurality of sequential signals to a plurality of transistors, wherein the plurality of transistors source current from a power supply.
[c2] The apparatus of claim 1, wherein the counter stage sequentially disables the plurality of transistors to cause a gradual reduction in an amount of current sourced from the power supply.
[c3] The apparatus of claim 2, wherein the counter stage enables the plurality of transistors when power consumption by the integrated circuit does not need to be reduced.
[c4] The apparatus of claim 1, wherein the plurality of transistors are each one selected from the group consisting of a p-type transistor and a n-type transistor.
[c5] A circuit for reducing a rate of current change of a microprocessor, comprising: a control stage that is connected to a power terminal and a ground terminal, wherein the control stage generates a control signal; and a counter stage that inputs the control signal and a clock signal, wherein the counter stage generates a first signal to a gate terminal of a first transistor.
[c6] The circuit of claim 5, wherein the first transistor has a terminal connected to power and another terminal connected to ground, and wherein the first transistor sources current from power to ground.
[c7] The circuit of claim 5, wherein the counter stage generates a second signal to a gate terminal of a second transistor. [c8] The circuit of claim 7, wherein the second transistor has a terminal connected to power and another terminal connected to ground, and wherein the second transistor sources current from power to ground.
[c9] The circuit of claim 5, wherein the counter stage generates a last signal to a gate terminal of a last transistor.
[clO] The circuit of claim 9, wherein the last transistor has a terminal connected to power and another terminal connected to ground, and wherein the last transistor sources current from power to ground.
[ell] A method for reducing a magnitude of a rate of current change for an integrated circuit, comprising: determining when power consumption by the integrated circuit needs to be reduced; and gradually reducing an amount of current sourced by a power supply based on the determination.
[cl2] The method of claim 11, wherein gradually reducing the amount of current comprises: selectively disabling a first transistor based on the determination, wherein disabling the first transistor causes a reduction in an amount of current sourced from a power supply; and selectively disabling a second transistor based on the determination, wherein disabling the second transistor causes a reduction in the amount of current sourced from the power supply.
[cl3] The method of claim 12, wherein the determination is made by a microarchitectural stage, the micro-architectural stage comprising: selectively generating a signal to a counter stage, wherein the counter stage generates a first signal to the first transistor and a second signal to the second transistor.
[cl4] The method of claim 13, wherein the counter stage comprises at least one selected from the group consisting of a finite state machine and a counter. [cl5] The method of claim 12, further comprising: selectively disabling a last transistor based on the determination, wherein disabling the last transistor causes a reduction in the amount of current sourced from the power supply.
[cl6] The method of claim 15, wherein the determination is made by a microarchitectural stage, the micro-architectural stage comprising: selectively generating a signal to a counter stage, wherein the counter stage generates a last signal to the last transistor.
[cl7] The method of claim 15, wherein the counter stage comprises at least one selected from the group consisting of a finite state machine and a counter.
[cl8] The method of claim 15, further comprising: selectively enabling the first, second, and last transistors when power consumption by the integrated circuit does not need to be reduced.
[cl9] The method of claim 15, wherein the first, second, and last transistor can each be one selected from the group consisting of a p-type transistor and a n-type transistor.
[c20] A method for reducing a magnitude of a rate of current change for an integrated circuit, comprising: a step of determining when power consumption by the integrated circuit needs to be reduced; and a step of gradually reducing an amount of current sourced by a power supply based on the determination.
[c21] The method of claim 20, wherein the step of gradually reducing the amount of current comprises: a step of selectively disabling a first transistor based on the step of determining, wherein disabling the first transistor causes a reduction in an amount of current sourced from a power supply; and a step of selectively disabling a second transistor based on the step of determining, wherein disabling the second transistor causes a reduction in an amount of current sourced from a power supply.
[c22] The method of claim 21, wherein the step of determining is made by a microarchitectural stage, the micro-architectural stage comprising: a step of selectively generating a signal to a counter stage, wherein the counter stage generates a first signal to the first transistor and a second signal to the second transistor.
[c23] The method of claim 21 , further comprising: a step of selectively disabling a last transistor based on the step of determining, wherein disabling the last transistor causes a reduction in the amount of current sourced from the power supply.
[c24] The method of claim 21, wherein the step of determining is made by a microarchitectural stage, the micro-architectural stage comprising: a step of selectively generating a signal to a counter stage, wherein the counter stage generates a last signal to the last transistor.
[c25] The method of claim 23, further comprising: a step of selectively enabling the first, second, and last transistors when power consumption by the integrated circuit does not need to be reduced.
PCT/US2002/025849 2001-08-14 2002-08-14 Method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit WO2003017490A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP02761371A EP1421691A1 (en) 2001-08-14 2002-08-14 Method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/930,373 2001-08-14
US09/930,030 2001-08-14
US09/930,373 US6871290B2 (en) 2001-08-14 2001-08-14 Method for reducing a magnitude of a rate of current change of an integrated circuit
US09/930,030 US20030034817A1 (en) 2001-08-14 2001-08-14 Apparatus for reducing a magnitude of a rate of current change of an integrated circuit

Publications (2)

Publication Number Publication Date
WO2003017490A1 true WO2003017490A1 (en) 2003-02-27
WO2003017490A8 WO2003017490A8 (en) 2004-06-24

Family

ID=27129988

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/025849 WO2003017490A1 (en) 2001-08-14 2002-08-14 Method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit

Country Status (3)

Country Link
EP (1) EP1421691A1 (en)
CN (1) CN1541450A (en)
WO (1) WO2003017490A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116191843A (en) * 2023-04-26 2023-05-30 广东华芯微特集成电路有限公司 Gate driving circuit architecture, control method and BLDC motor driving circuit

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102968658A (en) * 2011-08-31 2013-03-13 北京中电华大电子设计有限责任公司 Compensation method for power consumption of smart card
US9013124B2 (en) * 2012-02-14 2015-04-21 Texas Instruments Incorporated Reverse current protection control for a motor
CN108241399B (en) * 2016-12-27 2021-02-02 上海华虹集成电路有限责任公司 Power consumption step suppression circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993014568A1 (en) * 1992-01-14 1993-07-22 Robert Bosch Gmbh Driver circuit
US5398318A (en) * 1989-11-02 1995-03-14 Hitachi, Ltd. High speed, low noise output buffer with non-identical pairs of output transistors
US5424669A (en) * 1993-04-29 1995-06-13 Texas Instruments Incorporated Digitally controlled output slope control/current limit in power integrated circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398318A (en) * 1989-11-02 1995-03-14 Hitachi, Ltd. High speed, low noise output buffer with non-identical pairs of output transistors
WO1993014568A1 (en) * 1992-01-14 1993-07-22 Robert Bosch Gmbh Driver circuit
US5424669A (en) * 1993-04-29 1995-06-13 Texas Instruments Incorporated Digitally controlled output slope control/current limit in power integrated circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116191843A (en) * 2023-04-26 2023-05-30 广东华芯微特集成电路有限公司 Gate driving circuit architecture, control method and BLDC motor driving circuit

Also Published As

Publication number Publication date
EP1421691A1 (en) 2004-05-26
CN1541450A (en) 2004-10-27
WO2003017490A8 (en) 2004-06-24

Similar Documents

Publication Publication Date Title
JP2625633B2 (en) How to reduce logic macro power consumption.
US8127156B2 (en) Systems and methods for control of integrated circuits comprising body biasing systems
TWI665862B (en) Fan motor driving device, driving method, cooling device and electronic device using the same
US6806726B2 (en) Semiconductor integrated circuit
JP2003330568A (en) Semiconductor integrated circuit and circuit design system
US20040255062A1 (en) Data output circuit and data output method
US7237130B2 (en) Blade server performance management method and system
WO2003017490A1 (en) Method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit
JP5215622B2 (en) Semiconductor integrated circuit and method for controlling semiconductor integrated circuit
US6871290B2 (en) Method for reducing a magnitude of a rate of current change of an integrated circuit
US6496346B1 (en) Automatic system shutdown following processor thermal condition
JPH11317653A (en) Slew rate control method and circuit including prevention of through-current
US7012459B2 (en) Method and apparatus for regulating heat in an asynchronous system
US20030034817A1 (en) Apparatus for reducing a magnitude of a rate of current change of an integrated circuit
JP2007265601A (en) Method and circuit for reducing power consumption in integrated circuit
JP2004104875A (en) Dc conversion circuit, and setting method for pause mode thereof
JPH05211432A (en) Data output circuit and semiconductor integrated circuit
JPH07236180A (en) Device for activating logical unit
US20020158684A1 (en) Noise suppression circuitry and method
US7443222B1 (en) Dynamic clock control
JP4165215B2 (en) Digital input signal processor
US6646473B1 (en) Multiple supply voltage dynamic logic
US7804331B2 (en) Semiconductor device
US6515527B2 (en) Method for smoothing dI/dT noise due to clock transitions
US20060255836A1 (en) Clock driver circuit and driving method therefor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BY BZ CA CH CN CO CR CU CZ DE DM DZ EC EE ES FI GB GD GE GH HR HU ID IL IN IS JP KE KG KP KR LC LK LR LS LT LU LV MA MD MG MN MW MX MZ NO NZ OM PH PL PT RU SD SE SG SI SK SL TJ TM TN TR TZ UA UG UZ VN YU ZA ZM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ UG ZM ZW AM AZ BY KG KZ RU TJ TM AT BE BG CH CY CZ DK EE ES FI FR GB GR IE IT LU MC PT SE SK TR BF BJ CF CG CI GA GN GQ GW ML MR NE SN TD TG

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2002761371

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 20028158695

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 2002761371

Country of ref document: EP

CFP Corrected version of a pamphlet front page

Free format text: REVISED ABSTRACT RECEIVED BY THE INTERNATIONAL BUREAU AFTER COMPLETION OF THE TECHNICAL PREPARATIONS FOR INTERNATIONAL PUBLICATION

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWW Wipo information: withdrawn in national office

Ref document number: 2002761371

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP