CN116191843A - Gate driving circuit architecture, control method and BLDC motor driving circuit - Google Patents
Gate driving circuit architecture, control method and BLDC motor driving circuit Download PDFInfo
- Publication number
- CN116191843A CN116191843A CN202310460571.2A CN202310460571A CN116191843A CN 116191843 A CN116191843 A CN 116191843A CN 202310460571 A CN202310460571 A CN 202310460571A CN 116191843 A CN116191843 A CN 116191843A
- Authority
- CN
- China
- Prior art keywords
- delay
- circuit
- module
- control
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000010355 oscillation Effects 0.000 claims abstract description 18
- 238000006243 chemical reaction Methods 0.000 claims abstract description 9
- 230000000630 rising effect Effects 0.000 claims description 25
- 239000003990 capacitor Substances 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
- H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
- H02P25/022—Synchronous motors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/28—Arrangements for controlling current
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P2207/00—Indexing scheme relating to controlling arrangements characterised by the type of motor
- H02P2207/05—Synchronous machines, e.g. with permanent magnets or DC excitation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to a grid driving circuit architecture, a control method and a BLDC motor driving circuit, wherein the grid driving circuit architecture comprises a grid control circuit, a switch array module and a delay control module, the switch array module is connected with the grid control circuit, and the delay control module is connected with the grid control circuit; the grid control circuit is configured to perform first signal processing on the received PWM signal and the delay signal of the external controller and output a first control signal to the switch array module; the delay control module is configured to output a delay signal to the gate control circuit according to the gate control driving signal; the switch array module is configured to perform second signal conversion processing on the received first control signal, and transmit a grid control driving signal to the power output circuit, so that the problem of oscillation of the grid source voltage of the MOS tube in the power output circuit is reduced or even avoided, and a feasibility condition is provided for the BLDC motor to realize optimal state operation.
Description
Technical Field
The present disclosure relates to the field of motor control technologies, and in particular, to a gate driving circuit architecture, a control method, and a BLDC motor driving circuit.
Background
A brushless direct current (BLDC) motor is a synchronous motor using a Direct Current (DC) power source, which is essentially a permanent magnet synchronous motor that takes a direct current power input and turns into a three-phase alternating current power source with an inverter, with position feedback. The brushless direct current motor has the advantages of high reliability, no reversing spark, low mechanical noise and the like, along with the increasing level of industrial automation, the demand of the emerging economy for the stepping motor is increasing, and the brushless direct current motor is penetrated into multiple economic fields and is deepened continuously, such as fields of household appliances, computers, communication equipment, office automation (printers, copiers, compound machines), industrial automation, banking equipment and the like.
The conventional BLDC control and driving system is composed of an MCU control chip, a gate driving chip, and a power output module, as shown in fig. 1. The MCU control chip outputs PWM signals to control the grid driving chip, and then the grid driving chip outputs control current I drive And I sink And switching on or switching off a power MOS tube in the power output module so as to control the operation of the BLDC motor.
The characteristics of the power MOS transistor in the BLDC system are shown in FIG. 2, wherein V gs 、V ds 、I ds Respectively representing the grid voltage, the drain voltage and the drain current of the power MOS tube, I drive For the output current of the grid drive shown in fig. 1, the grid of the power MOS tube is charged, so that the purpose of starting the power MOS tube is realized. When the power MOS tube is V gs Reaching the turn-on threshold voltage V th Thereafter, I ds Start to rise at the same time V ds Descending. V (V) gs After reaching the set maximum value, an oscillation phenomenon occurs.
Disclosure of Invention
Accordingly, it is desirable to provide a gate driving circuit architecture, a control method and a BLDC motor driving circuit for solving the problem of oscillation of the BLDC motor driving system.
In a first aspect, the present invention provides a gate driving circuit architecture, including a gate control circuit configured to perform a first signal process on a received external controller PWM signal and a delay signal, and output a first control signal to a switch array module; the switch array module is connected with the grid control circuit and is configured to perform second signal conversion processing on the received first control signal to obtain a grid control driving signal; and the delay control module is connected with the grid control circuit and is configured to feed back and output the delay signal to the grid control circuit according to the grid control driving signal.
In one embodiment, the switch array module includes N first MOS transistors, where first ends of the N first MOS transistors are connected together, second ends of the N first MOS transistors are connected together and form an output end of the gate control driving signal, and third ends of the N first MOS transistors are connected with the gate control circuit respectively.
In one embodiment, the gate control circuit includes delay modules, where the number of the delay modules is the same as the number of the first MOS transistors; the output ends of the N delay modules are connected with the third ends of the N first MOS tubes in a one-to-one correspondence manner; the input end of the delay module is connected with the delay control module and the external controller.
In one embodiment, the delay module includes a first resistor and a first capacitor, a first end of the first resistor is an input end of the delay module, a second end of the first resistor is connected with a first end of the first capacitor and forms an output end of the gate control driving signal, and a second end of the first capacitor is grounded.
In one embodiment, the gate control circuit includes delay modules, where the number of the delay modules is the same as the number of the first MOS transistors; the N delay modules are connected with the N first MOS tubes in a one-to-one correspondence manner;
the input end of the Nth delay module is commonly connected with the output end of the Nth delay module, the delay control module and the third end of the Nth first MOS tube.
In one embodiment, the delay module is a digital clock circuit configured to output the delay signal, the delay signal having the expression: dt=nt, where T is the clock period and n is the number of stall periods.
In a second aspect, an embodiment of the present invention further provides a BLDC motor driving circuit, including the above gate driving circuit architecture; the MCU controller is connected with the grid control circuit and is configured to output the PWM signal to the grid control circuit;
and the power output circuit is connected with the switch array module, and is configured to perform third signal conversion control on the received first control circuit and output a first driving signal to the motor.
In one embodiment, the power output circuit is a three-phase full-bridge circuit, and the three-phase full-bridge circuit includes a U-phase upper bridge arm switch tube, a V-phase upper bridge arm switch tube, a W-phase upper bridge arm switch tube, a U-phase lower bridge arm switch tube, a V-phase lower bridge arm switch tube, and a W-phase lower bridge arm switch tube, where the number of the gate driving circuit architectures is six, and the output ends of the six gate driving circuit architectures are respectively connected with the U-phase upper bridge arm switch tube, the V-phase upper bridge arm switch tube, the W-phase upper bridge arm switch tube, the U-phase lower bridge arm switch tube, the V-phase lower bridge arm switch tube, and the W-phase lower bridge arm switch tube.
In a third aspect, an embodiment of the present invention further provides a method for controlling a gate driving circuit architecture, where the method includes: determining a driving system oscillation factor based on the operating characteristics of the grid control driving current output by the grid control circuit and the operating characteristics of the power output circuit switching tube; the oscillation factors include the rising slope and amplitude of the gate control drive current;
according to I drive ∝W*（V GS -V TH ） 2 Determining factors influencing rising slope and amplitude of grid control driving current, wherein W refers to channel width of a first MOS tube in a switch array module, and V GS Refers to the gate-source voltage, V, of a first MOS tube in a switch array module TH Refers to the threshold voltage of a first MOS tube in a switch array module, I drive The grid control driving current is output by the grid driving circuit framework;
the channel width of the first MOS tube of the switch array module is designed in advance to change the amplitude of the grid control driving current, and the starting time of the first MOS tube of the switch array module is adjusted to control the rising slope of the grid control driving current.
In one embodiment, the specific method for controlling the rising slope of the gate control driving current by adjusting the on time of the first MOS transistor of the switch array module includes: according to I drive = I ds_1 + I ds_2 + …… + I ds_n The delay module and the delay control module are matched to conduct each first MOS tube in the switch array module in sequence, the conduction time is controlled by the delay control module, when the conduction interval time of two adjacent first MOS tubes is shorter, the current rises faster, the rising slope of the grid control driving current is larger, otherwise, the conduction interval time of two adjacent first MOS tubes is longer, the current rises shorter, and the rising slope of the grid control driving current is smaller; wherein I is ds_n Refers to the conduction current corresponding to the nth first MOS tube.
One of the above technical solutions has the following advantages and beneficial effects:
the grid driving circuit framework comprises a grid control circuit, a switch array module and a delay control module, wherein the switch array module is connected with the grid control circuit, and the delay control module is connected with the grid control circuit; the grid control circuit is configured to perform first signal processing on the received PWM signal and the delay signal of the external controller and output a first control signal to the switch array module; the delay control module is configured to output a delay signal to the gate control circuit according to the gate control driving signal; the switch array module is configured to perform second signal conversion processing on the received first control signal, and transmit a grid control driving signal to the power output circuit, so that the problem of oscillation of grid source voltage of the MOS tube in the power output circuit is reduced or even avoided, and a feasibility condition is provided for the BLDC motor to realize optimal state operation. Specifically, the single driving MOS tube in the traditional grid driving circuit is replaced by the switch array module, and the rising slope and the amplitude of the grid control driving current output by the switch array module are controlled by the grid control circuit and the delay control module, so that the purposes of reducing and eliminating the oscillation of the BLDC driving system are achieved. Compared with the method of additionally adding RC elements outside a chip in the traditional method, the grid driving circuit architecture of the application not only reduces and eliminates oscillation, but also reduces cost and has good market competitiveness.
Drawings
FIG. 1 is a schematic diagram of a conventional BLDC control and drive system;
FIG. 2 is a graph of power MOS transistor characteristics in a BLDC system;
FIG. 3 is a schematic diagram of a switch array module according to one embodiment;
FIG. 4 is a schematic diagram of a delay module in one embodiment;
FIG. 5 is a second schematic diagram of a delay module in one embodiment;
FIG. 6 is a schematic diagram of a gate driving circuit structure according to one embodiment;
FIG. 7 is a second schematic diagram of a gate driving circuit structure according to an embodiment;
fig. 8 is a schematic diagram of a BLDC driving circuit structure in one embodiment.
Reference numerals:
10 grid control circuit, 11 delay module, 20 switch array module, 30 delay control module;
200MCU controller, 300 power output circuit;
r is a first resistor and C is a first capacitor.
Detailed Description
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
As shown in fig. 8, the present embodiment provides a gate driving circuit architecture, including:
a gate control circuit 10, the gate control circuit 10 being configured to perform a first signal process on the received external controller PWM signal and the delay signal, and output a first control signal to the switch array module 20;
the switch array module 20 is connected with the grid control circuit 10, and the switch array module 20 is configured to perform second signal conversion processing on the received first control signal to obtain a grid control driving signal;
and a delay control module 30, the delay control module 30 being connected to the gate control circuit 10, the delay control module 30 being configured to feed back and output a delay signal to the gate control circuit 10 according to the gate control driving signal.
It should be noted that, the delay control module 30 adjusts the output delay signal according to the operation characteristics of the gate control driving signal, where the operation characteristics of the gate control driving signal include the current rising slope and the amplitude.
The gate driving circuit architecture in the above embodiment includes a gate control circuit 10, a switch array module 20, and a delay control module 30, where the delay control module 30 is connected to the gate control circuit 10 based on the connection of the switch array module 20 to the gate control circuit 10; the gate control circuit 10 is configured to perform a first signal process on the received external controller PWM signal and the delay signal, and output a first control signal to the switch array module 20; the delay control module 30 is configured to output a delay signal to the gate control circuit 10 according to the gate control driving signal; the switch array module 20 is configured to perform a second signal conversion process on the received first control signal, and transmit a gate control driving signal to the power output circuit 300, so as to reduce or even avoid the problem of oscillation of the gate-source voltage of the MOS transistor in the power output circuit 300, thereby providing a feasible condition for implementing the best-state operation of the BLDC motor. Specifically, the switch array module 20 replaces a single driving MOS tube in a traditional gate driving circuit, and meanwhile, the gate control circuit 10 and the delay control module 30 are added to control the rising slope and the rising amplitude of the gate control driving current output by the switch array module 20, so that the purposes of reducing and eliminating the oscillation of a BLDC driving system are achieved. Compared with the method of additionally adding RC elements outside a chip in the traditional method, the grid driving circuit architecture of the application not only reduces and eliminates oscillation, but also reduces cost and has good market competitiveness.
As shown in fig. 3, 6 and 7, this embodiment further defines, in addition to the features of the above-described embodiment: the switch array module 20 includes N first MOS transistors M1, first ends of the N first MOS transistors M1 are commonly connected, second ends of the N first MOS transistors M1 are commonly connected and form an output end of a gate control driving signal, and third ends of the N first MOS transistors M1 are respectively connected with the gate control circuit 10.
Specifically, the switch array module 20 is formed by connecting N first MOS transistors M1 in parallel, where the first MOS transistors M1 may be NMOS transistors or PMOS transistors.
As shown in fig. 6, in one embodiment: the gate control circuit 10 includes delay modules 11, and the number of the delay modules 11 is the same as that of the first MOS transistors M1; the output ends of the N delay modules 11 are connected with the third ends of the N first MOS tubes M1 in a one-to-one correspondence manner;
the output end of the nth delay module 11 is connected with the third end of the nth first MOS tube M1, and the input end of the nth delay module 11 is respectively connected with the delay control module 30 and an external controller.
As shown in fig. 4, in one embodiment, the delay module 11 includes a first resistor R and a first capacitor C, where a first end of the first resistor R is an input end of the delay module 11, a second end of the first resistor R is connected to a first end of the first capacitor C and forms an output end of the delay module 11, and a second end of the first capacitor C is grounded.
The delay module in the above embodiment is composed of a resistor and a capacitor, and has a simple structure and low cost, and the resistance and capacitance of RC can be changed by the delay control module 30 to adjust the delay.
As shown in fig. 7, in one embodiment, the gate control circuit 10 includes delay modules 11, and the number of delay modules 11 is the same as the number of the first MOS transistors M1; the N delay modules 11 are connected with the N first MOS tubes M1 in a one-to-one correspondence manner;
the input end of the nth delay module 11 is commonly connected with the output end of the (N-1) th delay module 11, the delay control module 30 and the third end of the (N) th first MOS transistor M1.
As shown in fig. 5, in one embodiment, the delay module 11 is a digital clock circuit configured to output a delay signal having the following expression: dt=nt, where T is the clock period and n is the number of stall periods.
It should be noted that, the delay signal in the present embodiment is a digital signal;
specifically, the digital signal is realized in three modes, firstly, the digital signal is set by an external MCU controller through a control program; second, by the internal circuit setting of the grid driving circuit architecture; and thirdly, the internal circuit of the grid driving circuit framework is set by an external MCU controller.
Example 2
As shown in fig. 8: the embodiment provides a BLDC motor driving circuit, which comprises the grid driving circuit framework; the MCU controller 200, the MCU controller 200 is connected with the gate control circuit 10, the MCU controller 200 is configured to output PWM signals to the gate control circuit 10; and a power output circuit 300, the power output circuit 300 being connected to the switch array module 20, the power output circuit 300 being configured to perform a third signal conversion control on the received gate control driving signal and output the first driving signal to the motor.
In one embodiment, the power output circuit 300 is a three-phase full-bridge circuit, and the three-phase full-bridge circuit includes a U-phase upper bridge arm switch tube, a V-phase upper bridge arm switch tube, a W-phase upper bridge arm switch tube, a U-phase lower bridge arm switch tube, a V-phase lower bridge arm switch tube, and a W-phase lower bridge arm switch tube, where the number of gate driving circuit architectures is six, and output ends of the six gate driving circuit architectures are respectively connected to the U-phase upper bridge arm switch tube, the V-phase upper bridge arm switch tube, the W-phase upper bridge arm switch tube, the U-phase lower bridge arm switch tube, the V-phase lower bridge arm switch tube, and the W-phase lower bridge arm switch tube.
Specifically, the number of the grid driving circuit architectures is 6, each grid driving circuit architecture respectively and correspondingly outputs grid control driving signals to the U-phase upper bridge arm switching tube, the V-phase upper bridge arm switching tube, the W-phase upper bridge arm switching tube, the U-phase lower bridge arm switching tube, the V-phase lower bridge arm switching tube and the W-phase lower bridge arm switching tube, and the oscillation phenomenon of the grid source voltage of the MOS tube of the traditional power output circuit is reduced and eliminated by controlling the characteristics of the grid control driving signals.
Example 3
The embodiment provides a control method of a gate driving circuit architecture, which is applied to the gate driving circuit architecture, and the control method comprises the following steps:
determining a system oscillation factor based on the operating characteristics of the switching array module 20 outputting the gate control driving signal and the operating characteristics of the power output circuit switching tube; the oscillation factors include the rising slope and amplitude of the gate control drive current;
according to I drive ∝W*（V GS -V TH ） 2 Determining factors influencing the rising slope and amplitude of the grid control driving current, wherein W refers to the channel width of the first MOS tube M1, V GS Refers to the gate-source voltage, V, of the first MOS transistor M1 TH Refer to the threshold voltage of the first MOS transistor M1, I drive Refers to the gate control drive current, i.e., the gate control drive signal;
the channel width W of the first MOS tube M1 of the switch array module 20 is designed in advance, so that the amplitude of the grid control driving current is changed, and the starting time of the first MOS tube M1 of the switch array module 20 is adjusted, so that the rising slope of the grid control driving current is controlled.
It should be noted that, after the first MOS transistor M1 in the switch array module 20 is turned on, the conduction current that can be provided is determined by the channel width, and when the channel width of the MOS transistor is larger, the resistivity is smaller, and the excessive current is larger; conversely, the smaller the channel width, the greater the resistivity and the smaller the current that can be passed.
The channel width W is determined when the MOS transistor is fabricated.
In one embodiment, the specific method for controlling the rising slope of the gate control driving current by adjusting the on time of the first MOS transistor (M1) of the switch array module (20) includes:
according to formula I drive = I ds_1 + I ds_2 + …… + I ds_n The switch arrays are sequentially arranged by matching the delay module 11 and the delay control module 30The first MOS transistors M1 in the column module 20 are turned on, and the turn-on time of the first MOS transistors M1 is controlled by the delay control module 30, when the shorter the turn-on interval time of two adjacent first MOS transistors M1 is, the faster the current rises, the larger the rising slope of the gate control driving current is, otherwise, the longer the turn-on interval time of two adjacent first MOS transistors M1 is, the shorter the current rises, the smaller the rising slope of the gate control driving current is; wherein I is ds_n Refers to the on current corresponding to the nth first MOS transistor M1.
Wherein the delay control module 30 may be a micro control unit.
Specifically, after each MOS transistor of the switch array module 20 is turned on, a certain magnitude of on current can be provided, and the magnitude of the on current is determined by the channel width of the MOS transistor; furthermore, by matching the delay control module 30 and the delay module 11, each first MOS tube M1 in the switch array module 20 is precisely controlled to be turned on in sequence, so as to realize the process of increasing the gate control driving current step by step and overlapping the current output by the switch array module 20, when the interval time of sequentially turning on the MOS is shorter, the slope is larger, and the current rises faster; conversely, the smaller the slope, the slower the current rise.
According to the control method of the BLDC motor driving circuit, the single driving MOS tube in the traditional grid driving circuit is replaced by the switch array module 20 with a plurality of MOS tubes connected in parallel, and the rising slope of the grid control driving current output by the switch array module 20 is controlled by the delay module 11 and the delay control module 30, so that the purpose of reducing and eliminating the oscillation of a BLDC driving system is achieved. Compared with the method of adding an RC element outside a chip in the traditional method, the method can effectively reduce and eliminate the oscillation of a driving system, simultaneously reduce the cost and improve the market competitiveness.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A gate drive circuit architecture, comprising:
a gate control circuit (10), the gate control circuit (10) being configured to perform a first signal processing on the received external controller PWM signal and the delay signal, and to output a first control signal to the switch array module (20);
the switch array module (20), the said switch array module (20) is connected with said grid control circuit (10), the said switch array module (20) is configured to carry on the second signal conversion processing to the said first control signal received, get the grid control driving signal;
-a delay control module (30), the delay control module (30) being connected to the gate control circuit (10), the delay control module (30) being configured to output the delay signal to the gate control circuit (10) in dependence of the gate control drive signal.
2. The grid driving circuit architecture according to claim 1, wherein the switch array module (20) includes N first MOS transistors (M1), first ends of the N first MOS transistors (M1) are commonly connected, second ends of the N first MOS transistors (M1) are commonly connected and form an output end of the grid control driving signal, and third ends of the N first MOS transistors (M1) are respectively connected with the grid control circuit (10).
3. The gate drive circuit architecture according to claim 2, wherein the gate control circuit (10) comprises delay modules (11), the number of delay modules (11) being the same as the number of first MOS transistors (M1); the output ends of the N delay modules (11) are connected with the third ends of the N first MOS tubes (M1) in a one-to-one correspondence manner;
the input end of the delay module (11) is connected with the delay control module (30) and the external controller.
4. A gate drive circuit architecture according to claim 3, characterized in that the delay module (11) comprises a first resistor (R) and a first capacitor (C), a first end of the first resistor (R) being an input of the delay module (11), a second end of the first resistor (R) being connected to a first end of the first capacitor (C) and forming an output of the delay module (11), a second end of the first capacitor (C) being grounded.
5. The gate drive circuit architecture according to claim 2, wherein the gate control circuit (10) comprises delay modules (11), the number of delay modules (11) being the same as the number of first MOS transistors (M1); the N delay modules (11) are connected with the N first MOS tubes (M1) in a one-to-one correspondence manner;
the input end of the N-th delay module (11) is commonly connected with the output end of the N-1-th delay module (11), the delay control module (30) and the third end of the N-th first MOS tube (M1).
6. The gate drive circuit architecture according to claim 5, wherein the delay module (11) is a digital clock circuit configured to output the delay signal, the delay signal having the expression: dt=nt, where T is the clock period and n is the number of stall periods.
7. A BLDC motor driving circuit, comprising:
the gate drive circuit architecture of any of claims 1-6;
-an MCU controller (200), the MCU controller (200) being connected to the gate control circuit (10), the MCU controller (200) being configured to output the PWM signal to the gate control circuit (10);
and a power output circuit (300), wherein the power output circuit (300) is connected with the switch array module (20), and the power output circuit (300) is configured to perform third signal conversion control on the received gate control driving signal and output a first driving signal to a motor.
8. The BLDC motor driving circuit of claim 7, wherein the power output circuit (300) is a three-phase full-bridge circuit, the three-phase full-bridge circuit includes a U-phase upper leg switching tube, a V-phase upper leg switching tube, a W-phase upper leg switching tube, a U-phase lower leg switching tube, a V-phase lower leg switching tube, and a W-phase lower leg switching tube, the number of the gate driving circuit architectures is six, and output ends of the six gate driving circuit architectures are respectively connected to the U-phase upper leg switching tube, the V-phase upper leg switching tube, the W-phase upper leg switching tube, the U-phase lower leg switching tube, the V-phase lower leg switching tube, and the W-phase lower leg switching tube.
9. A gate driving circuit architecture control method applied to the gate driving circuit architecture of any one of claims 1 to 6, characterized in that the method comprises:
determining a driving system oscillation factor based on the operating characteristics of the switching array module (20) output gate control driving signals and the operating characteristics of the power output circuit switching tubes; the oscillation factors include the rising slope and amplitude of the gate control drive current;
according to I drive ∝W*（V GS -V TH ） 2 Determining factors influencing the rising slope and amplitude of the gate control driving signal, wherein W refers to the channel width of the first MOS transistor (M1), V GS Refers to the gate-source voltage, V, of the first MOS tube (M1) TH Refers to the threshold voltage of the first MOS tube (M1), I drive Refers to gate control drive current;
the channel width W of the first MOS tube (M1) of the switch array module (20) is designed in advance, so that the amplitude of the grid control driving current is changed, and the starting time of the first MOS tube (M1) of the switch array module (20) is adjusted, so that the rising slope of the grid control driving current is controlled.
10. The method according to claim 9, wherein the specific method for controlling the rising slope of the gate control driving current by adjusting the on time of the first MOS transistor (M1) of the switch array module (20) comprises:
according to formula I drive = I ds_1 + I ds_2 + …… + I ds_n The delay module (11) and the delay control module (30) are matched to conduct each first MOS tube (M1) in the switch array module (20) in sequence, the conducting time is controlled by the delay control module (30), when the conducting interval time of two adjacent first MOS tubes (M1) is shorter, the current rising is faster, the rising slope of the grid control driving current is larger, otherwise, the conducting interval time of two adjacent first MOS tubes (M1) is longer, the current rising is shorter, and the rising slope of the grid control driving current is smaller; wherein I is ds_n Refers to the conduction current corresponding to the nth first MOS tube (M1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310460571.2A CN116191843B (en) | 2023-04-26 | 2023-04-26 | Gate driving circuit architecture, control method and BLDC motor driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310460571.2A CN116191843B (en) | 2023-04-26 | 2023-04-26 | Gate driving circuit architecture, control method and BLDC motor driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116191843A true CN116191843A (en) | 2023-05-30 |
| CN116191843B CN116191843B (en) | 2023-07-25 |
Family
ID=86446574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310460571.2A Active CN116191843B (en) | 2023-04-26 | 2023-04-26 | Gate driving circuit architecture, control method and BLDC motor driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116191843B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5424669A (en) * | 1993-04-29 | 1995-06-13 | Texas Instruments Incorporated | Digitally controlled output slope control/current limit in power integrated circuits |
| US5831303A (en) * | 1995-07-14 | 1998-11-03 | Nokia Mobile Phones, Ltd. | Field effect transistor utilizing the gate structure two-dimensionally |
| WO2003017490A1 (en) * | 2001-08-14 | 2003-02-27 | Sun Microsystems, Inc. | Method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit |
| US9484908B1 (en) * | 2015-06-19 | 2016-11-01 | Hella Corporate Center Usa, Inc. | Gate drive circuit |
| CN106357099A (en) * | 2016-09-14 | 2017-01-25 | 昂宝电子（上海）有限公司 | System and method for realizing grid drive circuit |
| CN107026561A (en) * | 2016-02-01 | 2017-08-08 | 华润矽威科技（上海）有限公司 | Gate driving circuit and method |
| CN107634649A (en) * | 2017-09-27 | 2018-01-26 | 芯洲科技（北京）有限公司 | A kind of switching device drive circuit, method and voltage conversion circuit |
| CN110011521A (en) * | 2018-01-04 | 2019-07-12 | 华润矽威科技（上海）有限公司 | Driving circuit, driving chip and its driving method |
| CN112737339A (en) * | 2020-12-16 | 2021-04-30 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit |
| KR20220113133A (en) * | 2021-02-05 | 2022-08-12 | 주식회사 현대케피코 | Apparatus for controlling switching slope of igbt gate driver |
| CN116155148A (en) * | 2023-04-25 | 2023-05-23 | 广东华芯微特集成电路有限公司 | BLDC motor control drive circuit |
-
2023
- 2023-04-26 CN CN202310460571.2A patent/CN116191843B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5424669A (en) * | 1993-04-29 | 1995-06-13 | Texas Instruments Incorporated | Digitally controlled output slope control/current limit in power integrated circuits |
| US5831303A (en) * | 1995-07-14 | 1998-11-03 | Nokia Mobile Phones, Ltd. | Field effect transistor utilizing the gate structure two-dimensionally |
| WO2003017490A1 (en) * | 2001-08-14 | 2003-02-27 | Sun Microsystems, Inc. | Method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit |
| US9484908B1 (en) * | 2015-06-19 | 2016-11-01 | Hella Corporate Center Usa, Inc. | Gate drive circuit |
| CN107026561A (en) * | 2016-02-01 | 2017-08-08 | 华润矽威科技（上海）有限公司 | Gate driving circuit and method |
| CN106357099A (en) * | 2016-09-14 | 2017-01-25 | 昂宝电子（上海）有限公司 | System and method for realizing grid drive circuit |
| CN107634649A (en) * | 2017-09-27 | 2018-01-26 | 芯洲科技（北京）有限公司 | A kind of switching device drive circuit, method and voltage conversion circuit |
| CN110011521A (en) * | 2018-01-04 | 2019-07-12 | 华润矽威科技（上海）有限公司 | Driving circuit, driving chip and its driving method |
| CN112737339A (en) * | 2020-12-16 | 2021-04-30 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit |
| KR20220113133A (en) * | 2021-02-05 | 2022-08-12 | 주식회사 현대케피코 | Apparatus for controlling switching slope of igbt gate driver |
| CN116155148A (en) * | 2023-04-25 | 2023-05-23 | 广东华芯微特集成电路有限公司 | BLDC motor control drive circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116191843B (en) | 2023-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3316461B1 (en) | Half-bridge inverter modules with advanced protection through high-side to low-side control block communication | |
| US8390241B2 (en) | Motor drive based on III-nitride devices | |
| JP2007228650A (en) | Drive circuit for power switching element | |
| WO2007007466A1 (en) | Polyphase inverter, control method therefor, blower, and polyphase current output system | |
| CN102484434B (en) | Dead-time generating circuit and motor control apparatus | |
| US9564832B2 (en) | Circuit for synchronously switching series connected electronic switches | |
| US20150124502A1 (en) | Driving apparatus for driving switching elements of power conversion circuit | |
| EP2712087B1 (en) | Semiconductor device and circuit for controlling electric potential of gate of insulated-gate type switching element | |
| JP6634329B2 (en) | Semiconductor device | |
| US11621709B2 (en) | Power module with built-in drive circuits | |
| CN116191843B (en) | Gate driving circuit architecture, control method and BLDC motor driving circuit | |
| US10530349B1 (en) | Signal transmission device and drive device | |
| US6208541B1 (en) | PWM inverter apparatus | |
| US9490688B2 (en) | Method and circuit arrangement for switching a semiconductor switch | |
| US20100213883A1 (en) | Variable-delay-time control system for a motor | |
| US11792051B2 (en) | Multi-channel digital isolator with integrated configurable pulse width modulation interlock protection | |
| US10079604B1 (en) | Staggered switching in a load driver | |
| JP4765375B2 (en) | Power converter drive circuit | |
| CN112713890A (en) | Inverter circuit of driver | |
| CN117081370B (en) | Intelligent power module IPM, control method and equipment | |
| US20220173734A1 (en) | Drive circuit and drive system | |
| CN117526916B (en) | Driving circuit and method for insulated gate bipolar transistor | |
| JP7472645B2 (en) | Power module with built-in drive circuit | |
| JP2019088078A (en) | Driver circuit and power converter | |
| WO2020031538A1 (en) | Drive circuit, and drive system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |