CN1541450A - Method and appts. for reducing magnitude of rate of current change of integrated circuit - Google Patents
Method and appts. for reducing magnitude of rate of current change of integrated circuit Download PDFInfo
- Publication number
- CN1541450A CN1541450A CNA028158695A CN02815869A CN1541450A CN 1541450 A CN1541450 A CN 1541450A CN A028158695 A CNA028158695 A CN A028158695A CN 02815869 A CN02815869 A CN 02815869A CN 1541450 A CN1541450 A CN 1541450A
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- CN
- China
- Prior art keywords
- transistor
- electric current
- power supply
- last
- reduce
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
- H03K17/163—Soft switching
- H03K17/164—Soft switching using parallel switching arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Abstract
A method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit are provided. The apparatus uses a counter stage controlled by a control stage to sequentially disable a plurality of transistors that are used to source current from a power supply. By sequentially disabling the plurality of transistors, a reduction of an amount of current occurs gradually, effectively reducing the magnitude of the rate of current change. Further, the method uses a plurality of transistors controlled by a finite state machine, such as a counter, to gradually reduce current sourced from a power supply. The finite state machine is controlled by a micro-architectural stage that determines when the integrated circuit needs to be powered down.
Description
Background of invention
Because technological improvement, integrated circuit, for example microprocessor continues to become faster and stronger.Yet speed increases and the benefit of higher data throughput must be with the original balance that becomes of power consumption increase and higher working temperature.
When a microprocessor (in technology, being called " central processing unit " or " CPU ") near or when surpassing a certain power or temperature threshold, this microprocessor must reduce power to avoid its fault or impaired.For example, if the cooling system of a microprocessor is out of order, then this microprocessor must disconnect to avoid overheated fast.Similarly, if a microprocessor extracts power in the mode that influences other computer chip parts unfriendly, then this microprocessor must reduce power to avoid undesirable influence.
But the high power nature of a microprocessor makes that reduce this microprocessor power has any problem instantaneously, and this is can cause that the power supply to computer chip is impaired because if carry out like this.The transient change amount of an electric current like this may be so high, makes a big change in voltage not only cause damaging power supply, and may damage the computer chip parts.Relation between the voltage and current that equation 1 expression in time changes changes:
V＝Z*i (1)
Here V represents voltage, and Z represents impedance, and i represents electric current.Thus, it represents that when the instantaneous decline of i V will increase on the speed that general computer chip can not be stood.
Fig. 1 represent when power to a microprocessor, or other integrated circuits are instantaneous when being increased to a desired level, electric current and the universal relation between the time (10).Especially, Fig. 1 represents the rate of change Δ i/ Δ t when electric current electric current when 10A is reduced to 5A.
Brief summary of the invention
According to one aspect of the present invention, an equipment that reduces a current change of integrated circuit rate value comprises a controlled stage, whether it depends on this power consumption of integrated circuit needs reduction and produces a control signal, and counter stage, its signal of importing this control signal and producing a plurality of orders is to a plurality of transistors, and these a plurality of source transistors are from the electric current of a power supply.
According to another aspect of the present invention, a circuit that reduces a microprocessor current changing rate comprises a controlled stage, it is connected to a power end and earth terminal, this controlled stage produces a control signal, and counter stage, it imports this control signal and a clock signal, and this counter stage produces the grid of one first signal to a first transistor.
According to a further aspect, a kind of method that reduces a current change of integrated circuit rate value comprises and determines when that power consumption of integrated circuit need reduce and determine to reduce gradually the total amount that the electric current of (source) is provided by a power supply based on this.
According to a further aspect, a kind of method that reduces a current change of integrated circuit rate value comprises the step that determines when that this integrated circuit (IC) power consumption need reduce, and based on this definite step that the total amount of the electric current that provides by a power supply is provided gradually.
Will be apparent according to other aspect and advantage of following explanation and additional claim the present invention.
Brief description of drawings
Electric current and the universal relation between the time when Fig. 1 represents the power reduction.
Fig. 2 a represents the circuit diagram by one embodiment of the invention.
Fig. 2 b represents by embodiment electric current shown in Fig. 2 a and the relation between the time.
Describe in detail
The present invention relates to reduce the method and apparatus of the current changing rate value of a microprocessor or other integrated circuits.In addition, the present invention relates to reduce the method and apparatus of a microprocessor or other integrated circuit power.In addition, the present invention relates to cool off the method and apparatus of a microprocessor or other integrated circuits.
Fig. 2 a represents an exemplary circuit figure by the embodiment of the invention.Especially, Fig. 2 a represents a little-architecture piece (being also referred to as " little-the architecture level ") (30), it produces a signal m_out control counter block (being also referred to as " counter stage ") (32), and this counter block (32) can comprise for example counter (not shown) of a finite state machine.Clock signal clk of this counter block (32) input is used for regularly and the counting purpose, produces signal C respectively
0, C
1, C
2And C
3To the first transistor (34), transistor seconds (36), the 3rd transistor (38) and the 4th transistor (40).When a specific transistor shown in Fig. 2 a was " connection ", when promptly starting, that special transistor played a current source, because it is from V
DD(42) to V
SS(44) provide electric current.When a special transistor was " ending ", when promptly forbidding, the electric current that provides by that special transistor reduced.
This counter block (32) CLK just along at C
0, C
1, C
2And C
3Go up and produce low signal continuously.But those skilled in the art will be understood in other embodiment, and counter block (32) can differently be designed.
Those technical staff of this specialty also will understand the signal that can use the varying number that is produced by this counter block (32) in other embodiments.In addition, those technical staff of this specialty will understand the transistor that can use varying number in other embodiments.In addition, it can be a heat sensor that those technical staff of this specialty will understand this little-architecture piece (30), this heat sensor when this microprocessor near or begin to be used to reduce when overheated the power of a microprocessor.
Fig. 2 b represents based on the signal of representing among Fig. 2 a and circuit in electric current and the relation between the time (46).When m_out was high level (48), this counter block (33) was at C
0, C
1, C
2And C
3The high value of last generation, thus successively the first, the second, the 3rd and last transistor (34,36,38,40) by all conversions " conducting ".In this case, this transistor (34,36,38,40) is jointly from V
DD(42) to V
SS(44) provide 10A electric current.
When m_out forwards low level (50) to, this counter block (32) CLK just along at C
0, C
1, C
2And C
3Go up and produce low value continuously.Like this, forward low level (50) to afterwards on first edge just of this CLK at m_out, this counter block (32) is at C
0(52) go up to produce a low value, thus subsequently, make the first transistor (34) be transformed into " ending ", thus reduce effectively by transistor (34,36,38,40) provide from V
DD(42) to V
SS(44) common electric current.On the next one of CLK edge just, this count block (32) is at C
1(54) produce a low value.Thus, make transistor seconds (36) be transformed into " ending " successively, thus reduce effectively by this transistor (34,36,38,40) provide from V
DD(42) to V
SS(44) common electric current.On the next one of CLK edge just, this count block (32) is at C
2(56) go up to produce a low value, thus, make the 3rd transistor (38) be transformed into " ending " successively, thus reduce effectively by transistor (34,36,38,40) provide from V
DD(42) to V
SS(44) common electric current.Forward low level (50) to afterwards at m_out, at the next one of CLK just along this counter block (32) at C
3(58) go up to produce a low value, thus, make last transistor (40) be transformed into " ending " successively, thus reduce effectively by transistor (34,36,38,40) provide from V
DD(42) to V
SS(44) common electric current.
Those technical staff of this specialty will understand no matter when forbid a transistor, be derived from V
DD(42) to V
SS(44) the total amount ratio that electric current reduces an only transistor is used to provide from V
DD(42) to V
SS(44) situation of the occasion of electric current is littler.Thus, be derived from V by little by little reducing
DD(42) to V
SS(44) electric current, current changing rate value, or Δ i/ Δ t are than to influence the situation of the occasion that this electric current reduces littler by reduce this electric current to one desired level simply instantaneously.
Advantage of the present invention can comprise one or more following aspects.In certain embodiments, owing to use a plurality of transistors to reduce power consumption, the current changing rate value of a microprocessor reduces, and this microprocessor operation is more stable, and promptly noise is littler than only with a transistor reduction power consumption time.
In certain embodiments, because the current changing rate value of a microprocessor reduces gradually rather than reduces suddenly, this microprocessor operation is faster.
In certain embodiments, reduce because a microprocessor current changing rate value reduces to substitute suddenly gradually, the chance that power supply damages reduces.
In certain embodiments, because the current changing rate value of a microprocessor reduces gradually rather than reduces suddenly, the reduction of average power consumption will be influenced.
Though relatively limited embodiment number has been described the present invention, those technical staff of this specialty will understand the embodiment that can design other and not depart from scope of the present invention disclosed herein after having had being benefited of the disclosure.Thus, scope of the present invention is only limited by additional claim.
Claims (25)
1. equipment that is used to reduce the current changing rate value of an integrated circuit comprises:
A controlled stage, whether depend on the power consumption that this integrated circuit causes needs to reduce and produce a control signal; And
A counter stage is imported this control signal and is produced a plurality of sequential signals to a plurality of transistors, and wherein these a plurality of source transistors are from the electric current of a power supply.
2. the equipment of claim 1, wherein this controller level is sequentially forbidden this a plurality of transistors, makes to reduce the electric current total amount that is derived from this power supply gradually.
3. the equipment of claim 2, when wherein the power consumption that is caused by this integrated circuit did not need to reduce, this counter stage started these a plurality of transistors.
4. the equipment of claim 1, wherein this a plurality of transistorized each be selected from by a p-transistor npn npn and the group that the n-transistor npn npn is formed.
5. one kind with the circuit that reduces a microprocessor current changing rate, comprising:
A controlled stage is connected to a power end and an earth terminal, and wherein this controlled stage produces a control signal; And
A counter stage is imported this control signal and a clock signal, and wherein this counter stage produces the gate terminal of one first signal to a first transistor.
6. the circuit of claim 5, wherein this first transistor has an end that is connected to power supply and the other end that is connected to ground, and wherein this first transistor is derived from the electric current of power supply to ground.
7. the circuit of claim 5, wherein this counter stage produces the gate terminal of a secondary signal to a transistor seconds.
8. the circuit of claim 7, wherein this transistor seconds has an end that is connected to power supply and the other end that is connected to ground, and wherein this transistor seconds is derived from the electric current of power supply to ground.
9. the circuit of claim 5, wherein this counter stage produces a last last transistorized gate terminal of signal to.
10. the circuit of claim 9, wherein this last transistor has an end that is connected to power supply and is connected to the other end on ground, wherein this last source transistor from power supply the electric current to ground.
11. a method that reduces a current change of integrated circuit rate value comprises:
Determine when that the power consumption that integrated circuit causes needs to reduce; And
Determine based on this, little by little reduce the total amount of the electric current that is derived from a power supply.
12. the method for claim 11 wherein reduces the electric current total amount gradually and comprises:
Determine based on this, optionally forbid a first transistor, forbid that wherein this first transistor makes the electric current total amount that is derived from a power supply reduce; And
Determine based on this, optionally forbid a transistor seconds, forbid that wherein this transistor seconds makes the electric current total amount that is derived from this power supply reduce.
13. the method for claim 12, wherein this determines to formulate according to a little-architecture level, and this little-architecture level comprises:
Optionally produce signal to a counter stage, wherein this counter stage produces one first signal and arrives this transistor seconds to this first transistor and a secondary signal.
14. the method for claim 13, wherein this counter stage comprises that at least one is selected from by a finite state machine and the group that counter is formed.
15. the method for claim 12 also comprises:
Determine based on this, optionally forbid a last transistor, forbid that wherein this last transistor makes the electric current total amount that is derived from this power supply reduce.
16. the method for claim 15, wherein this determines to formulate according to a little-architecture level, and this little-architecture level comprises:
Optionally produce signal to a counter stage, wherein this counter stage produces a last signal to this last transistor.
17. the method for claim 15, wherein this counter stage comprises that at least one is selected from by a finite state machine and the group that counter is formed.
18. the method for claim 15 also comprises:
When the power consumption that is caused by this integrated circuit does not need to reduce, optionally start this first, the second and last transistor.
19. the method for claim 15, wherein this first, the second and last transistor each can be to be selected from by a p-transistor npn npn and the group that the n-transistor npn npn is formed.
20. a method that reduces a current change of integrated circuit rate value comprises:
Determine when the step that the power consumption that caused by this integrated circuit need reduce; And
Determine to reduce gradually the step of the total amount of the electric current that is derived from a power supply based on this.
21. the method for claim 20, the step that wherein reduces the electric current total amount gradually comprises:
Based on the step that the determining step selectivity is forbidden a first transistor, wherein, forbid that this first transistor makes reduction be derived from the total amount of the electric current of a power supply; And
Based on the step that the determining step selectivity is forbidden a transistor seconds, wherein, forbid that this transistor seconds makes reduction be derived from the total amount of the electric current of a power supply.
22. the method for claim 21, wherein this determining step is formulated by a little-architecture level, and this little-architecture level comprises:
Optionally produce the step of signal to a counter stage, wherein this counter stage produces one first signal and arrives this transistor seconds to this first transistor and secondary signal.
23. the method for claim 21 also comprises:
Forbid a last transistorized step based on the determining step selectivity, forbid that wherein this last transistor makes reduction be derived from the total amount of the electric current of this power supply.
24. the method for claim 21, wherein this determining step is formulated by a little-architecture level, and this little-architecture level comprises:
Optionally produce the step of signal to a counter stage, wherein this counter stage produces a last signal to this last transistor.
25. the method for claim 23 also comprises:
When the power consumption that is caused by this integrated circuit does not need to reduce, optionally start this first, the second and last transistorized step.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/930,373 | 2001-08-14 | ||
| US09/930,030 US20030034817A1 (en) | 2001-08-14 | 2001-08-14 | Apparatus for reducing a magnitude of a rate of current change of an integrated circuit |
| US09/930,373 US6871290B2 (en) | 2001-08-14 | 2001-08-14 | Method for reducing a magnitude of a rate of current change of an integrated circuit |
| US09/930,030 | 2001-08-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1541450A true CN1541450A (en) | 2004-10-27 |
Family
ID=27129988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA028158695A Pending CN1541450A (en) | 2001-08-14 | 2002-08-14 | Method and appts. for reducing magnitude of rate of current change of integrated circuit |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP1421691A1 (en) |
| CN (1) | CN1541450A (en) |
| WO (1) | WO2003017490A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968658A (en) * | 2011-08-31 | 2013-03-13 | 北京中电华大电子设计有限责任公司 | Compensation method for power consumption of smart card |
| CN104126269B (en) * | 2012-02-14 | 2018-04-03 | 德克萨斯仪器股份有限公司 | Reverse-current protection for motor controls |
| CN108241399A (en) * | 2016-12-27 | 2018-07-03 | 上海华虹集成电路有限责任公司 | Power consumption step suppression circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116191843B (en) * | 2023-04-26 | 2023-07-25 | 广东华芯微特集成电路有限公司 | Gate driving circuit architecture, control method and BLDC motor driving circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03147418A (en) * | 1989-11-02 | 1991-06-24 | Hitachi Ltd | Semiconductor integrated circuit, semiconductor memory and microprocessor |
| DE4200680A1 (en) * | 1992-01-14 | 1993-07-15 | Bosch Gmbh Robert | DRIVER CIRCUIT |
| US5424669A (en) * | 1993-04-29 | 1995-06-13 | Texas Instruments Incorporated | Digitally controlled output slope control/current limit in power integrated circuits |
-
2002
- 2002-08-14 CN CNA028158695A patent/CN1541450A/en active Pending
- 2002-08-14 WO PCT/US2002/025849 patent/WO2003017490A1/en not_active Application Discontinuation
- 2002-08-14 EP EP02761371A patent/EP1421691A1/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968658A (en) * | 2011-08-31 | 2013-03-13 | 北京中电华大电子设计有限责任公司 | Compensation method for power consumption of smart card |
| CN104126269B (en) * | 2012-02-14 | 2018-04-03 | 德克萨斯仪器股份有限公司 | Reverse-current protection for motor controls |
| CN108241399A (en) * | 2016-12-27 | 2018-07-03 | 上海华虹集成电路有限责任公司 | Power consumption step suppression circuit |
| CN108241399B (en) * | 2016-12-27 | 2021-02-02 | 上海华虹集成电路有限责任公司 | Power consumption step suppression circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1421691A1 (en) | 2004-05-26 |
| WO2003017490A1 (en) | 2003-02-27 |
| WO2003017490A8 (en) | 2004-06-24 |
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| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |