WO2003015286A1 - Decodage de viterbi turbo de canaux dans des processeurs de signaux numeriques - Google Patents

Decodage de viterbi turbo de canaux dans des processeurs de signaux numeriques Download PDF

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Publication number
WO2003015286A1
WO2003015286A1 PCT/US2002/024703 US0224703W WO03015286A1 WO 2003015286 A1 WO2003015286 A1 WO 2003015286A1 US 0224703 W US0224703 W US 0224703W WO 03015286 A1 WO03015286 A1 WO 03015286A1
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Prior art keywords
trellis
time
metrics
metric
instruction
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PCT/US2002/024703
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English (en)
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Stephen J. Plante
Zvi Greenfield
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Analog Devices, Inc.
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Priority to JP2003520088A priority Critical patent/JP4193989B2/ja
Priority to EP02756941.7A priority patent/EP1417768B1/fr
Publication of WO2003015286A1 publication Critical patent/WO2003015286A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
    • H03M13/3911—Correction factor, e.g. approximations of the exp(1+x) function
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6511—Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations

Definitions

  • This invention relates to digital signal processors for wireless mobile and base station applications and, more particularly, to the use of digital signal processors for turbo and Viterbi channel decoding in wireless base stations.
  • Second and third generation wireless systems employ channel coding and decoding algorithms and spread spectrum techniques to enhance transmission reliability.
  • a convolutional coding scheme is specified for voice transmission, and a parallel concatenated convolutional coding (PCCC) scheme is specified for data transmission.
  • the convolutional encoded data is decoded using the Viterbi decoding algorithm, and the PCCC encoded data is decoded using a turbo decoding algorithm.
  • the turbo and Viterbi decoding schemes are trellis- based algorithms.
  • Viterbi and turbo decoder algorithms are extremely computational intensive.
  • the forward error correction, or channel decoding, block in a wireless base station can approach 80% of the symbol rate processing in the software radio.
  • Proposed approaches to executing these algorithms within the allotted time constraints have included the use of ASICs and the use of a hardware block having the most basic components in a digital signal processor.
  • a digital signal processor rather than an ASIC, is a desirable solution because of its software programmability.
  • no currently available digital signal processor can handle the complete chip and symbol rate processing requirement of the software radio.
  • System designers are therefore researching solutions which use a digital signal processor and an ASIC or an ASIC alone to handle the symbol rate processing.
  • the ASIC would execute the forward error correction.
  • a digital signal processor having dual computation units, wide memory buses and the ability to handle multiple tasks in parallel is disclosed in U.S. Pat. No. 5,896,543 issued April 20, 1999 to Garde.
  • the disclosed digital signal processor delivers extremely high performance, but as currently configured cannot efficiently execute the forward error correction of a wireless base station within the allotted time constraints.
  • a method for calculating metrics of a trellis function in a digital signal processor.
  • the metrics of the trellis function are calculated for selected trellis states in response to trellis state metrics for a time to and transition metrics from time to to time t ⁇ specified by a trellis instruction.
  • the calculations for each selected trellis state include adding a transition metric to a first state metric for time t 0 to provide a first value, subtracting the transition metric from a second state metric for time to to provide a second value, comparing the corresponding first and second values, and selecting the maximum of the corresponding first and second values to provide trellis state metrics for time t lt
  • the method may further comprise the step of, for each selected trellis state, adding to the maximum value a correction factor that is a function of the corresponding first and second values.
  • the step of adding a correction factor may comprise accessing a lookup table containing correction factors.
  • the trellis instruction implements a forward trellis function for calculating ⁇ trellis state metrics
  • the trellis instruction implements a reverse trellis function for calculating ⁇ trellis state metrics.
  • the trellis instruction simultaneously implements a forward trellis function for calculating ⁇ trellis state metrics and a reverse trellis function for calculating ⁇ trellis state metrics, using a single instruction, multiple data approach.
  • a method for calculating metrics of a trellis function in a digital signal processor, h response to ⁇ metrics for a time to and transition metrics from time to to time t specified by a trellis instruction, an ⁇ metric is calculated for selected trellis states for time t 1 .
  • a ⁇ metric is calculated for the selected trellis states for time t ⁇ .
  • the step of calculating an ⁇ metric for the selected trellis states may comprise the steps of, for each selected trellis state, adding a transition metric to a first ⁇ metric for time t 0 to provide a first value and subtracting the transition metric from a second ⁇ metric for time t 0 to provide a second value, for each selected trellis state, comparing the corresponding first and second values, and selecting the maximum of the corresponding first and second values for each selected trellis state to provide metrics for time t ⁇ .
  • the step of calculating a ⁇ metric for the selected trellis states may comprise the steps of, for each selected trellis state, adding a transition metric to a first ⁇ metric for time t 2 to provide a first value and subtracting the transition metric from a second ⁇ metric for time t 2 to provide a second value, for each selected trellis state, comparing the corresponding first and second values, and selecting the maximum of the corresponding first and second values for each selected trellis state to provide ⁇ metrics for time t 1 .
  • the steps of calculating an metric and calculating a ⁇ metric may each further comprise the step of, for each selected trellis state, adding to the maximum value a correction factor that is a function of the corresponding first and second values.
  • the steps of calculating an metric and calculating a ⁇ metric may be performed simultaneously.
  • a method is provided for calculating a log MAP function in a digital signal processor.
  • a log MAP instruction specifies locations of first, second, third and fourth parameters. The sum or difference of the first and second parameters is calculated to provide a first value, and the sum or difference of the third and fourth parameters is calculated to provide a second value. The maximum of the first and second values is selected. Then a correction factor that is a function of the first and second values is added to the maximum value to provide log MAP result.
  • the step of adding a correction factor may comprise accessing a lookup table containing correction factors.
  • a digital signal processor may comprise a memory for storing instructions and operands for digital signal computations, a program sequencer for generating instruction addresses for fetching selected ones of the instructions from the memory, and a computation block comprising a register file for temporary storage of operands and results, and an accelerator for performing the operations described above, either separately or in any combination.
  • the digital signal processor comprises two or more computation blocks for performing multiple operations in parallel.
  • an accelerator is provided for use in the digital signal processor computation block.
  • the accelerator comprises a first carry save adder for receiving inputs to the accelerator, a first full adder for combining sum and carry outputs of the first carry save adder, a lookup table for generating a correction factor in response to the output of the first full adder, a multiplexer for selecting one or more of the inputs to the accelerator in response to the sign of the output of the first full adder, a second carry save adder for adding one or more outputs of the multiplexer and the output of the lookup table, and a second full adder for combining sum and carry outputs of the second carry save adder.
  • the first carry save adder and the first full adder may comprise a first pipeline stage; the lookup table, the multiplexer and the second carry save adder may comprise a second pipeline stage; and the second full adder may comprise a third pipeline stage.
  • the accelerator further comprises a data selector for supplying the sum and carry outputs of the second carry sum adder to the inputs of the first carry sum adder.
  • FIG. 1 is a block diagram of a wireless base station signal chain
  • FIG. 2 is a block diagram of a turbo decoder algorithm
  • FIG. 3 is a schematic representation of an eight state trellis
  • FIG. 4 illustrates an equation for calculating ⁇ metrics of a trellis
  • FIG. 5 illustrates an equation for calculating ⁇ metrics of a trellis
  • FIG. 6 illustrates an equation for calculating log likelihood ratio of a trellis
  • FIG. 7 is a block diagram of a digital signal processor suitable for implementing channel decoders in accordance with an aspect of the invention
  • FIG. 8 is a block diagram of an embodiment of each computation block shown in the digital signal processor of FIG. 7;
  • FIG. 9 is a data flow diagram that illustrates a first embodiment of operations that may be performed in response to a trellis instruction
  • FIG. 10 is a data flow diagram that illustrates a second embodiment of operations that may be performed in response to a trellis instruction
  • FIG. 11 illustrates software code for performing turbo channel decoding in accordance with an aspect of the invention
  • FIG. 12 is a schematic block diagram that illustrates calculation of alpha metrics and beta metrics for trellis states S0-S3 in a first digital signal processor cycle
  • FIG. 13 is a schematic block diagram that illustrates calculation of alpha metrics and beta metrics for trellis states S4-S7 in a second digital signal processor cycle
  • FIG. 14 is a data flow diagram that illustrates operations performed in response to a first log MAP instruction
  • FIG. 15 is a data flow diagram that illustrates operations performed in response to a second log MAP instruction
  • FIG. 16 illustrates software code for calculating the log likelihood ratio of a trellis using the log MAP instruction
  • FIG. 17 is a schematic block diagram that illustrates hardware components used for execution of the first instruction line in the software code of FIG. 16.
  • FIG. 18 is a block diagram that illustrates an embodiment of the accelerator of FIG. 8.
  • FIG. 1 A block diagram of an example of a wireless base station signal chain is shown in FIG. 1.
  • the signal chain includes symbol rate processing 10 and chip rate processing 12. It is desirable to incorporate the symbol rate processing 10 into a digital signal processor.
  • the symbol rate processing 10 includes a CRC attachment block 20, a channel coding block 22, a rate matching block 24 and an interleaving block 26.
  • the symbol rate processing 10 includes a de- interleaving block 30, a rate determination block 32, a channel decoding block 34 and a CRC attachment block 36.
  • FEC forward error correction
  • channel decoding can approach 80% of the symbol rate processing.
  • the channel decoding block 34 may utilize a convolutional code for voice or low data rate transmission and a PCCC scheme for high data rate transmission.
  • the channel decoding block 34 may utilize a Viterbi decoding algorithm for voice and a turbo decoding algorithm for data.
  • the turbo decoder includes MAP (maximum a posteriori) decoders 40 and 42, interleaver 44 and de-interleaver 46.
  • MAP maximum a posteriori
  • Turbo codes are described, for example, by M. Valenti in "An Introduction to Turbo Codes", Dept. of Elect. Eng., Virginia Polytechnic Inst. and by W. Ryan in "A Turbo Code tutorial", New Mexico State University.
  • a single MAP decoder may be used to implement the Viterbi decoder.
  • the Viterbi algorithm is described by H. Lou in “Implementing the Viterbi Algorithm", IEEE Signal Processing Magazine, Sept. 1995, pp. 42-52.
  • the turbo and Viterbi channel decoding algorithms are trellis-based algorithms performed on blocks of received data.
  • An example of an eight state trellis typically used in wireless systems is shown in FIG. 3.
  • Associated with each trellis state is an alpha (a metric, related to the probability of being at this state from the initial point in the calculation.
  • a beta ( ⁇ ) metric is also associated with each trellis state.
  • eight metrics and eight ⁇ metrics are associated with each time point in the trellis.
  • the trellis is also characterized by gamma ( ⁇ ) transition metrics, related to the probability of going from one state at a first time point to another state at the next time point.
  • ⁇ gamma
  • alpha metrics ⁇ 0 , ⁇ ls ... ⁇ are associated with trellis states SO, SI, ... S7, respectively.
  • beta metrics ⁇ 0 , ⁇ ls ... ⁇ 7 are associated with trellis states S0, SI, ... S7, respectively.
  • transition metric ⁇ o is associated with transitions from states SO, SI, S2 and S3
  • transition metric ⁇ i is associated with transitions from states S4, S5, S6 and S7.
  • FIG. 4 An equation for calculating alpha metrics for each trellis state is shown in FIG. 4, where k represents the trellis state and s represents the time point. The last term in the equation of FIG. 4 is a correction factor that is a function of the alpha metrics.
  • FIG. 5 An equation for calculating the beta metrics for each trellis state is shown in FIG. 5. The last term in the equation of FIG. 5 is a correction factor that is a function of the beta metrics.
  • ⁇ 0 ' MAX[ ⁇ 0 + To, ⁇ 4 - To] + C 0 ' (1)
  • the alpha metrics for each state are calculated by algebraically summing, for each of two previous states from which a transition to the current state is possible, the alpha metric of the previous state and the transition metric for a transition from the previous state to the current state to provide two values. Then, the maximum of the two valves is selected. The correction factor is added to the selected maximum value. As described below, the correction factor may be obtained from a lookup table.
  • the alpha metrics may be calculated for each state in the trellis in a similar manner. Likewise, the equation of FIG. 5 may be applied in a similar manner to calculate beta metrics for each state in the trellis.
  • the calculation of the metrics of two states, each based on the metrics of two previous states, is commonly referred to as a "butterfly" calculation.
  • the log likelihood ratio is also calculated in connection with channel decoding.
  • the log likelihood ratio is the log of a ratio of the profitability of state 1 to the probability of state 0.
  • An equation for calculating log likelihood ratio is shown in FIG. 6. Calculation of the log likelihood ratio is discussed in detail below.
  • a block diagram of an example of a digital signal processor (DSP) 110 suitable for implementing features of the present invention is shown in FIG. 7.
  • the principal components of DSP 110 are computation blocks 112 and 114, a memory 116, a control block 124, link port buffers 126, an external port 128, a DRAM controller 130, an instruction alignment buffer (LAB) 132 and a primary instruction decoder 134.
  • DSP digital signal processor
  • the computation blocks 112 and 114, the instruction alignment buffer 132, the primary instruction decoder 134 and the control block 124 constitute a core processor which performs the main computation and data processing functions of the DSP 110.
  • the external port 128 controls external communications via an external address bus 158 and an external data bus 168.
  • the link port buffers 126 control external communication via communication ports 136.
  • the DSP is preferably configured as a single monolithic integrated circuit.
  • the memory 116 may include three independent, large capacity memory banks 140, 142 and 144.
  • each of the memory banks 140, 142 and 144 has a capacity of 64 K words of 32 bits each.
  • each of the memory banks 140, 142 and 144 preferably has a 128-bit data bus. Up to four consecutive aligned data words of 32 bits each can be transferred to or from each memory bank in a single clock cycle.
  • the elements of the DSP 110 are interconnected by buses for efficient, high speed operation. Each of the buses includes multiple lines for parallel transfer of binary information.
  • a first address bus 150 (MAO) intercomiects memory bank 140 (M0) and control block 124.
  • a second address bus 152 (MAI) intercomiects memory bank 142 (Ml) and control block 124.
  • a third address bus 154 (MA2) intercomiects memory bank 144 (M2) and control block 124.
  • Each of the address buses 150, 152 and 154 is preferably 16 bits wide.
  • An external address bus 156 (MAE) interconnects external port 128 and control block 124.
  • the external address bus 156 is interconnected through external port 128 to external address bus 158.
  • Each of the external address buses 156 and 158 is preferably 32 bits wide.
  • a first data bus 160 (MDO) interconnects memory bank 140, computation blocks 112 and 114, control block 124, link port buffers 126, LAB 132 and external port 128.
  • a second data bus 162 (MD1) interconnects memory bank 142, computation blocks 112 and 114, control block 124, link port buffers 126, AB 132 and external port 128.
  • a third data bus 164 (MD2) interconnects memory bank 144, computation blocks 112 and 114, control block 124, link port buffers 126, IAB 132 and external port 128.
  • the data buses 160, 162 and 164 are connected through external port 128 to external data bus 168.
  • Each of the data buses 160, 162 and 164 is preferably 128 bits wide, and external data bus 168 is preferably 64 bits wide.
  • the first address bus 150 and the first data bus 160 comprise a bus for transfer of data to and from memory bank 140.
  • the second address bus 152 and the second data bus 162 comprise a second bus for transfer of data to and from memory bank 142.
  • the third address bus 154 and the third data bus 164 comprise a third bus for transfer of data to and from memory bank 144. Since each of the memory banks 140, 142 and 144 has a separate bus, the memory banks 140, 142 and 144 maybe accessed simultaneously.
  • data refers to binary words, which may represent either instructions or operands that are associated with the operation of the DSP 110. In a typical operating mode, program instructions are stored in one of the memory banks, and operands are stored in the other two memory banks.
  • At least one instruction and two operands can be provided to the computation blocks 112 and 114 in a single clock cycle.
  • Each of the memory banks 140, 142 and 144 may be configured to permit reading and writing of multiple data words in a single clock cycle. The simultaneous transfer of multiple data words from each memory bank in a single clock cycle is accomplished without requiring an instruction cache or a data cache.
  • each of the memory banks 140, 142 and 144 preferably has a capacity of 64 K words of 32 bits each.
  • Each memory bank may be connected to a data bus that is 128 bits wide.
  • each data bus may be 64 bits wide, and 64 bits are transferred on each of clock phase 1 and clock phase 2, thus providing an effective bus width of 128 bits.
  • Multiple data words can be accessed in each memory bank in a single clock cycle. Specifically, data can be accessed as single, dual or quad words of 32 bits each.
  • quad word transfers four instructions and eight operands, each of 32 bits, can be supplied to the computation blocks 112 and 114 in a single clock cycle.
  • the number of data words transferred and the computation block or blocks to which the data words are transferred are selected by control bits in the instruction.
  • the single, dual or quad data words can be transferred to computation block 112, to computation block 114, or to both.
  • Dual and quad data word accesses improve the performance of the DSP 110 in many applications by allowing several operands to be transferred to the computation blocks 112 and 114 in a single clock cycle.
  • the ability to access multiple instructions in each clock cycle allows multiple operations to be executed in each clock cycle, thereby improving performance.
  • a block diagram of an embodiment of each of the computation blocks 112 and 114 is shown in FIG. 8.
  • a multiple port register file 200 provides temporary storage for operands and results, hi a preferred embodiment, the register file 200 has a capacity of 32 words of 32 bits each, organized as eight rows of 128 bits each.
  • the register file 200 is connected through a multiplexer and latch (not shown) to each of the data buses 160, 162 and 164 (FIG. 7). When operands are fetched from memory 116, two of the three data buses are selected, and the operands on the selected buses are supplied to the register file 200.
  • the computation block shown in FIG. 8 includes a multiplier/accumulator 210, an arithmetic logic unit (ALU) 212, a shifter 214 and an accelerator 216.
  • the multiplier/accumulator 220, the ALU 212, the shifter 214 and the accelerator 216 are capable of simultaneous execution of instructions to the extent that sufficient instructions and operands can be supplied to the computation blocks.
  • Operands are supplied from the register file 200 to multiplier/accumulator 210, ALU 210, shifter 214 and accelerator 216 on operand buses 220.
  • Results from the multiplier/accumulator 210, the ALU 212, the shifter 214 and the accelerator 216 are returned to register file 200 on result buses 222.
  • the components of the computation block are controlled by signals from a secondary instruction decoder 224, in response to a decoded instruction.
  • the computation block preferably has a pipelined architecture for improved performance.
  • Each of the computation blocks 112 and 114 in the DSP includes the accelerator 216 for enhanced performance in wireless base stations.
  • the accelerator includes registers for temporary storage of data and control values and accelerator circuitry for executing specified instructions.
  • the structure and operation of the accelerator 216 are described in detail below. -lilt will be understood that the DSP 110 is described by way of example only. Features of the present invention may be implemented in different digital signal processor architectures.
  • a data flow diagram of the operations performed by each accelerator in response to an ACS, or trellis, instruction is shown in FIG. 9.
  • a high data word, such as an alpha metric or a beta metric, in a register pair TRmd is supplied to a subtracting unit 250 and to a summing unit 252.
  • a low data word in register pair TRmd is supplied to a subtracting unit 254 and to a summing unit 256.
  • a high data word in a register pair TRnd is supplied to a summing unit 258 and to a subtracting unit 260.
  • a low data word in register pair TRnd is supplied to a summing unit 262 and to a subtracting unit 264.
  • a high data word in a register Rm which may be a gamma transition metric, is supplied to subtracting unit 250, summing unit 252, summing unit 258 and subtracting unit 260.
  • a low data word in register Rm is supplied to subtracting unit 254, summing unit 256, summing unit 262 and subtracting unit 264.
  • the outputs of subtracting unit 250 and summing unit 258 are supplied to a MAX/TMAX unit 270.
  • the outputs of summing unit 252 and subtracting unit 260 are supplied to a MAX/TMAX unit 272.
  • the outputs of subtracting unit 254 and summing unit 262 are supplied to a MAX/TMAX unit 274.
  • the outputs of summing unit 256 and subtracting unit 264 are supplied to a MAX/TMAX unit 276.
  • the outputs of MAX/TMAX units 270, 272, 274 and 276 are stored in a quad register TRsq.
  • the MAX/TMAX units 270, 272, 274 and 276 each perform one of two functions that may be specified in the trellis instruction.
  • the maximum of the two inputs is selected and is stored in quad register TRsq.
  • the maximum of the two inputs is selected and a correction value is added to the selected maximum value.
  • the sum is stored in quad register TRsq.
  • the correction factor is a function of the two inputs to the MAX/TMAX unit. As described below, the correction factor can be determined from a lookup table.
  • the MAX/TMAX units 270, 272, 274 and 276 each provide an output bit to a bit selection register pair THRs. Each output bit indicates the input that was selected as the maximum value.
  • each accelerator performs two 32-bit butterfly calculations of a trellis in response to a single trellis instruction.
  • each accelerator performs four 16-bit butterfly calculations in response to a single trellis instruction, hi FIG. 10, register pair TRmd and register pair TRnd each contain four 16-bit data values, such as alpha metrics or beta metrics, and register Rm contains four 8-bit data values, such as transition metrics.
  • the data values are supplied to eight subtracting units, 290, etc. and eight summing units 292, etc., and the outputs of the subtracting units and the summing units are supplied to eight MAX units 294, etc.
  • subtracting unit 290 receives data word S3 from register pair TRmd and data word B3 from register Rm.
  • Summing unit 292 receives data word S3 from register pair TRnd and data word B3 from register Rm. The outputs of subtracting unit 290 and summing unit 292 are supplied to MAX unit 294. The MAX unit 294 selects the maximum of the two inputs and stores the selected maximum value in quad register TRsq. The TMAX option is not included in the embodiment of FIG. 10. The MAX units also supply an output bit to register pair THRs to indicate which input was selected. The remaining units in FIG. 10 operate in the same manner to provide four 16-bit butterfly calculations of a trellis in response to a single trellis instruction. An example of software code for calculating alpha metrics and beta metrics of a trellis function is shown in FIG. 11.
  • each ACS instruction specifies the calculations for two trellis butterfly calculations as shown in FIG. 9.
  • the ACS instruction is executed in computation blocks 112 and 114 (FIG. 7) to provide a total of four butterfly calculations.
  • the instructions are grouped in pairs in FIG. 11 , with a first instruction calculating alpha metrics and beta metrics for the first four states of the trellis at a given time point and the second instruction calculating alpha metrics and beta metrics for the last four states of the trellis at the given time point.
  • the calculations for a turbo channel decoder are performed using two instructions per time point in the trellis.
  • FIG. 11 illustrates a loop containing the operations for calculating metrics for four time points in the trellis. Operations in each instruction line of FIG. 11 are performed simultaneously by the digital signal processor.
  • the first instruction may calculate alpha metrics for the eight states of the trellis at a given time point
  • a second instruction may calculate beta metrics for the eight states of the trellis at the given time point.
  • TRl 1 :8 corresponds to quad register
  • TR5:4 and TR1:0 correspond to register pair TRmd and register pair TRnd, respectively.
  • the register sR24 corresponds to register Rm in FIG. 9. It will be understood that the instruction may be executed in both computation units with different data values to perform four butterfly calculations in response to a single ACS, or trellis, instruction.
  • the first instruction line in FIG. 11 further specifies that the data values in registers TR7:4 are moved to registers R7:4 in register file 200 (FIG. 8).
  • the first instruction line specifies memory load operations to registers xR3:0 in computation unit 112 and registers yR3:0 in computation unit 114. The execution of the first two instruction lines in the software code of FIG.
  • FIG. 12 illustrates calculation of alpha metrics and beta metrics for trellis states S0-S3 in a first cycle of DSP 110
  • FIG. 13 illustrates calculation of alpha metrics and beta metrics for trellis states S4-S7 in a second cycle of DSP 110.
  • an accelerator circuit 300 in computation block 112 receives data values from a register pair TR5 :4, a register pair TRl :0 and a register sR24 and supplies output data values to a quad register TRl 1 :8.
  • an accelerator circuit 302 in computation block 114 receives data values from a register pair TR5:4, a register pair TRl :0 and a register sR24 and supplies output data values to a quad register TRl 1:8.
  • the registers shown in FIG. 12 correspond to the registers specified by the ACS instruction in the first instruction line of FIG. 11.
  • the TR registers are located in each accelerator 216 (FIG. 8) and the R registers are located in each register file 200.
  • Register pair TR5:4 in FIG. 12 corresponds to register pair TRmd in FIG. 9, and register pair TRl :0 corresponds to register pair TRnd.
  • register sR24 in FIG. 12 corresponds to register Rm in FIG. 9, and quad register TRl 1:8 corresponds to quad register TRsq in FIG. 9.
  • FIG. 12 illustrates SLMD operation, where a single instruction is executed by two or more execution units, such as accelerator circuits 300 and 302, with different data.
  • the first instruction line of FIG. 11 calculates the alpha metrics and the beta metrics for trellis states S0-S3.
  • accelerator circuit 300 calculates alpha metrics ad, ad, ad and ad based on the values of ⁇ 5 and OL contained in register pair TR5:4, the values of a ⁇ and OQ contained in register pair TRl :0 and the values of ! and 0 contained in register sR24.
  • accelerator circuit 302 calculates beta metrics ⁇ d, ⁇ , ⁇ d, and ⁇ d based on the values of /3 5 and /3 4 contained in register pair 5:4, the values of ⁇ ⁇ and ⁇ contained in register pair TRl :0 and the values of j ⁇ and 7 0 contained in register sR24.
  • Accelerator circuit 300 calculates alpha metrics ad, ad, ad and ⁇ 7 ' based on the values of O] and Qfe contained in register pair TR7 : 6, the values of ⁇ 3 and ⁇ contained in register pair TR3:2 and the values of ⁇ and 7 0 contained in register sR25.
  • accelerator circuit 302 calculates beta metrics ⁇ d, ⁇ d, ⁇ d and ⁇ d based on the values of ⁇ and jS 6 contained in register pair TR7:6, the values of 3 and ⁇ 2 contained in register pair TR3:2 and the values of j ⁇ and 7 0 contained in register sR25.
  • the accelerator circuits 300 and 302 perform four butterfly calculations in a first DSP cycle as shown in FIG. 12 and four butterfly calculations in a second DSP cycle as shown in FIG. 13, thereby calculating the complete alpha metrics and beta metrics for the eight trellis states in two cycles of the digital signal processor.
  • the software code of FIG. 11 calculates the alpha metrics and the beta metrics for four time points of the trellis, hi the embodiment of FIGs.
  • accelerator registers TR0:7 in computation block 112 contain alpha metrics for trellis states S0-S7 at a first time point and accelerator registers TR8:15 contain the alpha metrics for trellis states S0-S7 at a second time point.
  • accelerator registers TR0:7 in computation block 114 contain beta metrics for trellis states S0-S7 at a first time point and accelerator registers TR7: 15 contain beta metric for trellis states S0-S7 at a second time point.
  • a data flow diagram that illustrates operations performed in response to a first type of log MAP instruction is shown in FIG. 14.
  • Data values are held in register pairs TRmd and TRnd and quad register Rmq. Each data value is 32 bits in the example of FIG. 14.
  • the data values may represent alpha metrics, beta metrics or transition metrics.
  • a summing unit 330 receives the high data word from register pair TRmd and the first data word from quad register Rmq.
  • a summing unit 332 receives the low data word from register pair TRmd and the second data word from quad register Rmq.
  • a summing unit 334 receives the high data word from register pair TRnd and the third data word from quad register Rmq.
  • a summing unit 336 receives the low data word from register pair TRnd and the fourth data word from quad register Rmq.
  • a TMAX unit 340 receives the outputs of summing units 330 and 334.
  • a TMAX unit 342 receives the outputs of summing units 332 and 336.
  • Each of the TMAX units 340 and 342 selects the maximum of its two inputs and adds a correction factor to the selected maximum value.
  • the correction factor is a function of the two input values and may be implemented as a lookup table.
  • the outputs of TMAX units 340 and 342 are stored in quad register TRsd.
  • the instruction illustrated in FIG. 14 adds the data values contained in quad register Rmq to the respective data values contained in register pairs TRmd and TRnd, selects the maximum of the outputs of two summing units and adds a correction factor to the selected maximum value.
  • FIG. 15 A data flow diagram that illustrates operations performed in response to a second type of log MAP instruction is shown in FIG. 15. Like elements in FIGs. 14 and 15 have the same reference numerals. The operations shown in FIG. 15 are similar to those shown in FIG. 14, except that summing units 330, 332, 334 and 336 of FIG. 14 are replaced with subtracting units 350, 352, 354 and 356, respectively. Thus, TMAX unit 340 receives the outputs of subtracting units 350 and 354, and TMAX unit 342 receives the outputs of subtracting units 352 and 356.
  • the instruction illustrated in FIG. 15 subtracts the data values contained in quad register Rmq from the data values contained in register pairs TRmd and TRnd, selects the maximum of the outputs of two subtracting units and adds a correction factor to the selected maximum value.
  • FIG. 16 An example of software code for calculating the log likelihood ratio of a trellis function is shown in FIG. 16.
  • the code is implemented using TMAX instructions, which perform the operations shown in FIGs. 14 and 15 and described above.
  • each TMAX instruction specifies calculations for two log MAP calculations as shown in FIG. 14 or FIG. 15.
  • the TMAX instruction is executed in computation blocks 112 and 114 (FIG. 7) to provide a total of four log MAP calculations.
  • TR1:0 and TR3:2 correspond to register pair TRmd and register pair TRnd, respectively, in FIG. 14.
  • R9:8 and Rl 1 :10 correspond to quad register Rmq in FIG. 14.
  • the data values contained in the specified registers are processed as shown in FIG. 14 or FIG. 15 and described above. It will be understood that the instruction may be executed in both computation units with different data values to perform four log MAP calculations in response to a single TMAX instruction.
  • the execution of the first instruction line in the software code of FIG. 16 is described with reference to FIG. 17. As shown in FIG.
  • accelerator circuit 300 in computation block 112 receives data values from register pairs TRl :0, R9:8, TR3:2 and Rl 1 : 10, and supplies output data values to register pair TR9:8.
  • accelerator circuit 302 in computation block 114 receives data values from register pairs TRl :0, R9:8, TR3:2 and Rl 1:10, and supplies output data values to register pair TR9:8.
  • Each of accelerator circuits 300 and 302 performs the operations shown in FIG. 14 or FIG. 15, as specified by the instruction.
  • each accelerator circuit 300, 302 (FIGs. 12, 13 and 17) is shown in FIG. 18.
  • the accelerator circuit has a pipeline architecture, including a first pipeline stage 400, a second pipeline stage 402 and a third pipeline stage 404.
  • the first and second pipeline stages 400 and 402 are connected through stage registers 410 and 412, and the second and third pipeline stages 402 and 404 are connected through a stage register 414.
  • First stage 400 includes an exclusive OR gate 420, a four input carry save adder 424 and a 32-bit adder 426.
  • Second stage 402 includes a multiplexer 430, a lookup table 432 and a three input carry save adder 434.
  • Third stage 404 includes a 32-bit adder 440.
  • a bypass result output by register 414 is coupled through a multiplexer 442 to inputs OP1 and OP2 to execute instructions in two pipeline phases as described below.
  • the accelerator circuit shown in FIG. 18 may be used to execute the ACS instruction.
  • the ACS instruction performs the following operation.
  • the circuit determines whether the value of expression (4) is positive or negative.
  • the value of expression (4) is positive, the first term within parentheses in expression (3) is the maximum value, and when this value is negative, the second term within parentheses in expression (3) is the maximum value.
  • the data value in register TRmd is supplied to inputs OP1 and OP2, the data value in register TRnd is supplied to input OP3 and the data value 2Rm is supplied to input OP4.
  • the output of 32-bit adder 426 represents the value of expression (4) above. This value is used to access a correction factor in lookup table 432.
  • the sign of the output of 32-bit adder 426 is used as a control signal for multiplexer 430, thereby selecting TRmd and Rm or TRnd and Rm.
  • the selected values and the output of lookup table 432 are supplied to inputs of carry save adder 434.
  • the output of 32-bit adder 440 represents the selected maximum yalue plus the correction factor C provided by lookup table 432.
  • the output of carry save adder 434 may be supplied to inputs OP1 and OP2 of carry save adder 424.
  • the carry output of adder 424 is supplied through multiplexer 442 to input OP1 and the sum output of adder 424 is supplied through multiplexer 442 to input OP2.
  • the bypass function is not utilized and the register input is supplied tlirough multiplexer 442 to input OP1. hi cases where the correction factor is not utilized in the ACS instruction, the output of lookup table 432 is zero.
  • the accelerator circuit shown in FIG. 18 may be used to execute the TMAX instruction.
  • the TMAX instruction performs the following operation.
  • the circuit determines whether the value of expression (6) is positive or negative.
  • the value in register TRmd is supplied to input OP1
  • the value in register Rml is supplied to input OP2
  • the value in register TRnd is supplied to input OP3
  • the value in register Rm2 is supplied to input OP4.
  • the output of 32 bit-adder 426 is used to access lookup table 432 and the sign of the output of adder 426 is used to control multiplexer 430.
  • the multiplexer 430 selects the maximum value and supplies the maximum value to carry save adder 434.
  • the adder 434 adds the selected maximum value and the correction value from lookup table 432 to provide an output result.

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Abstract

L'invention concerne un processeur de signaux numériques (110) conçu pour exécuter le décodage de Viterbi turbo de canaux dans des systèmes sans fil. Les blocs de calcul (112, 114) du processeur de signaux numériques (110) sont pourvus d'un accélérateur qui permet d'exécuter les instructions associées aux calculs en treillis. Une instruction ACS exécute les calculs en trellis des métriques alpha et bêta. Plusieurs calculs papillons peuvent être réalisés en réaction à une seule instruction. Une instruction TMAX est utilisée pour calculer le logarithme du rapport de vraisemblance du treillis.
PCT/US2002/024703 2001-08-06 2002-08-06 Decodage de viterbi turbo de canaux dans des processeurs de signaux numeriques WO2003015286A1 (fr)

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JP2003520088A JP4193989B2 (ja) 2001-08-06 2002-08-06 デジタル信号プロセッサにおける高性能ターボチャンネル復号およびＶｉｔｅｒｂｉ（ビタビ）チャンネル復号
EP02756941.7A EP1417768B1 (fr) 2001-08-06 2002-08-06 Decodage de canal turbo et viterbi dans des processeurs numeriques de signal

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US09/923,225 2001-08-06
US09/923,225 US7661059B2 (en) 2001-08-06 2001-08-06 High performance turbo and Viterbi channel decoding in digital signal processors

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US20030028845A1 (en) 2003-02-06
CN100336305C (zh) 2007-09-05
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US7661059B2 (en) 2010-02-09
EP1417768B1 (fr) 2013-05-29
CN1554152A (zh) 2004-12-08
EP1417768A4 (fr) 2006-10-18
JP2004538704A (ja) 2004-12-24

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