WO2003007478A2 - Verfahren und einrichtung zum erzeugen von mobilfunksignalen - Google Patents
Verfahren und einrichtung zum erzeugen von mobilfunksignalen Download PDFInfo
- Publication number
- WO2003007478A2 WO2003007478A2 PCT/DE2002/001899 DE0201899W WO03007478A2 WO 2003007478 A2 WO2003007478 A2 WO 2003007478A2 DE 0201899 W DE0201899 W DE 0201899W WO 03007478 A2 WO03007478 A2 WO 03007478A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- dds
- frequency
- modulator
- fout
- control word
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 8
- 230000005540 biological transmission Effects 0.000 claims description 19
- 230000006870 function Effects 0.000 claims description 5
- 230000001131 transforming effect Effects 0.000 claims description 5
- 230000009466 transformation Effects 0.000 claims description 4
- 239000008186 active pharmaceutical agent Substances 0.000 claims description 3
- 238000011144 upstream manufacturing Methods 0.000 claims description 2
- 230000004044 response Effects 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000000737 periodic effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0983—Modifications of modulator for regulating the mean frequency using a phase locked loop containing in the loop a mixer other than for phase detection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0941—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation at more than one point in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0966—Modifications of modulator for regulating the mean frequency using a phase locked loop modulating the reference clock
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/12—Indirect frequency synthesis using a mixer in the phase-locked loop
Definitions
- the present invention relates to a method for generating mobile radio signals using a DDS (direct digital frequency synthesis) and a modulator, comprising the steps:
- Mobile radio signals are transmitted as RF signals with a specific transmission frequency from a mobile station to a base station.
- a desired frequency for example an RF transmission frequency in the range of 900 or 1800/1900 MHz, as used in the currently common GSM standard - it is customary to mix, multiply or divide basic Winning frequencies.
- the base frequencies are generally derived from a quartz oscillator serving as a frequency standard, which oscillates stably at 26 MHz, for example. This basic frequency is used in the generation of the mobile radio signals immediately or after modification.
- an intermediate frequency is generated from the base frequency by means of a DDS (direct digital frequency synthesis), which is then processed further.
- the DDS is controlled via a DDS control word and a DDS clock frequency, the generation of the intermediate frequency basically going back to a counting process carried out in the DDS.
- a counter is incremented by the control word in time with the DDS clock frequency until the counter reaches an invariant maximum value which is inherent in the DDS (Phase battery width), whereupon it is reset again with an initial value which corresponds to the overflow of the previous counting cycle.
- the maximum value reached by the counter or the incrementation of the counter is used to generate a signal with the intermediate frequency. This signal therefore depends on the DDS clock frequency and the control word.
- Intermediate frequency output signal is transformed with a downstream modulator, for example an offset phase locked loop (O-PLL), in the range of mobile radio transmission frequencies.
- a downstream modulator for example an offset phase locked loop (O-PLL)
- O-PLL offset phase locked loop
- two oscillators are required, one of which provides a reference frequency, which flows into the control of a further voltage-controlled transmission oscillator.
- one goal in the design of the circuits is to use as few oscillators as possible, since these disrupt the circuit performance, for example through harmonic generation, crosstalk or the like. It is therefore an object of the present invention to provide a method of the type described in the introduction with which the number of oscillators required can be reduced.
- a method for generating mobile radio signals using a DDS and a modulator comprising the steps: A) generating an intermediate frequency by driving the DDS with a DDS control word and a DDS clock frequency and B) transforming the intermediate frequency to one Transmission frequency of the mobile radio signals using the modulator as a function of a reference frequency of the modulator. It is provided according to the invention that the reference frequency of the modulator - unchanged or divided by a division factor - is used as the DDS clock frequency, the DDS control word being selected to generate the intermediate frequency such that it compensates for fluctuations in the reference frequency of the modulator.
- the reference frequency of the modulator downstream of the DDS As the DDS clock frequency, it is possible to omit the oscillator assigned to the DDS for supplying the clock frequency. This measure simplifies the construction of a corresponding circuit and improves the circuit performance and its reproducibility.
- the problem with the solution according to the invention arises that the reference frequency of the modulator can fluctuate, in particular if the reference frequency of the modulator is generated by a channel synthesizer for generating regularly changing frequency channels for the mobile radio signals.
- the current DDS control word is selected in such a way that, in addition to the information for generating a desired intermediate frequency, it also contains information by means of which the fluctuations the reference frequency of the modulator can be compensated.
- the invention thus shows a way in which, by simplifying the circuit of a high-frequency transmitter module, the reference frequency of a modulator connected downstream of the DDS can be used to generate the DDS clock frequency.
- the reference frequency of the modulator in the channel synthesizer is generated from a variable output frequency of a voltage-controlled oscillator by transformation to the reference frequency.
- the transformation to the reference frequency can be carried out by a synthesizer phase locked loop (PLL).
- the DDS control word must be determined in accordance with the current reference frequency of the modulator.
- the following relationship must be specified:
- N is the phase battery width of the DDS.
- control word S With a constant phase battery width N of the DDS, the control word S must therefore be calculated from the desired intermediate frequency and the current clock frequency, which is directly dependent on the reference frequency of the modulator. The calculation can be made possible with relatively little hardware expenditure.
- the DDS control word is determined from a previously stored table as a function of the current DDS clock frequency and the desired intermediate frequency. This variant of the invention is selected, for example, when a sufficient amount of storage space is available inexpensively.
- the DDS control word is generated from an output signal of a further modulator, in particular a GMSK modulator.
- the DDS control word contains information on frequency modulation by the further modulator, on the intermediate frequency and on compensating for the fluctuation in the reference frequency of the modulator.
- the method according to the invention is inherently independent of the type of further modulator, so that other types of modulators can also be used instead of a GMSK modulator.
- the invention further relates to a device for generating mobile radio signals, in particular according to the method of the type described above, comprising: a DDS (direct digital frequency synthesis) for generating an intermediate frequency from a DDS control word and a DDS clock frequency and - a modulator for transforming the Intermediate frequency to a transmission frequency of the mobile radio signals depending on a reference frequency of the modulator.
- a DDS direct digital frequency synthesis
- the DDS clock frequency is derived from the reference frequency of the modulator and that the DDS control word is selected in accordance with the reference frequency of the modulator.
- a channel synthesizer can be provided for generating frequency channels of the mobile radio signals, the output frequency of the channel synthesizer - unchanged or divided by a division factor - being fed to the modulator as the reference frequency and the DDS as the DDS clock frequency. Furthermore, it can be provided according to the invention that the channel synthesizer has an oscillator, preferably a voltage-controlled oscillator, and a synthesizer phase locked loop connected downstream of this.
- a frequency divider can be provided for dividing the reference frequency of the modulator down to the desired DDS clock frequency.
- This can be a conventional frequency divider or another DDS.
- the DDS control word can be calculated or read from a previously stored table.
- the device according to the invention can therefore have a calculation unit for calculating the DDS control word or a memory unit for storing and reading out a table which contains the DDS control word as a function of the current DDS clock frequency and the desired intermediate frequency.
- the modulator is designed as a phase locked loop, in particular as an offset PLL. This leads to a circuit concept for transforming up the intermediate frequency that can be easily integrated and implemented cost-effectively.
- the device according to the invention comprises a further modulator, in particular a GMSK modulator, which is connected upstream of the DDS for generating a DDS control word.
- the device according to the invention can be controlled by a higher-level control unit, which acts, for example, on the further modulator, the DDS, and on the channel synthesizer.
- FIG. 1 shows a functional block representation which shows one possibility of realizing the method according to the invention
- FIG. 2 shows a functional block view of the transmission circuit of an integrated high-frequency transmission
- a circuit arrangement according to the invention is generally designated 10.
- This includes a DDS (direct digital frequency synthesis device) 12, which is followed by a modulator designed as an offset PLL (offset phase locked loop) 14.
- a signal with a reference frequency fref is fed into the offset PLL 14 by a channel synthesizer 16 via the line 18.
- This signal with the reference frequency f re f is further branched off via the line 20 and fed to a frequency divider 22.
- the frequency f re f is divided down by a division factor N, so that a signal with a frequency r clk-DDS is obtained, which is fed via line 24 to the DDS 12 as a clock signal.
- N fclk-DDS
- the device according to the invention for generating mobile radio signals works as follows:
- a control word S is fed to the DDS via a line 26 and a clock signal with a clock frequency f c ik_ DDS is fed via a line 24.
- a periodic signal with the intermediate frequency fout-DDS ' for example of 20 MHz, is generated in the DDS 12 in a manner known per se. This is done by incrementing a counter with a predetermined maximum count value (phase battery width) in each clock cycle predetermined by the clock frequency fclk-DDS by the respectively specified control word S until the maximum count value (phase battery width) is reached or exceeded. The counter is then reset, the value by which the maximum count value was exceeded during incrementation being adopted for a renewed increment after the reset. The counter is then incremented again. The progress of the incrementation or the reaching of the maximum value is used to generate a periodic signal with the intermediate frequency fout-DDS.
- This periodic signal with the intermediate frequency fclk-DD S is then stepped up via the offset PLL circuit 14 to a transmission frequency fout-RF.
- the phase difference between the signal output via line 30 by the DDS with the intermediate frequency fout-DD S and the comparison signal output on line 32 to the phase detector 28 is first detected in a phase detector 28.
- This comparison signal is obtained by mixing the mobile radio output signal with the frequency f Q ut-RF and the reference signal with the frequency f re f via a mixer 34.
- the signal output by the phase detector 28 via the line 36 is fed to a charge pump 38, via which a loop filter 42 is controlled via the line 40.
- the output signal of the loop filter 42 is output via the line 44 for driving a voltage-controlled oscillator 46, the center frequency of which is, for example, 1800 MHz.
- one and the same oscillator namely the oscillator 48 assigned to the channel synthesizer 16 is ultimately used to generate the reference signal for the offset PLL 14 and to generate the clock signal for the DDS 12. Its output frequency is stepped up to the reference frequency f re f via a further phase locked loop 50.
- FIG. 2 now shows an application for the circuit according to the invention according to FIG. 1.
- the same reference symbols are used for the same or similar components as were described in FIG. 1.
- FIG. 2 shows a schematic illustration of a transmit / receive module 52, only the circuit concept relevant to the transmission of mobile radio signals being shown. However, it should be pointed out that there is a connection via line 54 to reception mixers and thus to the circuit parts relevant for the reception of mobile radio signals.
- Figure 2 now shows - partly highlighted with dashed lines - the three essential components of the invention, namely the DDS 12, the offset PLL 14 and the channel synthesizer 16. Furthermore, Figure 2 shows how these components in the circuit concept of the transmit / receive module 52 are involved.
- a signal with a fundamental frequency fbase of, for example, 26 MHz is fed into the circuit via a line 58.
- this is fed to a modulator 60 via a line 62, the frequency of which is divided in advance by means of a frequency divider 64 with a division factor M, for example to a frequency of 2.16 MHz.
- the modulator 60 is controlled by a control unit 68 via a line 66.
- the modulator 60 is, for example, a GMSK modulator.
- the control unit 68 also controls an adder 72 via a line 70, which adds an output signal from the modulator 60 and an output signal from the control unit 68 to the control word S, which in turn is fed to the DDS 12 via the line 26.
- the signal with the base frequency fbase is also fed to the phase locked loop PLL 50 of the channel synthesizer 16 as a reference signal.
- the PLL 50 interacts in the manner already described with reference to FIG. 1 with the voltage-controlled oscillator 48, which for example outputs a signal with a frequency of 3.6 GHz.
- a loop filter 70 is connected downstream of the oscillator 48.
- the output signal of the PLL 50 with the reference frequency f re f is fed to the offset PLL 14 on the one hand via the line 18 and on the other hand fed to the frequency divider 22 via the line 20.
- the reference frequency quenz f re f divided by means of the frequency divider 22 with the division factor N to the clock frequency f c lk-DDS, which is supplied via line 24 to the DDS 12 as the frequency of the clock signal.
- the DDS 12 Based on the control word S fed in via line 26 and the clock frequency f c lk-DDS e ⁇ - n signal input via line 24, the DDS 12 generates the signal with the intermediate frequency fout-DD S 'which the offset PLL 14 uses line 30 is fed.
- This signal with the intermediate frequency fout-DS is processed as described above with reference to FIG. 1 in the PLL 14, more precisely via its components phase detector 28, charge pump 38, loop filter 42 and oscillator 46.
- two oscillators are provided in the offset PLL 14, namely the oscillator 46 and the oscillator 74, the oscillator 46 having a center frequency such that these transmit frequencies in the range of 1800 or 1900 MHz, whereas the oscillator 74 is designed such that it has a center frequency in the range of 900 MHz.
- Such provision of two oscillators with these frequency ranges is required, for example, for the operation of a mobile phone in three different GSM networks.
- the reference frequency f re f output via the line 18 is first divided down via a variably adjustable frequency divider 76 before it is fed to the offset PLL 14 and fed into the mixer 34 ,
- the output signal with the transmission frequency fout-RF is fed and amplified via line 78 to a power amplifier 80 of the transmission output stage. From this the transmission signal fed to an antenna 82 and emitted in the form of electromagnetic waves.
- FIG. 2 shows one possibility of how the circuit concept according to the invention can be integrated in a transmit / receive module 52 for a mobile radio terminal in such a way that, while simplifying the circuit concept, it can be reproduced well at high circuit performance - is settled.
- the reference frequency f re f of the channel synthesizer 16 is used to both control the offset PLL 14 and to clock the DDS 12 after division by means of the frequency divider 22.
Landscapes
- Transmitters (AREA)
- Amplitude Modulation (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Transceivers (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/483,868 US20040176045A1 (en) | 2001-07-10 | 2002-05-23 | Method and device for producing mobile radio signals |
EP02745084A EP1405418A2 (de) | 2001-07-10 | 2002-05-23 | Verfahren und einrichtung zum erzeugen von mobilfunksignalen |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10133514.8 | 2001-07-10 | ||
DE10133514A DE10133514A1 (de) | 2001-07-10 | 2001-07-10 | Verfahren und Einrichtung zum Erzeugen von Mobilfunksignalen |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2003007478A2 true WO2003007478A2 (de) | 2003-01-23 |
WO2003007478A8 WO2003007478A8 (de) | 2003-03-13 |
WO2003007478A3 WO2003007478A3 (de) | 2003-05-22 |
Family
ID=7691294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2002/001899 WO2003007478A2 (de) | 2001-07-10 | 2002-05-23 | Verfahren und einrichtung zum erzeugen von mobilfunksignalen |
Country Status (5)
Country | Link |
---|---|
US (1) | US20040176045A1 (de) |
EP (1) | EP1405418A2 (de) |
CN (1) | CN1605156A (de) |
DE (1) | DE10133514A1 (de) |
WO (1) | WO2003007478A2 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103546410A (zh) * | 2012-07-09 | 2014-01-29 | 电子科技大学 | 一种连续相位qpsk调制方法及其调制装置 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ITBO20030117A1 (it) * | 2003-03-05 | 2004-09-06 | A E B Srl | Apparato radiomicrofonico a trasmissione digitale |
TWI373925B (en) | 2004-02-10 | 2012-10-01 | Tridev Res L L C | Tunable resonant circuit, tunable voltage controlled oscillator circuit, tunable low noise amplifier circuit and method of tuning a resonant circuit |
DE102004023220A1 (de) * | 2004-03-11 | 2005-10-06 | Siemens Ag | Verfahren und Vorrichtung zum Erzeugen einer Schwingung mit veränderlicher Frequenz |
US7590210B2 (en) * | 2004-09-13 | 2009-09-15 | Nortel Networks Limited | Method and apparatus for synchronizing internal state of frequency generators on a communications network |
US7643595B2 (en) * | 2004-09-13 | 2010-01-05 | Nortel Networks Limited | Method and apparatus for synchronizing clock timing between network elements |
US20080212658A1 (en) * | 2007-03-01 | 2008-09-04 | Ahmadreza Rofougaran | Method and system for communication of signals using a direct digital frequency synthesizer (ddfs) |
CN103516652B (zh) * | 2012-06-25 | 2016-06-15 | 电子科技大学 | 一种连续相位bpsk调制方法及其调制装置 |
EP2860881B1 (de) | 2012-06-30 | 2016-04-06 | Huawei Technologies Co., Ltd. | Trägerfrequenzeinstellverfahren und vorrichtung für mimo-mikrowellenvorrichtung |
CN104113507B (zh) * | 2013-04-18 | 2017-03-08 | 电子科技大学 | 连续相位16qam调制方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2247368A (en) * | 1990-08-25 | 1992-02-26 | Roke Manor Research | Phase modulation signal generator |
US5184093A (en) * | 1991-03-08 | 1993-02-02 | Mitsubishi Denki Kabushiki Kaisha | Frequency synthesizer |
EP0717491A2 (de) * | 1994-12-13 | 1996-06-19 | Hughes Aircraft Company | Synthetisierer hoher Präzision sowie niedrigen Phasenrauschens, mit Vektormodulator |
WO2001020774A1 (en) * | 1999-09-14 | 2001-03-22 | Conexant Systems, Inc. | Wireless transmitter having a modified translation loop architecture |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4926130A (en) * | 1988-01-19 | 1990-05-15 | Qualcomm, Inc. | Synchronous up-conversion direct digital synthesizer |
US5128623A (en) * | 1990-09-10 | 1992-07-07 | Qualcomm Incorporated | Direct digital synthesizer/direct analog synthesizer hybrid frequency synthesizer |
US5162762A (en) * | 1991-03-25 | 1992-11-10 | At&T Bell Laboratories | Phase-lock loop with adaptive scaling element |
JP3317837B2 (ja) * | 1996-02-29 | 2002-08-26 | 日本電気株式会社 | Pll回路 |
FR2755556A1 (fr) * | 1996-11-06 | 1998-05-07 | Motorola Semiconducteurs | Modulateur de frequence, emetteur et emetteur-recepteur incorporant ce modulateur de frequence |
US5834985A (en) * | 1996-12-20 | 1998-11-10 | Telefonaktiebolaget L M Ericsson (Publ) | Digital continuous phase modulation for a DDS-driven phase locked loop |
US6002923A (en) * | 1997-11-07 | 1999-12-14 | Telefonaktiebolaget Lm Ericsson | Signal generation in a communications transmitter |
US6664827B2 (en) * | 2001-03-02 | 2003-12-16 | Adc Telecommunications, Inc. | Direct digital synthesizer phase locked loop |
-
2001
- 2001-07-10 DE DE10133514A patent/DE10133514A1/de not_active Ceased
-
2002
- 2002-05-23 EP EP02745084A patent/EP1405418A2/de not_active Withdrawn
- 2002-05-23 CN CNA028139356A patent/CN1605156A/zh active Pending
- 2002-05-23 US US10/483,868 patent/US20040176045A1/en not_active Abandoned
- 2002-05-23 WO PCT/DE2002/001899 patent/WO2003007478A2/de not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2247368A (en) * | 1990-08-25 | 1992-02-26 | Roke Manor Research | Phase modulation signal generator |
US5184093A (en) * | 1991-03-08 | 1993-02-02 | Mitsubishi Denki Kabushiki Kaisha | Frequency synthesizer |
EP0717491A2 (de) * | 1994-12-13 | 1996-06-19 | Hughes Aircraft Company | Synthetisierer hoher Präzision sowie niedrigen Phasenrauschens, mit Vektormodulator |
WO2001020774A1 (en) * | 1999-09-14 | 2001-03-22 | Conexant Systems, Inc. | Wireless transmitter having a modified translation loop architecture |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103546410A (zh) * | 2012-07-09 | 2014-01-29 | 电子科技大学 | 一种连续相位qpsk调制方法及其调制装置 |
Also Published As
Publication number | Publication date |
---|---|
US20040176045A1 (en) | 2004-09-09 |
EP1405418A2 (de) | 2004-04-07 |
WO2003007478A3 (de) | 2003-05-22 |
CN1605156A (zh) | 2005-04-06 |
DE10133514A1 (de) | 2003-01-30 |
WO2003007478A8 (de) | 2003-03-13 |
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