WO2002099670A1 - Systeme de calcul parallele a architecture programmable - Google Patents

Systeme de calcul parallele a architecture programmable Download PDF

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Publication number
WO2002099670A1
WO2002099670A1 PCT/RU2002/000276 RU0200276W WO02099670A1 WO 2002099670 A1 WO2002099670 A1 WO 2002099670A1 RU 0200276 W RU0200276 W RU 0200276W WO 02099670 A1 WO02099670 A1 WO 02099670A1
Authority
WO
WIPO (PCT)
Prior art keywords
group
inputs
parallel
outputs
ram
Prior art date
Application number
PCT/RU2002/000276
Other languages
English (en)
Russian (ru)
Inventor
Gennadiy Ivanovich Bacherikov
Viktor Ivanovich Gevorkyan
Vadim Mikhailovich Krokhin
Vadim Jurievich Tatur
Original Assignee
Gennadiy Ivanovich Bacherikov
Viktor Ivanovich Gevorkyan
Vadim Mikhailovich Krokhin
Vadim Jurievich Tatur
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gennadiy Ivanovich Bacherikov, Viktor Ivanovich Gevorkyan, Vadim Mikhailovich Krokhin, Vadim Jurievich Tatur filed Critical Gennadiy Ivanovich Bacherikov
Publication of WO2002099670A1 publication Critical patent/WO2002099670A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus

Definitions

  • the invention is subject to computing and may be subject to change.
  • a computer containing a process is known, an input-output switch,
  • command download switch command memory, data access module
  • the accessory for this computer is that when executed
  • RAM Responsive Storage Device
  • a significant disadvantage of such a system is a strong interconnection.
  • upstream processor system bus, utility RAM, internal RAM, and
  • the download node, the first group of inputs and outputs is connected to the front 3 ⁇ mmunsh atsi ⁇ nn ⁇ y s ⁇ ed ⁇ y, ⁇ i e ⁇ m v ⁇ aya g ⁇ u ⁇ a in ⁇ d ⁇ v ⁇ - ⁇ you ⁇ d ⁇ v site
  • the operating inputs are connected to the third operating group
  • the first group of outputs is connected to the group
  • the information output is connected to the group input of the download
  • the output is connected to the system bus and is also connected to
  • the programmable hardware may have an additional introduction of one or
  • the input and output unit of each network adapter is connected to the system bus
  • the input and output of the research process is connected to the system bus, with
  • the first group is also connected to the entrance to the main entrance of each network.
  • buffer memory 8-first communicated medium; 9- ⁇ -parallel ⁇ rocess ⁇ ,
  • Fig. 1 blocks 1, 2, 3, 4, 5, 6, 7 use the parallel
  • the internal memory 6 is intended for storage of information on site
  • This block is for loading the process. ⁇ some cases of RAM and
  • Buffered RAM 7 serves for exchange
  • Medium 8 and it may be more like the usual RAM in the form of a collection of registers,
  • the download node 4 is intended for downloading and downloading commands and data in
  • the download node contains: 18 - a block of hardware shredders, 19 - a registry
  • the ff.5 is shown as one of
  • Command block contains: 25 - cam, 26 -
  • Units of bus drivers 18,24 ensure communication of units in the unit
  • Block of bus drivers 23 Ensures the connection of the blocks of the download node with the RAM 7
  • Block command 20 provides
  • the facility is located at 19, which contains official information ⁇
  • the machine 25 compares the current address as it is counted
  • Register 26 serves
  • the download node works as follows: Including ⁇ 1 through
  • system bus 2 and drive unit 18 sends commands to the unit
  • count of address 21 is the starting address of the information array.
  • the counter of address 21 increases its value in accordance with
  • Commutation 22 may be completed as described in [5,7].
  • Team block may be completed as described in [5,7].
  • the unit 25 compares the current address counter with the last
  • the command 27 issues the following to the offending process 1, which sent the factory,
  • the second boot node 4 may have been entered.
  • Network adapters 10, 11 are designed to connect a parallel
  • Network adapters 15, 16 are intended for connection
  • Computing node 17 on second 12 and third 13 communicated environments with
  • the device operates the following way. Any ⁇ ammma,
  • non-neurological type system bus and one or more network adapters.
  • this process controller is also 10 industrial process. Its main task is to ensure
  • a process that can be run can perform investigational processes. Therefore
  • Applications may and may not be computational nodes.
  • Programs may start other processes that are in progress.
  • a process may start a few other processes before it
  • Processes are carried out on processes corresponding to the type. Well, in
  • Each parallel process 9 is enabled using the download node 4, and
  • the data that is being processed is processed through the first communica
  • the arhitektory consumes one or more communicated media (12.13 per fsh.Z),
  • Process and data that is being processed, is produced through the second and / or
  • ROM 3 there is some data in ROM 3, and also records information about the unit’s settings in 12 service RAM 6. The last one contains the data for the download node 4, and
  • the master process 1 issues a command to the download node
  • download node 4 the input data from the RAM 3 and is written to the negative or to the buffer
  • process elements 5 can exchange data with other matrices
  • the system must be equipped with one or more communicated systems.
  • neighbors (12.13 in FIG. 3), optionally connected through a network of adapters.
  • the computing system is generally operational.
  • the device makes it possible to significantly increase the speed of processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Cette invention relève du domaine du matériel informatique et peut être utilisée dans des systèmes à rendement élevé qui servent à traiter de grandes quantités de données en temps réel. Ce système de calcul parallèle à architecture programmable comprend des milieux de communication et N processeurs parallèles. Chacun de ces processeurs comporte une matrice d'éléments de traitement, un processeur de commande, une mémoire RAM, un bus système, une mémoire d'exploitation, une mémoire tampon, un noeud de chargement ainsi qu'un adaptateur réseau. En outre, ce système comprend des noeuds de calcul, chacun de ces noeuds étant doté d'un processeur en série et d'adaptateurs réseaux. L'organisation des liens entre les unités faisant partie du système de calcul parallèle, le mode de réalisation du processeur parallèle ainsi que l'introduction d'éléments de communication permettent d'accroître la vitesse de traitement des données ainsi que l'efficacité d'exécution de programmes complexes.
PCT/RU2002/000276 2001-06-06 2002-06-05 Systeme de calcul parallele a architecture programmable WO2002099670A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU2001115081 2001-06-06
RU2001115081/09A RU2202123C2 (ru) 2001-06-06 2001-06-06 Параллельная вычислительная система с программируемой архитектурой

Publications (1)

Publication Number Publication Date
WO2002099670A1 true WO2002099670A1 (fr) 2002-12-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU2002/000276 WO2002099670A1 (fr) 2001-06-06 2002-06-05 Systeme de calcul parallele a architecture programmable

Country Status (2)

Country Link
RU (1) RU2202123C2 (fr)
WO (1) WO2002099670A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112004002797B4 (de) 2004-03-19 2015-12-31 Zakrytoe Aktsionernoe Obschestvo "Intel A/O" Ausfallsicherung und Lastausgleich
US7760626B2 (en) 2004-03-31 2010-07-20 Intel Corporation Load balancing and failover
US8032821B2 (en) * 2006-05-08 2011-10-04 Microsoft Corporation Multi-thread spreadsheet processing with dependency levels
JP5680466B2 (ja) * 2011-03-29 2015-03-04 三菱重工業株式会社 並列処理システム及び並列処理システムの動作方法
RU2486581C1 (ru) * 2012-07-11 2013-06-27 Открытое акционерное общество "Научно-исследовательский институт "Субмикрон" Параллельная вычислительная система с программируемой архитектурой
RU2591180C1 (ru) * 2015-05-29 2016-07-10 Юрий Анатольевич Ткаченко Защищенный компьютер, сохраняющий работоспособность при повреждении
RU2644535C2 (ru) * 2016-06-01 2018-02-12 Владимир Викторович Ермишин Архитектура параллельной вычислительной системы
RU2653293C1 (ru) * 2017-07-11 2018-05-07 Акционерное общество "Федеральный научно-производственный центр "Нижегородский научно-исследовательский институт радиотехники" Устройство первичной обработки радиолокационной информации

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008815A (en) * 1983-05-31 1991-04-16 Thinking Machines Corporation Parallel processor
US5421019A (en) * 1988-10-07 1995-05-30 Martin Marietta Corporation Parallel data processor
RU2084953C1 (ru) * 1990-11-13 1997-07-20 Интернэшнл Бизнес Машинз Корпорейшн Параллельная процессорная система
RU2110088C1 (ru) * 1994-07-06 1998-04-27 Закрытое акционерное общество "Парком" Параллельный процессор с перепрограммируемой структурой

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008815A (en) * 1983-05-31 1991-04-16 Thinking Machines Corporation Parallel processor
US5421019A (en) * 1988-10-07 1995-05-30 Martin Marietta Corporation Parallel data processor
RU2084953C1 (ru) * 1990-11-13 1997-07-20 Интернэшнл Бизнес Машинз Корпорейшн Параллельная процессорная система
RU2110088C1 (ru) * 1994-07-06 1998-04-27 Закрытое акционерное общество "Парком" Параллельный процессор с перепрограммируемой структурой

Also Published As

Publication number Publication date
RU2202123C2 (ru) 2003-04-10

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