WO2002099449A1 - Appareil et procede d'attaque de broches de raccordement de circuits dans un systeme de test de circuits - Google Patents

Appareil et procede d'attaque de broches de raccordement de circuits dans un systeme de test de circuits Download PDF

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Publication number
WO2002099449A1
WO2002099449A1 PCT/US2002/021875 US0221875W WO02099449A1 WO 2002099449 A1 WO2002099449 A1 WO 2002099449A1 US 0221875 W US0221875 W US 0221875W WO 02099449 A1 WO02099449 A1 WO 02099449A1
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WIPO (PCT)
Prior art keywords
circuit
testing apparatus
under test
current
output
Prior art date
Application number
PCT/US2002/021875
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English (en)
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WO2002099449A8 (fr
Inventor
Douglas W. Babcock
Original Assignee
Analog Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/757,746 external-priority patent/US6677775B2/en
Application filed by Analog Devices, Inc. filed Critical Analog Devices, Inc.
Priority to EP02761076A priority Critical patent/EP1358497A1/fr
Publication of WO2002099449A1 publication Critical patent/WO2002099449A1/fr
Publication of WO2002099449A8 publication Critical patent/WO2002099449A8/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Definitions

  • a typical ATE system for testing a finished IC includes a control system such as a personal computer programmed to run tests and process and store test result data automatically.
  • the system also includes various power sources used to power the IC under test and to generate any test signals required for the tests. These can typically include DC as well as AC sources.
  • the system also includes a "test head" in which the IC is mounted for the test.
  • the test head typically includes a device interface board (DIB) that provides the appropriate electronic interface between the IC under test and the rest of the test system.
  • DIB device interface board
  • the DIB typically makes connections to the IC via the connection pins on the IC package. Test stimulus signals generated by the test system are applied to the appropriate IC inputs and resulting response signals from the IC outputs are coupled to the test system via the DIB connections to the IC pins.
  • an ATE system typically also includes additional circuitry between the controlling processor and the DIB.
  • This circuitry commonly referred to as "pin electronics,” includes driving circuitry for generating the stimulus signals to be applied to the IC input pins and receiving and detection circuitry for processing response signals from the IC output pins.
  • Conventional pin driver circuits exhibit various drawbacks when they are called upon to generate the highly accurate stimulus signals required by present high-speed circuits.
  • conventional amplification stages which require current to switch on and off to generate square pulses cannot generate short pulses with symmetry, i.e., substantially equal rise and fall times.
  • the present invention is directed to a circuit testing apparatus and method that provides circuit testing drive signals with extremely accurate timing and voltage parameters and which exhibit a high level of pulse symmetry.
  • the circuit testing apparatus of the invention includes a controller that controls signals being transferred between the circuit under test and the circuit testing apparatus.
  • a driver circuit in the circuit testing apparatus generates signals to be applied to the circuit under test.
  • the driver circuit includes a high speed slave chain and a DC control loop chain to the circuit under test.
  • the driver circuit is coupled to a pin on the circuit under test.
  • the pin electronics can include a separate driver circuit for each pin on the circuit under test, with a driver circuit being coupled to each pin, such that separately generated and controllable drive signals can be applied to each pin.
  • a circuit testing apparatus includes a controller for controlling signals being transferred between a circuit under test and the circuit testing apparatus.
  • the circuit testing apparatus further includes a driver circuit for generating signals to be applied to the circuit under test.
  • the driver includes a high speed slave chain and DC control loop chain coupled to the circuit under test.
  • the high speed slave chain receives a differential voltage logic pulse train and converts the logic pulse train into a high speed current steering for producing the drive signal to be applied to the circuit under test.
  • the DC control loop chain provides feedback paths for DC regulation of inputs of the high speed slave chain.
  • a circuit testing apparatus includes a controller for controlling signals being transferred between a circuit under test and the circuit testing apparatus.
  • the circuit testing apparatus further includes a driver means for generating signals to be applied to the circuit under test.
  • the driver includes a high speed slave chain and DC control loop chain coupled to the circuit under test.
  • the high speed slave chain receives a differential voltage logic pulse train and converts the logic pulse train into a high speed current steering for producing the drive signal to be applied to the circuit under test.
  • the DC control loop chain provides feedback paths for DC regulation of inputs of the high speed slave chain.
  • a method of testing a circuit includes providing a controller for controlling signals being transferred to and from the circuit under test.
  • the method also includes providing a driver circuit coupled to the circuit under test.
  • the method further includes receiving a differential logic pulse train, and converting the logic pulse train into a high speed current steering for producing the drive signal to be applied to the circuit under test.
  • FIG. 1 contains a schematic block diagram of one embodiment of a circuit testing system in accordance with the present invention.
  • FIG. 2 contains a schematic block diagram of one embodiment of pin electronics in the circuit testing system in accordance with the present invention.
  • FIG. 3 is a schematic diagram illustrating the logical function of pin electronics in accordance with the invention.
  • FIG. 4 is a schematic diagram of one embodiment of a portion of a pin driver circuit in accordance with the invention.
  • FIG. 5 is a schematic diagram of an alternative embodiment of a portion of a pin driver circuit in accordance with the invention.
  • FIG. 6 is a schematic diagram of another alternative embodiment of a portion of a pin driver circuit in accordance with the invention.
  • FIG. 7 is a schematic diagram of the top level of an implementation of the pin driver circuitry.
  • FIG. 8 is a more detailed schematic diagram of the input clamp stage of the high speed slave and DC control loop chains.
  • FIG. 9 is a more detailed schematic diagram of the current controlled gain stage of the high speed slave and DC control loop chains.
  • FIG. 10 is a more detailed schematic diagram of the output stage of the high speed slave and DC control loop chains.
  • FIG. 11 is a schematic diagram of the DC control loop chain.
  • FIG. 1 contains a schematic block diagram of one embodiment of a circuit testing system 10 in accordance with the present invention.
  • the system 10 includes a main test system or console 12 interfaced to a test head 14.
  • the console 12 includes a controller or processor 18 and memory 20 which can be implemented in, for example, a personal computer.
  • the processor 18 runs under the control of a program stored in the memory 20 for automatically testing a circuit under test 30 mounted in the test head 14.
  • the processor 18 and memory 20 control virtually all aspects of the tests being performed including the timing and levels of DC and time varying stimulus signals applied to the circuit under test.
  • the processor 18 and memory 20 also process and store data for response signals transferred by the circuit under test 30 to the console 12 in response to the stimulus signals.
  • the console 12 also includes multiple power supplies 16 used for providing power to the circuit under test 30 during testing and also provides the stimulus signals applied to the circuit under test 30 during testing.
  • the console 12 also includes electronic circuitry 22 designed and implemented according to the particular circuit under test 30 and the particular tests being performed.
  • the circuitry 22 can include the pin electronics 24 used to interface with the pins on the circuit under test 30 in accordance with the invention. As shown in FIG. 1, in an alternative embodiment, the pin electronics 24 are implemented in the test head 14. It will be understood that the pin electronics 24 are not implemented in both the console 12 and the test head 14 but are illustrated in both places in FIG. 1 merely to illustrate that the location of the pin electronics is not limited to only one of the possible locations.
  • the circuit under test 30 is mounted in the test head 14 during testing.
  • the circuit under test 30 can be any type of circuit or integrated circuit such as a microprocessor circuit.
  • the pin electronics 24 interface with the circuit under test 30 via a device interface board 26 to apply stimulus signals to, and receive response signals from, the circuit under test 30.
  • the device interface board 26 includes interconnections between the pin electronics 24 and the pins on the package of the circuit under test 30 as well as the electronics used to facilitate the interconnections, e.g., filtering circuitry.
  • the device interface board 26 also includes the mechanical interface to the package pins on the circuit 30. When the circuit 30 is held in place in a socket on the device interface board 26, connections are made to the pins on the circuit 30 to complete the interface between the system 10 and the circuit 30.
  • the pin electronics 24 are shown in FIG. 1 as part of electronic circuitry 28.
  • the circuitry 28 refers to electronic circuitry required to perform the particular required tests on the particular circuit being tested. This can be, for example, amplification circuitry, signal conditioning circuitry, filtering circuitry, etc.
  • FIG. 2 is a schematic block diagram illustrating the general configuration of one embodiment of the pin electronics 24 in accordance with the invention.
  • the pin electronics include a receiver/driver circuit 32a, 32b, . . . , 32n for each pin in the circuit under test 30 to which a connection is to be made by the test system.
  • Each receiver/driver circuit 32 includes a pin driver circuit 34 and a receiver circuit 36 coupled together to a line that is coupled to the circuit under test via the device interface board 26.
  • Each pin driver 34 is coupled to the line via an electronic switch 38 that allows the driver 34 to be electrically disconnected from the line when the line is being used to receive signals from the circuit under test.
  • Each receiver circuit 36 is also coupled to the line via an electronic switch 40 that allows the receiver 36 to be electrically disconnected from the line when the line is being used to apply a drive signal to the circuit under test.
  • Each receiver circuit 36 can include a window comparator circuit formed from a pair of comparators 42 and 44 connected together as shown. In each window comparator circuit, an upper threshold voltage is applied to the noninverting input of the comparator 42 and a lower threshold voltage is applied to the inverting input of the comparator 44.
  • the outputs of the comparators are coupled to the test system for analysis. The timing of state changes in the comparator outputs can be used to analyze a signal received from the associated output of the circuit under test.
  • the pin driver circuits 34 receive a signal on an input line 33 from the controlling processor 18 that defines the signal that is to be generated and applied to the circuit under test by the driver 34.
  • the signal received on the line 33 can be a square wave which transitions between a logic high level and a logic low level at a particular frequency, duty cycle, etc., determined to be appropriate for the particular test.
  • the pin driver 34 must generate a stimulus signal in accordance with the parameters of the controlling signal for application to the circuit under test.
  • FIG. 3 is a schematic block diagram that illustrates the logical function of the pin driver circuit 34.
  • the controlling data signal which defines the parameters of the desired output drive signal is applied to input logic circuitry 46.
  • the signal in general can transition between logic low and high levels and can be characterized by a number of signal parameters, e.g., pulse rise and fall times, pulse symmetry, pulse duration, square wave duty cycle, etc.
  • the control signal is applied to logic 46 that is used to control switching of a switching means 48.
  • the switching means 48 effectively generates a stimulus signal that is compatible with the circuit under test and which complies as closely as possible with the signal parameters defined by the data control signal applied to the logic 46. That is, as the control signal transitions between its logic high and low states, the switching means 48 applies signal levels compatible with the circuit under test. For example, when the control signal is in a logic high state, the switching means 48 is configured to apply a drive signal at a high voltage level referred to herein as V H .
  • the switching means 48 is configured to apply a drive signal at a low voltage level referred to herein as V L . These voltages are applied tlirough an output resistance R OUT to generate the drive signal voltage level V OU T to be applied as a stimulus to the circuit under test.
  • the driver circuit 34 and particularly the switching means 48, are actually implemented with amplification and signal conditioning circuitry designed to meet the drive signal requirements.
  • the accuracy requirements for drive signals have become extremely challenging to meet.
  • Driver circuits used in conventional testing systems are becoming increasingly incapable of meeting these increasingly stringent drive signal requirements.
  • one conventional type of driver uses a class AB output stage that operates in class A conditions at low output currents and class B conditions when an output device shuts off due to higher output currents.
  • class AB drivers offer a high degree of functionality including high voltage swing capability and relatively low power, but they also suffer from a number of limitations when ultimate speed and accuracy are required. In particular these limitations are due to the fact that current flowing through the output transistor string is allowed to be shut off in at least one of the transistors.
  • Class A drivers operate at higher power levels than AB drivers, and their output swings are generally lower. Class A drivers operate faster and more accurately than AB drivers. Class A drivers provide for an output voltage swing that occurs as a current is either allowed to pass or not allowed to pass through its output resistor. That is, the driver transitions between two states, one in which current flows through the output resistor and one in which the current is shut off. Under high-speed dynamic conditions, output transistors are being switched on and off very quickly to switch the current through the output resistance between on and off. A problem arises in this situation due to the fact that the transistors turn on very differently than they turn off.
  • FIG. 4 contains a schematic diagram of one embodiment of a portion of a pin driver circuit 134 in accordance with the invention that addresses these problems of conventional pin driver circuits.
  • the pin driver circuit 134 includes a differential pair of transistors Ql and Q2 connected as shown. Each emitter leg includes a current source value L and I 2 , each of which is set at a fixed current. A gain degeneration resistor Rl is connected between the emitters of the transistors Ql and Q2 such that the configuration performs as a linear amplifier instead of the switched circuits used in the prior art systems.
  • the current through the leg of the circuit that contains the transistor Ql, and, therefore, the current through the output resistor R OUT determines the output voltage level V OUT generated by the driver circuit output stage.
  • the resistance values Rl and R OUT are selected such that the voltage drop across the output resistance R OUT sets the output voltage V O U T of the drive signal to the desired levels.
  • the amount of current flowing through the transistor Ql is controlled in turn by the amount of current flowing through the resistor Rl . When the voltage on the emitter of Q2 is higher than that of Ql, then current flows from the Q2 side of Rl to the Ql side of Rl.
  • This differential-input signal which for this description takes the form of a square pulse or some combination of square pulses, transitions between a low level input voltage V I and a high level input voltage V ⁇ J .
  • V I low level input voltage
  • V ⁇ J high level input voltage
  • the low and high output levels are also determined by the selection of the output resistance R OUT -
  • the high level output drive voltage V H is applied to R OUT by a unity gain amplifier 61.
  • the value of R OUT is selected such that when the higher current flows through R O U T , the output voltage V OU T is at the desired low output voltage value, and when the lower current flows through RO U T, the output voltage V O U T is at the desired high output voltage value.
  • the currents Ii and I 2 are chosen such that regardless of the direction of current flow through Rl, both transistors Ql and Q2 are conducting some current, i.e., neither transistor is completely shut off, and the difference in current between the two states flowing through R OUT determines the voltage swing of the output V OUT - For example, if R OUT is 50 ohms, and the difference in current through Ql in the low state and the high state is 20 ma, then the difference between the high and low levels of V OUT will be 1.0 volt.
  • the operation of the circuit of FIG. 4 will now be illustrated by example circuit parameters. It will be understood that these parameters are used only to illustrate the invention and are not limiting. Other circuit parameters can be used within the scope of the invention.
  • the difference in current through R OUT between states should be set to 20 ma.
  • the source currents l ⁇ and I 2 can each be set to 12 ma and Rl can be chosen to be 50 ohms.
  • the voltage V H at the top of R OUT is set to 1.1 volts.
  • the differential input signal can be controlled such that the base or Ql is -0.5 and the base of Q2 is 0 volt.
  • the current through R OUT in the high output state is 2 ma, resulting in a 0.1 volt drop across RO UT such that V OUT is 1.0 volt.
  • the current through R OUT in the low output state is 22 ma, resulting in a 1.1 volt drop across R OUT such that VO UT is 0.0 volt.
  • the emitters of Ql and Q2 are at approximately -0.7 and -1.2 volt, respectively.
  • the 22 a current through R O U T results in a 1.1 volt drop across R OUT , or a V OUT of 0.0 volt.
  • the emitters of Ql and Q2 are at approximately —1.2 and -0.7 volt, respectively.
  • the 2 ma current through R OUT results in a 0.1 volt drop across R OU T , °r a V OUT of 1.0 volt.
  • the linear circuit of the invention uses fixed current sources and controls the output swing by varying the base differential voltage of Ql and Q2.
  • the source currents and resistance Rl are chosen such that the operation of the device never results in either transistor being shut off. Keeping both devices on all the time eliminates the stored charge problem found in prior devices.
  • controlling the output level by varying the base voltages allows the circuit of the invention to operate at acceptable output voltage levels with relatively small input voltage levels. These factors provide the capability of generating very fast and accurate stimulus signals with very high fidelity and signal quality.
  • FIG. 5 is a schematic diagram of an alternative embodiment of a portion of a pin driver circuit 234 in accordance with the invention.
  • the resistance Rl of the previous embodiment is implemented as two resistors connected as shown, each having a value of Rl/2.
  • the dual current sources l ⁇ and I 2 of the previous embodiment are implemented as a single current source having a current value of L + 1 2 . This circuit functions in a similar fashion to the circuit shown in FIG. 4.
  • FIG. 6 is a schematic diagram of another alternative embodiment of a portion of a pin driver circuit 334 in accordance with the invention.
  • the circuit includes cascode transistors Q3 and Q4 as well as a connection point for the unused current that flows through Q2 and Q4. This causes the total current sourced by the V H voltage source 361 to be constant regardless of output voltage V O U T amplitude. From a DC point of view, this keeps the output resistance of the V H buffer amplifier 361 constant which in turn reduces interaction between the high and low output voltage levels caused by changes in output swing level. From a dynamic point of view, the buffer 361 sees very small transient current spikes rather than large current transitions.
  • the cascode transistors Q3 and Q4 as well as a connection point for the unused current that flows through Q2 and Q4. This causes the total current sourced by the V H voltage source 361 to be constant regardless of output voltage V O U T amplitude. From a DC point of view, this keeps the output resistance of the V H buffer amplifier 361 constant which in turn
  • the V H voltage source used in one embodiment can be a class AB style driver. It is noted that the foregoing describes the circuit of the invention as including a differential input in which the difference between the input voltages is used to operate the circuit. However, it will be understood that a single-ended input can also be used in accordance with the invention. That is, one of the inputs can be held at a constant voltage while the other is varied to control the input to the circuit.
  • FIG. 7 illustrates the top level of an implementation of the pin driver circuitry.
  • a high current amplifier that has its output resistor Rout equal to 50 Ohm, which is similar to characteristic impedance of the transmission line path to the Device Under Test (DUT) pin that the output node connects to.
  • the high current amplifier receives as input the voltage V HREF .
  • Differential output currents lo and IoB leave at both the respective terminals of resistor Rout such that when the current lo is greater than current IoB, the voltage at the output is said to be in a logical high state or, VH.
  • the output lo is less than the current IoB, the voltage at the output is said to be in a logical low state or, VL.
  • the high current buffer arrangement is provided for illustrative purposes to show one of many arrangements where the inventive circuit may be used.
  • the high current buffer's input voltage level, V HREF as well as the sum and difference of currents, lo and IoB, both common mode and differential output voltages may be programmed.
  • the buffer arrangement is usually unity gain that provides high current and low impedance output.
  • the output node is usually connected to a 50 Ohm transmission line and is terminated at 50 Ohms at the DUT pin.
  • the buffer supplies in excess of 50 mA when the driver is programmed for an output pulse of 1 V in amplitude.
  • the pin driver also includes a high speed slave (HSS) chain 370 and DC control loop (DCCL) chain 372.
  • the high speed slave (HSS) chain 370 provides the functionality to convert an input differential voltage logic pulse train into the high current steering of outputs lo and IoB.
  • the HSS chain 370 requires two logic inputs D and DB to take the form of an ECL level complimentary signal, such that D is at a logical high and DB will be at a logical low.
  • These input pulse signals amplitudes are on the order of 0.5 V peak to peak, with the high logic levels at approximately -0.8 V and logic low levels at approximately — 1.3 V.
  • the pin driver when fabricated using ADI's XF2 semiconductor process can handle input pulse repetition rates upward of 2 GHz.
  • the HSS chain 370 includes an input clamp stage 374, current controlled gain stage 376, and output stage 378.
  • the input pulse signals D and DB are presented to the input clamp stage of the HSS chain 370.
  • the input clamp stage 378 converts these signals into differential ramps that are clamped at their fixed amplitude levels.
  • the input clamp stage 378 provides differential outputs Q and QB that are highly accurate and linear slew rate transitions of a fixed amplitude.
  • the input clamp stage 378 directs the outputs Q and QB as inputs D and DB to the current control gain stage 376.
  • the input current signal I GAIN adjusts these fixed amplitude levels.
  • the current controlled gain stage 376 provides a time invariant output at its outputs Q and QB, where the amplitude is adjusted from essentially 0 to maximum voltage by means of DC current injected into the I GAIN port.
  • CCGS 376 Q and QB are directed as inputs D and DB to the output stage 378.
  • the outputs of the CCGS 378 Q and QB provide controlled amplitude differential voltage pulses to the output stage.
  • the output stage drives a linear differential fixed Gm stage that outputs high currents lo and IoB.
  • the HSS chain 370 has two control mechanisms. They are the I GAIN input to the gain stage that sets the difference between lo and IoB output currents and the Icompl and Icomp2 inputs to the output stage that control the sum of the lo and IoB currents.
  • both the VH and VL output voltage levels may be controlled.
  • the DC control loop (DCCL) chain 372 is essentially identical in its circuit configuration to the high speed slave chain (HSS) 370.
  • the DC control loop (DCCL) chain 372 is used solely to provide a closed loop DC regulation for the high speed slave chain 370 via its I GAm , Icompl and Icomp2.
  • the DCCL chain 372 includes a DC input clamp stage
  • the high speed slave chain 370 accepts high speed differential inputs D and DB from a logic source where the DC control loop chain 372 inputs remains fixed, logic wise.
  • the internal circuitry of the high speed slave chain 370 is ratio-matched to the internal components of the DC control loop chain 372. For illustrative purposes, the currents and device sizes in the high speed slave chain 370 are 10 times the size of their counterparts in the DC control loop chain 372.
  • the DC control loop chain 372 provides low speed feedback paths for amplifiers Al, A2 and their associated circuitry via respective I GAmx , Icomplx and Icomp2x inputs, wherein the Slave chain receives exactly proportional scaled control currents via its I GAIN , Icompl and Icomp2 inputs.
  • the output differential currents lox and loBx are controlled by sourcing a current into the I in port. This value realized 0 to maximum output current differential when I in current was adjusted from 0 to 1mA. This current may be generated by a DAC with an output voltage of 0 Volts. With the input D of the DC input clamp stage fixed with a logical value of high and the other differential input DB set at a logical value of low, the DCCL chain 372 output lox will always be greater than or equal to output loBx of the DC control loop chain 372. If I in is set to 0mA, DCCL chain 372 outputs lox and loBx will become equal. Otherwise, if I in is set higher than 0mA, lox will be proportionately larger than loBx.
  • the closed loop signal path for this action is through amplifier Al, which at its output drives current sources Ql, and Q2 that in turn generate the high speed slave chain 370 (HSS) and DC control loop chain 372 (DCCL) currents I GAIN and I GAINX , respectively. These currents are inversely proportional to lo and IoB differential current levels, thus at maximum output current differential, I GAJN and I GAINX are at 0.
  • the DC differential feedback path is closed through DC output stage 384 current output lox and the combination of R x and R 2 gain setting resistors as well as II offset current source.
  • output currents lox and loBx and output currents lo and IoB are equal to Io/lO and IoB/10 respectively.
  • the currents and device sizes in the HSS chain 370 are ten times the size of their counterparts in the DCCL chain 372.
  • the output current summation namely Io+IoB, is controlled by holding the loBx output current of the DCCL chain 372 equal to that of the 12 current source.
  • Amplifier A2 through identical current sources formed by transistor Q3 and Q4, generates feedback currents Icomp/10 that regulate the DC output stage's compliance current sources.
  • lox will remain at its fixed value set by 12 and the amplifier A2 by the feedback current Icomp/10.
  • the output current lox will increase in proportion to I m and the gain set resistors ? t and R 2 .
  • the currents of the output stage of the high speed slave chain 370 will be proportional to the currents from the output stage of the DC control loop chain
  • the current outputs of high speed slave chain 370 will reverse states in response to input logic stimulus. For example, the lower of either lox or loBx currents will remain constant regardless of output level programmed of the output stage of the DCCL chain 372.
  • FIG. 8 illustrates a more detailed schematic of the input clamp stage of the high speed slave (HSS) chain 370 and DC control loop (DCCL) chain 372.
  • the input clamp stage of the HSS chain 370 and DCCL chain 372 converts differential logic signals at inputs D and DB into fixed amplitude complimentary output voltages Q and QB.
  • the transistors Ql and Q2 receive the input signals D and DB at their respective bases.
  • the arrangement of the transistors Ql and Q2 form a differential switched pair that steers current from source II away from the current supplied by sources 12 and 13 to folded cascode transistors Q4 and Q3, respectively.
  • the current sources 12 and 13 are each set to deliver more than the current available from current source II to insure that transistors Q3 and Q4 always remain actively biased.
  • transistors Q3 and Q4 always remain actively biased.
  • the collector current of transistor Q3 is either equal to the current from the current source 12, such that the input D is a logical high value and the input DB is a logical low value. This current is equal to the difference of the currents from current sources II and 12 the input D is a logical low and DB is a logical high.
  • the collector current of transistor Q4 is complimentary to that of transistor Q3.
  • Current sources 14 and 15 provide pull down current such that the collector node voltages of transistors Q3 or Q4 will rise if no current is being diverted by Ql or Q2.
  • Current sources II, 12, 13, 14, and 15 are selected so that the resultant voltage rise and fall times of the collectors of transistors Q2 and Q3 will be equal.
  • Transistors Q7 and Q9 form the negative clamp and transistors Q8 and Q10 form the positive clamp.
  • the voltage Vref sets the clamp voltage differential. In the case, 0.4 V keeps the signal swing small enough for limited voltage headroom constraints, while at the same time keeping either transistors Q9 or Q10 from leaking emitter current when cutoff. This condition affects both slew rate and the voltage transition linearity.
  • Transistors Q5 and Q6 buffer the high impedance collector nodes from the following current controlled gain stage differential pair.
  • Transistors Q9 and Q10 are specifically sized so that they present a very low clamp point impedance to the bases of transistors Q5 and Q6 which keeps them from ringing. Matched, scaled, fixed voltage circuitry is contained in the DC input clamp stage.
  • the input clamp stage 380 receives fixed logic input D and DB.
  • the input clamp stage 380 of the DCCL chain 372 also outputs fixed amplitude complimentary output voltages.
  • the complimentary output voltages Q and QB of the input clamp stage 380 demonstrate linear and matched rise and fall times with very low aberrations and fixed amplitude.
  • the quality of the output signals Q and QB of the input clamp stage 380 is directly representative of the quality of the pin driver output waveform as from this stage forward, all amplification and gain control is linear.
  • FIG. 9 illustrates a detailed schematic of the current controlled gain stage of the high speed slave (HSS) chain 370 and DC control loop (DCCL) chain 372.
  • the complimentary outputs Q and QB of the input clamp stage drive the inputs D and DB of the current controlled gain stage (CCGS) 410 with a fixed amplitude voltage signal.
  • the CCGS 410 employs a controlled cascode translinear multiplier cell configuration to provide wide bandwidth with high DC precision and low distortion means for controlling the amplitude of the fixed amplitude voltage signal.
  • pin drivers have been limited to minimum output pulse amplitudes in the range of 100 to 200mV due to their ability to provide for low distortion large and small signal pulses with the same circuit configuration.
  • Variable clamp circuits have been used, but these are typically constrained by their inability to provide for linear performance as signal amplitudes are reduced to point that bipolar emitter/base junctions are not reverse biased enough to fully turn them off. Variable clamps also result in signal propagation delay changes that are proportional to signal amplitude. Also, FIG. 9 further illustrates that components Ql , Q2, Q3, Q4, Rg, Rl, R2, II and
  • Emitter followers Q7 and Q8 provide for a low impedance base drive for the output stage via output ports Q and QB.
  • FIG. 10 illustrates a detailed schematic of the output stage of the HSS chain 370 and the DCCL chain 372.
  • the output stage 420 is a standard cascoded differential linear amplifier whose output currents, lo and IoB, drives either the driver output resistor R OUT in the case of the HSS chain 370, or provides feedback currents for the DCCL chain 372.
  • HSS chain 370 current sources II and 12 are sized to 36mA each. This current level enables the driver to provide a 1.5V output swing with the DUT terminated into 50 Ohms.
  • This amplitude level requires 60 mA of lo to IoB differential current swing, the remaining current is used to make sure neither transistor Ql or Q2 goes into cut-off at high signal swings, and that the feedback loop regulation of the output stage 410 compliance current flowing through transistors Q5 and Q6 via ports Icompl and Icomp2 will always be active.
  • the cascoded transistors Q3 and Q4 provide for high stage bandwidth and provide for higher voltage swings at the output Q and QB.
  • Lower cascoded transistors Q5 and Q6 isolate the high capacitance of feedback input Icompl and Icomp2 from the high speed emitter voltage swings of transistors Ql and Q2.
  • the output stage 384 of the DCCL chain 372 is identical in its structure but, as stated above, is scaled to 1/10 the currents and device sizes of the output stage of HSS chain 370.
  • cascode transistors Q3 and Q4 provide for high stage bandwidth and provide for higher voltage swings at the output.
  • Lower cascode devices Q5 and Q6 isolate the high capacitance of feedback input Icompl and Icomp2 from the speed emitter voltage swings of input transistors Ql and Q2.
  • FIG. 11 illustrates a detailed schematic of the DC loop control (DCCL) chain.
  • the DCCL chain 372 has only one input, Iin that is used to adjust the difference between output currents lox and loBx.
  • DCCL chain 372 includes two feedback paths that provide for regulation of the difference between the output currents lox and loBx and the sum of the output currents lox an loBx. These loops are called the gain control loop 390 (GCL) and compliance current loop 388 (CCL), respectively.
  • GCL 390 is directly controlled by sourcing current into the Iin port.
  • the current source for Iin is typically a digital to analog converter (DAC) with an output voltage compliance range that includes 0 V.
  • the high gain amplifier Al has its inverting input connected to ground.
  • the high gain amplifier Al will force the voltage at input Iin to equal the voltage on its inverting input. If it is assumed that the CCL 388 is not connected at this time, fixed equal current sources 19 and 110 pull all of their current through the cascoded transistors Ql 1 and Q12. Thus, the sum of currents from current sources 19 and 110 will be equal to the sum of output currents lo and IoB.
  • the Vref of the DCCL chain 372 is a fixed voltage source that drives the emitter follower transistors Ql and Q2, which in turn impose this voltage between the bases of transistors Q3 and Q4 in the CCGS chain 382. Neglecting for the moment gain control transistors Q5 and Q6, this voltage is amplified and appears as a voltage differential at the collectors of transistors Q7 and Q8. Transistors Q9 and Q10 form emitter followers that buffer this signal and drive the bases of the output stage transistor Q21 and Q22 of the DCCL chain 372. Note, because of the polarity of Vref, the base of the transistor Q21 is higher than that of Q22. This causes more current to flow into lox than loBx. The collector current from either transistors Ql 1 or Q12 must always be greater than the difference voltage between Q21 and Q22 bases divided by resistor R12 to keep the input clamp stage in linear operation.
  • the DCCL chain 372 has a fixed, unipolar voltage reference at its input while the HSS chain 370 has a differential logic signal that reveres polarity. This results in the fact that while the DC output can only provide for its output current lox to be greater than or equal to output current loBx.
  • the HSS chain 370 will have lox greater or equal to IoB when its logic inputs have D high and DB low and loBx greater than or equal to lo when D is low and DB is high. This infers that in this logic state the HSS chain 370 outputs currents lo and IoB .will directly match their DCCL chain 372 counterparts lox and loBx, respectively.
  • the HSS chain 370 output current lo will match the DCCL chain 372 counterpart loBx and the HSS chain 370 output IoB will match to the DC counterpart lox.
  • h switched current Class A drivers only the VL low level output voltage moves in response to amplitude control. This is because the only time current is flowing through Rout in a switched architecture is when the driver output is in the higher current, VL output state.
  • the driver output is in a VH high state, no current is flowing through Rout, therefore the VH level is set by the High Current Buffer only and remains the same irregardless of the output current that the switched current driver is supplying.
  • current is always flowing tlirough lo and IoB outputs, therefore both must be regulated.
  • the current compliance loop (CCL) 388 functions to regulate the IoB output current of the DCCL chain 372 output stage to a fixed value, independent of Iin current level.
  • Current loBx has been set to be less than or equal to currents lox in the DCCL chain 372 and this will reflect a fixed voltage for Driver VH output voltage level. Since current loBx is held constant while lo increases in response to an increased input current Iin, then the collector current of transistors Qll and Q12 must increase as well.
  • current source 12 is set for the minimum value of current loBx that is required and current sources 19 and 110 can provide more than the maximum current required by lox and loBx
  • the high gain amplifier A2 through current sources formed by transistors Q17 and Q18, will adjust feedback currents Icompl and Icomp2 so that current loBx will exactly equal to current from current source 12.
  • current Iin is increased or decreased, the compliance currents from collectors of transistors Qll and Q12 will increase or decrease, respectively.
  • current source II and 12 are equal, their absolute values set to keep enough current in the output stage at low signal amplitudes so that neither Q21 or Q22 will ever be allowed to go into cutoff .
  • scaled Icompl and Icomp2 feedback currents are also sent to control the HSS chain 370 output stage 376 from current sources formed by transistors Q19 and Q20.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un appareil de test de circuits comprenant une commande servant à commander les signaux transférés entre un circuit à tester et l'appareil de test de circuit. Par ailleurs, l'appareil de test de circuits comprend un circuit d'attaque qui émet des signaux à appliquer au circuit à tester. Ce circuit d'attaque comprend une chaîne secondaire à haute vitesse et une chaîne boucle de commande c.c. couplée au circuit à tester. La chaîne secondaire à haute vitesse reçoit un train d'impulsions logiques à tension différentielle qu'elle convertit en une commande de courant à haute vitesse pour émettre le signal d'attaque à appliquer au circuit à tester. La chaîne boucle de commande c.c. forme les boucles de retour servant à régler l'intensité du courant c.c. des entrées de la chaîne secondaire à haute vitesse.
PCT/US2002/021875 2001-01-10 2002-01-10 Appareil et procede d'attaque de broches de raccordement de circuits dans un systeme de test de circuits WO2002099449A1 (fr)

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EP02761076A EP1358497A1 (fr) 2001-01-10 2002-01-10 Appareil et procede d'attaque de broches de raccordement de circuits dans un systeme de test de circuits

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US09/757,746 US6677775B2 (en) 2001-01-10 2001-01-10 Circuit testing device using a driver to perform electronics testing
US09/757,746 2001-01-10
US26572901P 2001-02-01 2001-02-01
US60/265,729 2001-02-01
US26716201P 2001-02-07 2001-02-07
US60/267,162 2001-02-07

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101222229B (zh) * 2007-01-12 2010-09-15 义隆电子股份有限公司 内建自我测试的讯号转换装置
US20190091042A1 (en) * 2010-02-01 2019-03-28 Biomet Manufacturing, Llc Transdermal intraosseous device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377202A (en) * 1993-05-03 1994-12-27 Raytheon Company Method and apparatus for limiting pin driver offset voltages
WO2000039928A1 (fr) * 1998-12-23 2000-07-06 Raytheon Company Architecture de circuit integre de circuit d'attaque pin a haute vitesse destinee a des applications d'equipements d'essai automatiques
US6166569A (en) * 1999-04-23 2000-12-26 Analog Devices, Inc. Test interface circuits with waveform synthesizers having reduced spurious signals

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377202A (en) * 1993-05-03 1994-12-27 Raytheon Company Method and apparatus for limiting pin driver offset voltages
WO2000039928A1 (fr) * 1998-12-23 2000-07-06 Raytheon Company Architecture de circuit integre de circuit d'attaque pin a haute vitesse destinee a des applications d'equipements d'essai automatiques
US6166569A (en) * 1999-04-23 2000-12-26 Analog Devices, Inc. Test interface circuits with waveform synthesizers having reduced spurious signals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101222229B (zh) * 2007-01-12 2010-09-15 义隆电子股份有限公司 内建自我测试的讯号转换装置
US20190091042A1 (en) * 2010-02-01 2019-03-28 Biomet Manufacturing, Llc Transdermal intraosseous device

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