WO2002091592A1 - Codes a controle de parite faible densite, et produits turbocodes faible densite - Google Patents

Codes a controle de parite faible densite, et produits turbocodes faible densite Download PDF

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Publication number
WO2002091592A1
WO2002091592A1 PCT/US2002/014614 US0214614W WO02091592A1 WO 2002091592 A1 WO2002091592 A1 WO 2002091592A1 US 0214614 W US0214614 W US 0214614W WO 02091592 A1 WO02091592 A1 WO 02091592A1
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Prior art keywords
bit
matrix
parity
codeword
output
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PCT/US2002/014614
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English (en)
Inventor
Roman R. Khannanov
Garik Markarian
Sergey I. Ortyukov
Keith Pickavance
Sergey L. Portney
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Comtech Telecommunications Corp.
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Priority to EP02731730A priority Critical patent/EP1407555A1/fr
Publication of WO2002091592A1 publication Critical patent/WO2002091592A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/296—Particular turbo code structure
    • H03M13/2963—Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2978—Particular arrangement of the component decoders
    • H03M13/2987—Particular arrangement of the component decoders using more component decoders than component codes, e.g. pipelined turbo iterations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

Definitions

  • the present invention relates to the field of linear block codes, in general, and in particular, a method of and apparatus for encoding and decoding low density parity check codes and low density turbo product codes.
  • LDPC codes Low density parity check (LDPC) codes were first thought about in 1962. Since that time, there has been a substantial amount of mathematical knowledge about such LDPC codes. LDPC codes have natural uses in all areas of communication systems and are especially suited to scenarios where long block lengths of codes are to be used for extra performance requirements. However, LDPC codes have laid dormant due to many reasons, such as the recent invention of the Viterbi algorithm which is a practically realizable algorithm for decoding convolutional codes. In addition, LDPC codes were not easily implementable. LDPC codes are one dimensional codes that have a very long block length such that encoders and decoders have been unable to utilize them in an efficient manner due to the requirement of storing such long block lengths in their respective memories. Further, the complexity, randomness of bits and long block lengths of LDPC codes were not easily handled by the encoders, decoders and processing units of many electronic devices. However,
  • LDPC codes give better results than conventional Viterbi and Turbo Product Codes because of their longer block length and more random nature of their coding scheme. Much more theoretical work was completed in which ideas were independently adopted such that much faster processors are now available to be used in a practical situation.
  • encoding and decoding schemes are only utilized towards product codes, extended hamming codes and turbo product codes.
  • encoding and decoding schemes are not present which are utilized towards LDPCs and low density turbo product codes (LDTPCs). What is needed is an encoding and decoding scheme which is utilized towards LDPCs and LDTPCs.
  • a method of encoding a one dimensional input codeword into an output codeword includes an output codeword bit comprising the following steps. Receiving the input codeword, wherein the input codeword includes an input codeword bit. Creating a generator matrix, wherein the generator matrix includes a parity matrix that has a plurality of parity bits. Combining the input codeword bit with a corresponding parity bit from the plurality of parity bits. This generates an output redundant bit that is associated with the output codeword bit. Transmitting the input codeword bit as well as the output redundant bit.
  • Figure 1 illustrates an overall block diagram of the encoder and decoder system in accordance with the present invention.
  • Figure 2 illustrates a generator matrix having dimensions (n, k) in accordance with the present invention.
  • Figure 3 a illustrates a flow chart related to the encoding method in accordance with the present invention.
  • Figure 3b illustrates a parity matrix having dimension (n, n-k) in accordance with the present invention.
  • Figure 4 illustrates a timing diagram of the decoding method with respect to LDPC codes in accordance with the present invention.
  • Figure 5 illustrates a general LDTPC block matrix in accordance with the present invention.
  • Figure 1 shows a general overall block diagram of the overall encoding and decoding system 100 of the present invention.
  • the unencoded LDPC codes enter the encoder module 10 wherein the data is encoded.
  • the LDPC codes enter as one dimensional codeword vectors u having information bits u n .
  • the encoder 10 is preferably coupled to a memory 12 which preferably stores the parity matrix which is used to encode the LDPC data, as will be discussed in more detail below. This is such that the system 100 does not need to wait for the whole codeword u to enter the system before encoding the matrix.
  • the memory 12 stores the actual u information codeword as well as the parity bits.
  • the received encoded block of data v is demodulated by the demodulator 16 which then supplies the decoder 18 with hard decision and soft decision values.
  • the decoder 18 decodes the encoded data by using an iterative decoding scheme and a parity check matrix in the LDPC code. It is preferred that the decoder 18 is a Soft In/Soft Out (SISO) decoder, which receives demodulated soft decision input data and produces soft decision output data.
  • SISO Soft In/Soft Out
  • the decoder 18 is coupled to a memory 20, whereby the memory 20 stores the decoded data, as will be discussed in more detail below. Once the data is decoded, the decoder 18 outputs the decoded data.
  • the LDPC code enters the encoder 10 as an input information vector codeword u.
  • the information vector codeword u has a block length of 30,000 bits such that:
  • the LDPC code is a one-dimensional code and has a very large block length.
  • the LDPC code has a significantly higher number of "zeros" than "ones”, which makes the encoding and decoding process for the LDPC very simple, efficient and fast.
  • the encoder 10 of the present invention creates and utilizes a generator matrix 200 (Figure 2) in conjunction with the one dimensional LDPC codeword to encode the input codeword u into an encoded output codeword v.
  • the system 100 is configured such that the LDPC codeword will be encoded with a generator matrix 200 having a dimension (n,k), shown in Figure 2.
  • the generator matrix 200 in Figure 2 is a (32768, 30000) matrix, whereby the generator matrix 200 includes a unit matrix 202 and a parity or redundant matrix 204.
  • the unit matrix 202 preferably has k bit rows and k bit columns. Alternatively, the unit matrix 202 has an unequal number of rows and columns.
  • the unit matrix 202 has a size of 30000 x 30000 bits, due to the codeword u having a block length of 30,000 bits.
  • the unit matrix 202 is preferably the same size k as the block length of the LDPC information vector codeword u.
  • the parity matrix 204 has a size 30000 x 2768, in which the 2768 bits represent the redundant bits (n-k).
  • the parity matrix 204 is preferably used to add the redundancy or parity vector to the codeword u to form the output vector v, as will be discussed below.
  • FIG. 3 a illustrates a general flow diagram of the preferred encoding procedure in accordance with the present invention.
  • a generator matrix size 200 of (n,k) is set.
  • parameters J and K are set, as will be described in more detail below.
  • Step 304 includes creating the generator matrix 200, wherein the generator matrix 200 includes a unit matrix 202 and parity matrix 204.
  • the encoder 10 receives the information codeword u which has u k _, bits.
  • the output redundant vector of the parity check bits (or output redundant bits) of the parity matrix 204 are set and updated, as will be discussed below.
  • the encoder 10 preferably transmits the output codeword v k _, and stores in vector of the parity check bits (step 312).
  • the encoder determines whether the codeword bit n that is being processed is the last bit in the codeword vector u. If it is not, the encoder repeats steps 306 through 314. However, if the value of n is equal to the block length N of the codeword vector u, the encoder transmits the output redundant vector of the parity check bits, as shown in step 316.
  • the encoder 10 of the present invention utilizes parameters J and K to place "ones" in the columns and rows, respectively, of the generator matrix 200. Since the LDPCs have a substantially random nature, the number of J and K "ones" placed in the generator matrix 200 are less compared to the total number of bits n and k of the generator matrix 200. It is preferred that between three and four J ones are inserted into each of the columns of the generator matrix 200. Similarly, it is preferred that between three and four K one are inserted into each of the rows of the generator matrix 200. Nonetheless, any number of J and K "ones" may be inserted into the generator matrix 200.
  • the LDPC codes have an unequal J number throughout the parity check matrix 204.
  • the LDPC codes also have an unequal K number throughout the parity check matrix.
  • certain LDPC codes are constructed using unequal values of J for each row and unequal values of K for each column. This causes each parity check bit to be dependent on a different number of potentially different information bits and reduces the regularity in the code as well as causes the code to verge towards randomness. More detail concerning the construction of the generator matrix 200 is discussed below.
  • the encoder 10 encodes the LDPC codes by transforming the generator matrix 200 into systematic form.
  • the encoder 10 places some of the J and K "ones” diagonally across the unit matrix 202, as shown in Figure 2, thereby placing "zeros" in the rest of the unit matrix 202.
  • This configuration in the unit matrix 202 preferably allows the information vector codeword u to be combined only with the bits in the parity matrix 204.
  • other configurations of the "ones" in the unit matrix 202 are used such that the codeword u is directly combined with the bits in the parity matrix 204.
  • the remaining number of J and K "ones" which are not placed in the unit matrix 202 are then randomly placed within the parity matrix 204, as shown in Figure 2.
  • the "ones” are arranged in a known, configured set, wherein the placement of the "ones” are transmitted along with the encoded data bits.
  • These remaining “ones” are used by the encoder 10 in conjunction with each bit in the u codeword to encode the LDPC codeword into an encoded output vector v.
  • each bit in the information vector « is combined with each parity bit a in a corresponding row or column of the parity matrix 204.
  • the parity matrix 204 shown in Figure 3a includes 29,999 bit rows and 2767 bit columns, whereby the parity matrix 204 contains parity bit a 00 , shown in the upper left hand corner of the matrix 204, to parity bit ⁇ 29999,2767 , shown in the lower right hand corner of the matrix 204.
  • the encoder 10 utilizes the input information bit u 0 and preferably directly sends the u 0 over the transmission channel 14, because the configuration of the diagonal "ones" in the unit matrix 202 allow the exact vector u to be seen in the 30,000 bit position of the output vector v.
  • the encoder 10 receives u 0 , it sets and updates the output redundant vector v (n . k) of the parity check bits a, which in this example is 2768 bits long. Then the encoded bit is sent out as v 0 , which is equal to « 0 .
  • the output redundant vector having parity check bits, v 30000 , v 30001 , ... v 32768 is preferably stored while the encoder waits for the next bit u to be input to the encoder 10. The updates are done via the equations shown below:
  • the encoder 10 Once the encoder 10 has encoded and sent out the first output bit v 0 , it preferably sends out the parity bits a k in the parity matrix 204 that are associated with the first input bit « 0 .
  • the encoder 10 forms an output redundant bit v 30000 by combining the information bit u 0 with the first parity bit in the first row of the parity matrix 204, which is « 00 .
  • the combination of the output redundant bit with the information bit is preferably done by logical multiplication.
  • the encoder 10 forms the output redundant bit v 30001 by combining the input information bit u with the second parity bit in the first row of the parity matrix 204, 0jl .
  • the encoder 10 then forms the output redundant bit v 30002 by combining the information bit u with the third parity bit in the first row of the parity matrix 204, ⁇ 02 . This process repeats until the encoder 10 encodes v 32767 by combining the information bit u with the last parity bit in the first row of the parity matrix 204, ⁇ 0;2767 -
  • the encoder 10 stores the output redundant bits in the memory 12, whereby the encoder 10 transmits the output redundant bit vector after the complete codeword u has been received and encoded by the encoder 10.
  • the encoder 10 transmits the output redundant bits v (n _ k) associated with the output codeword v 0 as they are generated.
  • the encoder 10 forms the final output bit v using bit 1 of the information vector codeword u .
  • the encoder 10 receives u it updates the output redundant vector of the parity check bits.
  • the output redundant vector of parity check bits is preferably stored while the encoder 10 waits for the next bit of the codeword u to be input to the encoder 10.
  • the updates for the output codeword v x are done via the equations shown below:
  • V 32767 — 32767 ® U ⁇ & a l,2767 where the combination of the output redundant bit with the information bit is preferably done by logical addition.
  • the final output bit is sent out as v x which is equivalent to «,.
  • the encoder 10 utilizes the information bit u and sends the vector bit u x over the transmission channel 14, because the configuration of the diagonal "ones" in the unit matrix 202 allow the exact vector u to be seen in the first 30000 positions of the output vector v.
  • the encoder 10 Once the encoder 10 has encoded and sent out v l5 it sends out the parity bits a associated with the output bit v x using the equations above.
  • the encoder 10 forms the output redundant bit v (n _ k) by combining the input information bit u x with the first parity bit in the second row of the parity matrix 204, which is a xfi .
  • the encoder 10 preferably combines the information bit u x with the parity bit x>0 by utilizing a logical multiplication technique.
  • the encoder 10 then updates the output redundant bit v 30000 by performing a logical addition technique between the output redundant bit and the redundant codeword bit v 30000 from the last bit of the codeword u.
  • the encoder 10 forms the output redundant bit v 30>001 for output bit v x by combining the information bit u x with the second parity bit in the second row of the parity matrix 204, which is a x .
  • the encoder 10 updates the output redundant bit v 30001 by performing a logical addition technique between the output redundant bit and the output redundant codeword bit v 30001 .
  • the encoder 10 forms the output redundant bit v 30>002 for bit v by combining the information bit u x with the third parity bit in the second row of the parity matrix 204, which is a 2 , and performing a logical addition technique of the combination with the output redundant bit v 30002 .
  • This process repeats for bit v x until the encoder 10 encodes all the output redundant bits v 32767 by combining the information bit u x with the last parity bit in the second row of the parity matrix 204, which is ⁇ l ⁇ 2767 and updating the product with the output redundant bit v 32 ⁇ 767 .
  • the 2768 output redundant bits are preferably output following the information bits v.
  • the output codeword v is:
  • each bit is formed in the final output codeword v by using the corresponding parity bit from each column for the corresponding row in the parity matrix, 202.
  • the parity bits used to form the output redundant bits in the codeword v are taken along a column in the parity matrix 202, rather than a row.
  • the parity bits used to form the output redundant bits in the codeword v are taken from a combination of the rows and columns of the parity matrix 202, i.e. a diagonal configuration.
  • the encoder 10 is given parameters J and K units.
  • the value of K is greater than the value of J.
  • the generator matrix 200 includes the unit matrix 202 having a size k x k, whereby the unit matrix 202 has a diagonal of "ones" and the remaining bits of "zeros."
  • the generator matrix 200 includes an initial parity matrix 204 which represents J lines from k sub matrixes, whereby the parity matrix 204 is a result of the cyclic rearrangement of columns of the diagonal in the unit matrix 202.
  • each column of parity matrix 204 includes J units and each row of the parity matrix 204 includes K unit matrices.
  • An approximation is preferably used because, the initial parity matrix 204 has linearly dependent rows.
  • the number of information symbols appears more than k x (N - J) such that the block length N of the code has the maximum information bits within the block.
  • K > k it is possible to choose cyclic rearrangements of columns of diagonal sub matrixes in such a manner that parity matrix 204 will set J orthogonal parity checks for each symbol of the code.
  • such a matrix having an orthogonal property for parity checks allows use of the initial parity matrix 204 to generate subsequent parity matrixes. This is preferably done by rearranging the columns in each strip of the initial parity matrix, whereby the number of attempts to rearrange the columns in each strip is predetermined.
  • the orthogonality of the parity matrix 204 is checked. If the orthogonality of the parity matrix 204 is met, the arrangement of columns is kept. However, if the orthogonality of the parity matrix 204 is not met, the arrangement of the columns is cancelled. After all the strips in the parity matrix have been rearranged and the desired parity matrix 204 is not met, a new parity matrix 204 is formed having orthogonal properties to the initial parity matrix 204. Such a new parity matrix would give better results for LDPC codes that are to be transmitted over a channel having white additive Gaussian noise.
  • H s is formed.
  • the decoder 18 is preferably a SISO decoder which uses hard decision values and soft decision values provided by the demodulator 16.
  • the demodulator 16 For the encoded codeword v received from the transmission channel 14, the demodulator
  • the decoding algorithm includes a predetermined number of iterations. For each iteration, each row of the parity check matrix 204 is preferably consecutively processed, whereby the each bit in the syndrome, s, is calculated and the corresponding reliability value of the vector, E, is updated.
  • the system 100 may utilize more than one decoder (not shown) in parallel to decode the encoded codewords. Parallel decoders are preferably used to decode blocks having more than one dimension, such as LDTPCs, as will be discussed below. This is evident mainly from the way the decoding algorithm in the decoder 18 works by first evaluating the syndromes s in order. Then, the soft metric vectors are calculated using these syndromes.
  • the reliability symbols E are positive. If a change occurs to the reliability values whereby the reliability value E becomes negative, the hard decision value x associated with the reliability value E is changed.
  • the detailed procedure of decoding and processing a row of the LDPC will now be discussed. It should be noted that although the discussion regarding the decoding of the codewords relates to LDPC codes, the decoding procedure and method may be used with other types of error correction codes. Before processing of ayth row, there are current values of hard decision vectors, reliability vectors and syndrome vectors in the decoder 18. After processing the /th row, the modified values of the hard decision vectors, reliability vectors and syndrome vectors are obtained and updated.
  • n(j, k) the position of the Mi one in they ' th row.
  • n(j, 1), n(j, 2), ..., n(j, K) are the positions of the "ones" in each row y.
  • the set of reliability vectors for row are E n(j l) E n(j 2) .,.., E n(j ⁇ ) .
  • the reliability vectors for E n(j ⁇ ) is designated as E l3 E 2 ..., E ⁇ .
  • Processing of each row includes the step of setting E kl to be the minimal reliability value and E ⁇ to be the next reliable value.
  • the components of the hard decision vectors x are then updated as necessary, whereby the syndrome s is recalculated for the next iteration.
  • the decoding process is complete if the syndrome vector s is equal to 0. If the decoder stops before the syndrome vector s is equal to 0, then a block error is detected in the codeword .
  • matrix H is a low density matrix.
  • the information word is multiplied by the matrix G. This results in a systematic code word including the unchanged information bit portion and parity or redundant bit portion.
  • FIG. 4 illustrates a general timing diagram of the decoding process in accordance with the present invention.
  • Step 1 shows that the first block of data is received in the decoder 18.
  • step 2 the syndrome is calculated for the first codeword.
  • step 3 a result for the first syndrome of the first block is reached.
  • step 4 the second block of data is received in the decoder 18.
  • step 5 the syndrome is calculated for the second codeword.
  • step 6 the decoder 18 is concurrently performing an iterative decoding scheme on block 1 for a "m" number of iterations.
  • step 7 the decoded results of the first block are calculated. It is preferred that the decoder 18 stores the decoded results in memory 20 while it continues to decode the subsequent blocks of data.
  • step 8 shows that a result for the second syndrome is reached.
  • the decoder receives the subsequent blocks of encoded data from the encoder (not shown). Meanwhile, in step 9, the decoder 18 is concurrently performing an iterative decoding scheme on block 2 for "m" number of iterations. Following, in step 10 the decoding results are provided for the second block. This process is repeated and continues for N number of blocks of data that are being received.
  • the LDPC codes are configured in a product code fashion, such that the LDPC codes will be encoded and decoded as a turbo product code.
  • the present invention uses an LDPC code inside a product code to make a low density turbo product code or LDTPC.
  • LDTPCs are encoded a different way than traditional turbo codes, they are decoded as a turbo code.
  • the information vector codewords u, b, c, d, etc. are received by the encoder 10.
  • the encoder 10 then generates a block matrix 500 in which all the incoming LDPC codewords are organized per row. As shown in Figure 5, all the k bits of the codeword u are placed along the first row in the unit matrix portion 501 of the block matrix 500. Figure 5 also illustrates that all the parity (n-k) bits of the codeword u are placed in the parity matrix 502 of the block matrix 500. In addition, as shown in Figure 5, all the A: bits of the codeword b are placed along the second row in the unit matrix portion 501 of the block matrix 500 and so on. Figure 5 also illustrates that all the parity (n-k) bits of the codeword b are placed in the parity matrix 502 of the block matrix 500.
  • a parity check bit row 503 is added to the last row of the block 500, as shown in Figure 5.
  • the parity check bit row 503 is preferably added by the encoder 10, whereby the encoder generates the parity check bit row 503 by encoding each codeword along the corresponding row or column. Once the parity check bit row 503 is added, the encoded bits are sent across the transmission channel
  • the order of the bits is arbitrary as long as the bits, once received or decoded, can be lined up again in the same form.
  • the decoder 18 can decode the LDTPC code by using the same iterative decoding scheme discussed above in regard to the LDPC codes and parity check codes. However, in addition to decoding all the rows of the LDTPC block, the decoder will complete one additional decoding of the columns using the parity check bit row 503.
  • the encoder 10 in the system 100 includes one or more parallel processors to significantly reduce the number of operations to encode one input bit in the information vector u. The reduction is dependent on the number of parallel processors used in the encoder 10.
  • more than one encoder may be used (not shown) to encode more than one input bit at a time and carry out simultaneous processing of the parity rows or alternately, columns, in the parity matrix 202. It should be noted that parallel processors and decoders are preferably used to decode blocks having more than one dimension.
  • decoding of the codewords is performed with prior knowledge of all the constituent codes. This is performed by taking a set of known but random LDPC codes in the construction of the LDTPCs such that the block structure remains in tact and the parity codes work properly.
  • the uniqueness of the constituent codes enables the system 100 to have full control over the security of the transmitted data. This is achieved before compromise by selecting a unique set. After the data has been compromised, this unique set is adjusted to a new unique set which has been defined in a predetermined way such that the receiving end is able to understand the set.
  • use of differing constituent codes throughout the block allows better error protection.
  • a certain error correction scheme is performed for a certain portion of the block, whereas a different error correction scheme is performed for another part of the block.
  • the transmitting end and receiving end of the system 100 are given sufficient information such that both ends are able to process the exact codes used in the block as well as know exactly where in the block the different error correction schemes are to be used.
  • Block synchronization is applied by taking a known unique set of constituent codes and calculating the reliability values of the decoded word in a known channel. Synchronization occurs when the reliability values indicate a high probability that convergence has occurred for the block. Decoding will be performed accurately when the blocks of data are synchronized. However, multiple decoding of the block may be needed if there is an initial lock up of the decoder. Nonetheless, re- synchronization of the block is relatively simple if slippages occur only for a few bits after the initial lock up.
  • Another alternate embodiment of the present invention allows the system 100 to counteract any errors in a particular column or row of the product code by constructing the product code to have shifts within.
  • the alternative embodiment of the present invention uses shifts of different LDPC codes for the rows to minimize chances of receiving similar errors in the same rows and/or columns.
  • the present uses shifts of the same LDPC code in the rows and/or columns.
  • the shifts may include moving successive rows and/or columns to the right or left by any number of bit positions.
  • the use of shifts in the present invention reduces the risk of overloading the parity check matrix.
  • the use of shifts of the LDPCs enables the system 100 to detect errors as well as correct errors. Therefore, the system 100 is able to avoid the use of cyclic redundancy checking to detect errors in a soft decision decoding system, whereby the data rate is able to be kept to the highest possible rate.

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Abstract

L'invention concerne un procédé et un dispositif permettant de coder un mot de code unidimensionnel de manière à produire un mot de code de sortie, ce mot de code de sortie comprenant un bit de mot de code de sortie. Les étapes de ce procédé consistent à recevoir le mot de code d'entrée, lequel comprend un bit de mot de code d'entrée, à créer une matrice (200) de générateur qui comprend une matrice (204) de parité comportant une pluralité de bits de parité, à combiner le bit du mot de code d'entrée avec un bit de parité correspondant sélectionné dans la pluralité de bits de parité afin de générer un bit de sortie redondant associé au bit du mot de code de sortie, à transmettre le bit du mot de code d'entrée, et à transmettre le bit de sortie redondant.
PCT/US2002/014614 2001-05-09 2002-05-09 Codes a controle de parite faible densite, et produits turbocodes faible densite WO2002091592A1 (fr)

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EP2472726A1 (fr) * 2009-08-25 2012-07-04 Fujitsu Limited Emetteur, dispositif de codage, récepteur et dispositif de décodage
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