WO2002082539A2 - A radio frequency (rf) device and its method of manufacture - Google Patents

A radio frequency (rf) device and its method of manufacture Download PDF

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Publication number
WO2002082539A2
WO2002082539A2 PCT/EP2002/003764 EP0203764W WO02082539A2 WO 2002082539 A2 WO2002082539 A2 WO 2002082539A2 EP 0203764 W EP0203764 W EP 0203764W WO 02082539 A2 WO02082539 A2 WO 02082539A2
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conducting
layers
layer
ground plane
dielectric
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PCT/EP2002/003764
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French (fr)
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WO2002082539A3 (en
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Peter Wennekers
Thomas Eugene Zirkle
Rainer Thoma
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Motorola Inc
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Publication of WO2002082539A2 publication Critical patent/WO2002082539A2/en
Publication of WO2002082539A3 publication Critical patent/WO2002082539A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
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    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/0105—Tin [Sn]
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    • H01L2924/01058—Cerium [Ce]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a radio frequency device incorporating a conductive RF pad and its method of manufacture.
  • RF pads may be used in conjunction with active devices which find application in microwave and radio equipment. Some may be configured as waveguide structures.
  • US 5, 401, 912 describes a microwave surface mount package having a U-shaped via around a lead via, thereby improving isolation.
  • a radio frequency (RF) device comprising a substrate, a conducting ground plane formed thereon, a layered stack formed on the conducting ground plane wherein the stack is composed of a plurality of conducting layers and a plurality of dielectric layers arranged alternately, and a conducting RF pad wherein, in a peripheral region of the device, the conducting ground plane and the conducting layers are interconnected by conducting vias thereby to form an enclosed, central region, and wherein the conducting RF pad is located within the central region and formed on at least one of the dielectric layers.
  • the RF pad comprises a plurality of conducting layers interconnected by conducting vias and separated from one another by dielectric layers. This type of configuration forms a capacitive ballast spaced from the ground plane of the device, so as to provide a capacitance at a lower frequency than that at which the device normally operates.
  • This preferred arrangement has been shown to improve the frequency response of the device at frequencies lower than those in its normal operating range.
  • the effect of the capacitive ballast is to shape the electric fields into predefined patterns so as to create a capacitance.
  • More than one capacitive ballast may be provided.
  • The, or each ballast are dimensioned and arranged so that lateral electric fields are attenuated more rapidly than has previously been the case. This is partly due to the proximity of the ballasts to the ground plane.
  • the detrimental capacitive effects are a function of the conductivity, the frequency and the relative areas of the capacitive ballasts.
  • known sizes of conducting layers overlay one another.
  • the effect is for one area, to effectively shield another and this has been formed to have beneficial effects at lower frequencies.
  • the device may further include a conducting base layer and at least one conducting path means interconnecting the base layer with the ground plane.
  • the device incorporates a slot in the stack for enabling connection to the RF pad.
  • a further embodiment includes conducting pads positioned on the surface of the uppermost conducting layer forming the stack.
  • a method of fabricating a radio frequency (RF) device including the steps of; forming a conducting ground plane on a dielectric substrate, forming on top of the ground plane a layered stack composed of alternate layers of conducting and dielectric layers, interconnecting, in a peripheral region of the device, the ground plane and conducting layers by means of conducting vias thereby to form an enclosed, central region, and forming a conducting RF pad within the central region and on at least one of the dielectric layers.
  • RF radio frequency
  • Figure 1 is a plan view of an embodiment of a radio frequency device in accordance with the invention.
  • Figure 2 is a section along the line of 2-2 in Figure 1;
  • Figure 3 is a partial view of a cross-section through an alternative embodiment of a radio frequency device in accordance with the invention.
  • Figure 1 is plan view of a RF device 10, comprising a radio frequency pad or RF-pad 11 surrounded by a conducting structure 13.
  • the RF-Pad 11 is depicted as being mounted on a surface of a semiconductor substrate 12.
  • the structure 13 surrounds the RF-pad 11 and comprises a closed path formed from a metallic conductor, such as aluminium or copper.
  • the conducting structure 13 is hereinafter referred to as a cup 13. It will be appreciated that the cup 13 may be circularly symmetric and have a circular or even oval cross-section. What is important is that the path is a closed path. Cup 13 encloses the RF-pad 11 substantially at its centre.
  • the RF-pad 11 can be circular or indeed of any shape, but a square or a regular polygon is preferred.
  • a narrow slit or openingl ⁇ is formed, which allows a connection 17 to be made from the pad 11 to an active device, such as a transistor (not shown) formed within the substrate 12.
  • RF-pad 11 The construction of RF-pad 11 is similar to that of the conductive walls of the cup 13 and is described in detail below. Different layers of the device 10 are shown in Figure 2.
  • a silicon wafer 20 defines a substrate .
  • a layer 24 is generated on the substrate 20 by ion-implantation of an acceptor such as boron. This acceptor ion doping of the substrate 20 is performed in predetermined locations across the surface of the silicon wafer 20 or across the entire wafer surface.
  • An alternative method of forming layer 24 is by epitaxial growth of acceptor doped silicon on substrate 20.
  • Layer 24 is highly conductive and has a carrier concentration exceeding 10 /cm .
  • the thickness of layer 24 is at least 0.5 microns.
  • a third silicon layer 26 is then grown using epitaxial growth of acceptor doped silicon on top of layer 24.
  • the doping in the third layer is low and consequently so is the conductivity.
  • the thickness of the third layer 26 is at least 0.5 microns. It should be noted that epitaxial layer 26 is covered by a thin natural Silicon Dioxide layer field oxide after completion of the epitaxial growth of layer 26. For reasons of simplicity the field oxide layer is not depicted.
  • a protective layer of dielectric material such as silicon dioxide 28 which is generated by a chemical vapour deposition (CND) method or by sputtering.
  • the thickness of layer 28 ranges typically from 0.5 to 2.0 microns.
  • each dielectric layer is planarised by a chemo-mechanical etching and polishing method CMP so as to yield a surface with minimum roughness.
  • a first metallic layer 30 is formed on a first dielectric layer 28.
  • the preferred method is by sputtering an aluminium alloy or CND/electroplating of copper. Prior to the deposition of metal to the surface of the dielectric it is necessary to coat the dielectric with a very thin intermediate layer in order to improve the adhesion of metal to dielectric. If aluminium is used as a metal, a thin coating layer of sputtered Titanium Nitride (TiN) is coated on the dielectric. The thickness of the thin coating layer is only several tens of nanometres and for the sake of clarity the coating layer is not shown here.
  • the metal layer 30 is patterned by photolithography.
  • a structured photoresist (not shown) protects those areas of the metal 30, which will not be etched in a subsequent etching process.
  • the etching process may be either the removal of the unprotected metal in a chemical ion plasma or wet chemical bath. A combination of both steps may be used.
  • Metal layer 30 is typically between 0.1 and 1.0 microns thick.
  • the metal layer 30 is coated with a thin TiN adhesion layer and a second dielectric layer 33 is then applied by CND method.
  • a CMP process step then follows to achieve planarity of the second dielectric layer 33.
  • a second metal layer 34 is then added at discrete locations to the second dielectric layer 33.
  • Conductive interconnects are formed between first and second metal layers 30 and 34 by way of small openings, referred to as vias 40 which are formed in the second dielectric layer 33, which are subsequently filled with metal.
  • the position of the vias 40 is defined by photolithography.
  • Nias 40 are etched by an ion plasma beam (not shown) in exposed areas of second dielectric layer 33, which were not protected with photoresist.
  • the vertical walls of the vias 40 are coated by sputtered Ti ⁇ , to improve adhesion to the vias filling metal.
  • the filling metal is typically tungsten, which is introduced into vias 40 by a CND method. This coating is not shown in the Figures.
  • the adhesion layer sequence (not shown) comprises thin sputtered layers of Titanium (Ti) and Titanium ⁇ itride(Ti ⁇ ). These layers are only several tens of nanometres thick.
  • a second metal layer is formed over the adhesion layer by sputtering or CND of Aluminium and electroplating Copper. The second metal layer is formed in a similar manner to the first layer.
  • Figure 2 shows an example of four metal layers 30, 34, 36, 38 separated by three dielectric layers 33, 35, 37.
  • the uppermost metal layer 38 is protected against corrosion by a top dielectric layer39. Openings are etched into this layer to allow electrical access to the RF pad 11 and ground-pads 15.
  • the cup 13 of Fig 1 with conductive walls is thus formed by appropriate structuring of each of the metal layers and interconnecting these layers with densely packed vias. Hexagonal packing of vias is preferred because this pattern provides the densest packing scheme.
  • the bottom of the cup is made from first metal layer 30.
  • RF-pad 11 comprises a stack of metal layers separated by insulating dielectric layers.
  • a top plate is the RF-pad area, which provides access to "off chip” electronic circuitry (not shown). The size of this area has a lower limit, typically 50 micron x 50 micron because of packaging rules in the chip assembly factory.
  • the vertical stack of metal layers beneath the RF-pad area 11 makes connections to the lower areas on the second metal layer 34.
  • This area can be sized for the desired capacitance of the overlap zone 200.
  • the RF-pad 11 and metal stack force the electrical field into a generally vertical direction (that is transverse to the plane defined by the substrate) as the distance between layer 34 and bottom of the cup (i.e. first metal layer) is much smaller than the lateral separation of the RF-pad stack and the surrounding cup walls.
  • one or more conductive paths between this silicon layer and the bottom of the cup and metal layer 30 maybe added.
  • FIG. 3 shows a P+ sinker implantation 41 is merged with a Source/Drain implantation which is a processing layer in the manufacturing of PMOS devices.
  • An ohmic metallic contact 43 made from Titanium Suicide or Cobalt Suicide connects the P+ doped regions by way of a metal via 44 to the first metal layer 30.
  • an RF-signal is transported to an active device (not shown), formed in the silicon substrate 20, by the conductor 17. It is recommended, that the conduct or 17 is a part of a microstrip line, which utilizes the first metal layer 30 as ground plane as shown in
  • the electromagnetic field in a microstrip line is mainly straight and vertical between the wire and the ground plane.
  • the RF device 10 is provided with metal pads 45, positioned on the surface of the uppermost metal layers (15 of Fig. 2).
  • the device 10 may then be mounted onto a printed circuit board (PCB) by means of the metal pads 45 which contact a metal trace (which may be grounded) on the surface of the PCB, thus providing the device 10 with a conducting lid.
  • PCB printed circuit board
  • a similar metal pad 46 provided on the RF pad 11 can also be arranged to contact an appropriate metal trace on the PCB.

Abstract

A radio frequency (RF) device (10) comprises a substrate (20), a conducting ground plane (30) formed thereon, a layered stack (33-39) formed on the conducting ground plane (30) wherein the stack (33-39) is composed of a plurality of conducting layers (34, 36, 38) and a plurality of dielectric layers (33, 35, 37, 39) arranged alternately, and a conduting RF pad (11) wherein, in a periphl region of the device (10), the conducting ground plane (30) and conducting layers (34, 36, 38) are interconnected by conducting vias (40) thereby to form an enclosed, central region, and wherein the conducting RF pad (11) is located with the central region and formed on at least one of the dielectric layers (37). An advantage of the device is that it does not suffer from deleterious effects such as stray or parasitic capacitance.

Description

A RADIO FREQUENCY (RF) DEVICE AND ITS METHOD OF MANUFACTURE
Field of the Invention
The present invention relates to a radio frequency device incorporating a conductive RF pad and its method of manufacture.
Background of the Invention RF pads may be used in conjunction with active devices which find application in microwave and radio equipment. Some may be configured as waveguide structures.
At RF frequencies, unwanted stray and parasitic capacitance can arise which degrades performance.
Several attempts have been made to remove or reduce these effects. US 5, 401, 912 describes a microwave surface mount package having a U-shaped via around a lead via, thereby improving isolation.
However, there is still a need for providing an RF device which is capable of operating across a broad frequency range and in particular a device which does not suffer unwanted capacitance effects.
Summary of the Invention In a first aspect of the present invention there is provided a radio frequency (RF) device comprising a substrate, a conducting ground plane formed thereon, a layered stack formed on the conducting ground plane wherein the stack is composed of a plurality of conducting layers and a plurality of dielectric layers arranged alternately, and a conducting RF pad wherein, in a peripheral region of the device, the conducting ground plane and the conducting layers are interconnected by conducting vias thereby to form an enclosed, central region, and wherein the conducting RF pad is located within the central region and formed on at least one of the dielectric layers. In one embodiment, the RF pad comprises a plurality of conducting layers interconnected by conducting vias and separated from one another by dielectric layers. This type of configuration forms a capacitive ballast spaced from the ground plane of the device, so as to provide a capacitance at a lower frequency than that at which the device normally operates.
This preferred arrangement has been shown to improve the frequency response of the device at frequencies lower than those in its normal operating range. Typically the effect of the capacitive ballast is to shape the electric fields into predefined patterns so as to create a capacitance.
More than one capacitive ballast may be provided. The, or each ballast, are dimensioned and arranged so that lateral electric fields are attenuated more rapidly than has previously been the case. This is partly due to the proximity of the ballasts to the ground plane. The detrimental capacitive effects are a function of the conductivity, the frequency and the relative areas of the capacitive ballasts.
Preferably, known sizes of conducting layers overlay one another. The effect is for one area, to effectively shield another and this has been formed to have beneficial effects at lower frequencies.
The device may further include a conducting base layer and at least one conducting path means interconnecting the base layer with the ground plane.
Preferably, the device incorporates a slot in the stack for enabling connection to the RF pad.
A further embodiment includes conducting pads positioned on the surface of the uppermost conducting layer forming the stack.
In a second aspect of the present invention there is provided a method of fabricating a radio frequency (RF) device including the steps of; forming a conducting ground plane on a dielectric substrate, forming on top of the ground plane a layered stack composed of alternate layers of conducting and dielectric layers, interconnecting, in a peripheral region of the device, the ground plane and conducting layers by means of conducting vias thereby to form an enclosed, central region, and forming a conducting RF pad within the central region and on at least one of the dielectric layers.
Brief Description of the Drawings
Preferred embodiments of the invention will now be described, by way of examples only, and with reference to the Figures in which:
Figure 1 is a plan view of an embodiment of a radio frequency device in accordance with the invention;
Figure 2 is a section along the line of 2-2 in Figure 1; and
Figure 3 is a partial view of a cross-section through an alternative embodiment of a radio frequency device in accordance with the invention.
Detailed Description of the Preferred Embodiments
Referring to the Figures, Figure 1 is plan view of a RF device 10, comprising a radio frequency pad or RF-pad 11 surrounded by a conducting structure 13. The RF-Pad 11 is depicted as being mounted on a surface of a semiconductor substrate 12. The structure 13 surrounds the RF-pad 11 and comprises a closed path formed from a metallic conductor, such as aluminium or copper. The conducting structure 13 is hereinafter referred to as a cup 13. It will be appreciated that the cup 13 may be circularly symmetric and have a circular or even oval cross-section. What is important is that the path is a closed path. Cup 13 encloses the RF-pad 11 substantially at its centre. The RF-pad 11 can be circular or indeed of any shape, but a square or a regular polygon is preferred. In one side of the wall of the cup 13 a narrow slit or openinglό is formed, which allows a connection 17 to be made from the pad 11 to an active device, such as a transistor (not shown) formed within the substrate 12.
The construction of RF-pad 11 is similar to that of the conductive walls of the cup 13 and is described in detail below. Different layers of the device 10 are shown in Figure 2.
In Figure 2, a silicon wafer 20 defines a substrate . A layer 24 is generated on the substrate 20 by ion-implantation of an acceptor such as boron. This acceptor ion doping of the substrate 20 is performed in predetermined locations across the surface of the silicon wafer 20 or across the entire wafer surface. An alternative method of forming layer 24 is by epitaxial growth of acceptor doped silicon on substrate 20.
Layer 24 is highly conductive and has a carrier concentration exceeding 10 /cm . The thickness of layer 24 is at least 0.5 microns.
A third silicon layer 26 is then grown using epitaxial growth of acceptor doped silicon on top of layer 24. The doping in the third layer is low and consequently so is the conductivity. The thickness of the third layer 26 is at least 0.5 microns. It should be noted that epitaxial layer 26 is covered by a thin natural Silicon Dioxide layer field oxide after completion of the epitaxial growth of layer 26. For reasons of simplicity the field oxide layer is not depicted.
On the surface of layer 26 there is formed a protective layer of dielectric material such as silicon dioxide 28 which is generated by a chemical vapour deposition (CND) method or by sputtering. The thickness of layer 28 ranges typically from 0.5 to 2.0 microns.
For the construction of a sequence of dielectric followed by metallic layers, the planarity of each dielectric layer is very important. Therefore each dielectric layer is planarised by a chemo-mechanical etching and polishing method CMP so as to yield a surface with minimum roughness.
A first metallic layer 30 is formed on a first dielectric layer 28. The preferred method is by sputtering an aluminium alloy or CND/electroplating of copper. Prior to the deposition of metal to the surface of the dielectric it is necessary to coat the dielectric with a very thin intermediate layer in order to improve the adhesion of metal to dielectric. If aluminium is used as a metal, a thin coating layer of sputtered Titanium Nitride (TiN) is coated on the dielectric. The thickness of the thin coating layer is only several tens of nanometres and for the sake of clarity the coating layer is not shown here.
The metal layer 30 is patterned by photolithography. A structured photoresist (not shown) protects those areas of the metal 30, which will not be etched in a subsequent etching process. The etching process may be either the removal of the unprotected metal in a chemical ion plasma or wet chemical bath. A combination of both steps may be used. Metal layer 30 is typically between 0.1 and 1.0 microns thick.
Next, the metal layer 30 is coated with a thin TiN adhesion layer and a second dielectric layer 33 is then applied by CND method. A CMP process step then follows to achieve planarity of the second dielectric layer 33. A second metal layer 34 is then added at discrete locations to the second dielectric layer 33.
Conductive interconnects are formed between first and second metal layers 30 and 34 by way of small openings, referred to as vias 40 which are formed in the second dielectric layer 33, which are subsequently filled with metal. The position of the vias 40 is defined by photolithography. Nias 40 are etched by an ion plasma beam (not shown) in exposed areas of second dielectric layer 33, which were not protected with photoresist.
The vertical walls of the vias 40 are coated by sputtered TiΝ, to improve adhesion to the vias filling metal. The filling metal is typically tungsten, which is introduced into vias 40 by a CND method. This coating is not shown in the Figures.
As the via filling process generates a rough surface of second dielectric layer 33, due to Tungsten hillock formation, a second CMP step is necessary to achieve a planar dielectric surface. Contact between the via metal and subsequently formed metal layers is by way of an adhesion layer sequence, which is formed on the dielectric layer. The adhesion layer sequence (not shown) comprises thin sputtered layers of Titanium (Ti) and Titanium Νitride(TiΝ). These layers are only several tens of nanometres thick. A second metal layer is formed over the adhesion layer by sputtering or CND of Aluminium and electroplating Copper. The second metal layer is formed in a similar manner to the first layer. By repeating the steps as described above, a stack comprised of alternating dielectric and metal layers, is produced. Figure 2 shows an example of four metal layers 30, 34, 36, 38 separated by three dielectric layers 33, 35, 37. The uppermost metal layer 38 is protected against corrosion by a top dielectric layer39. Openings are etched into this layer to allow electrical access to the RF pad 11 and ground-pads 15.
The cup 13 of Fig 1 with conductive walls is thus formed by appropriate structuring of each of the metal layers and interconnecting these layers with densely packed vias. Hexagonal packing of vias is preferred because this pattern provides the densest packing scheme. The bottom of the cup is made from first metal layer 30.
It is important to note that the heavily doped silicon layer 24 has no direct current (DC) connection to the first metal layer 30. So as to improve the shielding of the bottom of the cup from the heavily doped silicon layer, a good capacitive coupling of this layer to the first metal layer is necessary. Therefore a large overlap zone 100 is produced between layers 24 and 30. This overlap zone needs to be substantially larger than the overlap zone200 of the metal stack forming the RF-pad 11. RF-pad 11 comprises a stack of metal layers separated by insulating dielectric layers. A top plate is the RF-pad area, which provides access to "off chip" electronic circuitry (not shown). The size of this area has a lower limit, typically 50 micron x 50 micron because of packaging rules in the chip assembly factory. To make the RF pad overlap zone 200 independent of the packaging rules, the vertical stack of metal layers beneath the RF-pad area 11 makes connections to the lower areas on the second metal layer 34. This area can be sized for the desired capacitance of the overlap zone 200. The RF-pad 11 and metal stack force the electrical field into a generally vertical direction (that is transverse to the plane defined by the substrate) as the distance between layer 34 and bottom of the cup (i.e. first metal layer) is much smaller than the lateral separation of the RF-pad stack and the surrounding cup walls. To improve additional screening of the heavily doped silicon layer 24 even further, one or more conductive paths between this silicon layer and the bottom of the cup and metal layer 30 maybe added.
In such an alternative embodiment, several regions in the silicon epitaxial layer 24 are heavily doped with an acceptor and connect layer to the surface of epitaxial Silicon layer. Figure 3 shows a P+ sinker implantation 41 is merged with a Source/Drain implantation which is a processing layer in the manufacturing of PMOS devices. An ohmic metallic contact 43 made from Titanium Suicide or Cobalt Suicide connects the P+ doped regions by way of a metal via 44 to the first metal layer 30. This arrangement has the advantage that geometrical design considerations shown in Figure 2 concerning the overlap zones 100 are not necessary.
Outside the cup an RF-signal is transported to an active device (not shown), formed in the silicon substrate 20, by the conductor 17. It is recommended, that the conduct or 17 is a part of a microstrip line, which utilizes the first metal layer 30 as ground plane as shown in
Figure. The electromagnetic field in a microstrip line is mainly straight and vertical between the wire and the ground plane.
In a further embodiment, the RF device 10 is provided with metal pads 45, positioned on the surface of the uppermost metal layers (15 of Fig. 2). The device 10 may then be mounted onto a printed circuit board (PCB) by means of the metal pads 45 which contact a metal trace (which may be grounded) on the surface of the PCB, thus providing the device 10 with a conducting lid. Thus an effectively electrically screened structure is provided. A similar metal pad 46 provided on the RF pad 11 can also be arranged to contact an appropriate metal trace on the PCB.

Claims

1. A radio frequency (RF) device (10) comprising a substrate (20), a conducting ground plane (30) formed thereon, a layered stack (33-39) formed on the conducting ground plane (30) wherein the stack (33-39) is composed of a plurality of conducting layers (34, 36, 38) and a plurality of dielectric layers (33, 35, 37, 39) arranged alternately, and a conducting RF pad (11) wherein, in a peripheral region of the device (10), the conducting ground plane (30) and the conducting layers (34, 36, 38) are interconnected by conducting vias (40) thereby to form an enclosed, central region, and wherein the conducting RF pad (11) is located within the central region and formed on at least one of the dielectric layers (37).
2. A RF device (10) as claimed in Claim 1 in which the RF pad (11) comprises a plurality of conducting layers (34, 36, 38) interconnected by conducting vias (40) and separated from one another by dielectric layers (35, 37).
3. A RF device (10) as claimed in Claim 1 in which the device (10) further includes a conducting base layer (24) and at least one conducting path means (41, 43, 44) interconnecting the base layer (24) with the ground plane (30).
4. A RF device (10) as claimed in Claim 1 wherein the device incorporates a slot (17) in the stack (33-39) for enabling connection to the RF pad (11).
5. A RF device (10) as claimed in Claim 1 and further including conducting pads (45) positioned on the surface of the uppermost conducting layer (38) forming the stack (33-39).
6. A method of fabricating a radio frequency (RF) device (10) including the steps of; forming a conducting ground plane (30) on a dielectric substrate (28), forming on top of the ground plane (30) a layered stack (33-39) composed of alternate layers of conducting (34, 36, 38) and dielectric layer (33, 35, 37, 39), interconnecting, in a periperal region of the device (10), the ground plane (30) and conducting layers (34, 36, 38) by means of conducting vias (40) thereby to form an enclosed, central region, and forming a conducting RF pad (11) within the central region and on at least one of the dielectric layers (37).
7. A method as claimed in Claim 6 in which the dielectric substrate (28) is fabricated by forming a layer of silicon dioxide on a layer of silicon.
8. A method ad claimed in Claim 7 in which the dielectric substrate (28) and each of the dielectric layers (33, 35, 37, 39) are planarised by chemo-mechanical etching and polishing.
9. A method as claimed in Claim 8 in which the conducting layers (34, 36, 38) are formed on the dielectric layers (33, 35, 37, 39) by coating the layers with sputtered titanium nitride, then sputtering aluminium alloy onto the coating.
10. A method as claimed in Claim 6 in which the conducting vias (40) are formed by ion beam plasma etching exposed areas of the dielectric layers (33, 35, 37, 39), coating walls of the vias (40) with sputtered titatium nitride and then filling the vias with tungsten by means of a chemical vapour deposition method.
PCT/EP2002/003764 2001-04-06 2002-04-02 A radio frequency (rf) device and its method of manufacture WO2002082539A2 (en)

Priority Applications (1)

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AU2002304813A AU2002304813A1 (en) 2001-04-06 2002-04-02 A radio frequency (rf) device and its method of manufacture

Applications Claiming Priority (2)

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GBGB0108762.6A GB0108762D0 (en) 2001-04-06 2001-04-06 A high frequency (HF)device and its method of manufacture
GB0108762.6 2001-04-06

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Publication number Priority date Publication date Assignee Title
EP1465255A3 (en) * 2003-04-04 2007-05-02 Sharp Kabushiki Kaisha Integrated circuit

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JPS60137050A (en) * 1983-12-26 1985-07-20 Toshiba Corp Semiconductor device

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JP2000150802A (en) * 1998-11-18 2000-05-30 Nec Corp Method for shielding analog signal pad and semiconductor integrated circuit

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Publication number Priority date Publication date Assignee Title
EP1465255A3 (en) * 2003-04-04 2007-05-02 Sharp Kabushiki Kaisha Integrated circuit

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WO2002082539A3 (en) 2003-07-31
AU2002304813A1 (en) 2002-10-21
GB0108762D0 (en) 2001-05-30

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