WO2002082448A1 - Identification d'un circuit integre a partir de ses parametres physiques de fabrication - Google Patents
Identification d'un circuit integre a partir de ses parametres physiques de fabrication Download PDFInfo
- Publication number
- WO2002082448A1 WO2002082448A1 PCT/FR2002/001192 FR0201192W WO02082448A1 WO 2002082448 A1 WO2002082448 A1 WO 2002082448A1 FR 0201192 W FR0201192 W FR 0201192W WO 02082448 A1 WO02082448 A1 WO 02082448A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- identification
- circuit
- delay
- integrated circuit
- terminal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
- H03K5/15066—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using bistable devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
Definitions
- the present invention relates to the identification of an electronic element or assembly from parameters related to the manufacture of an identification circuit contained in an integrated circuit chip.
- identification generally uses a network of physical parameters (PPN) related to the manufacture of the integrated circuit chip.
- PPN physical parameters
- This identification is commonly designated by the Anglo-Saxon expression "integrated circuit fingerprint”.
- a first family of known identification methods consists in measuring electrical parameters of the integrated circuit chip. It may, for example, be a measurement of a threshold voltage of a transistor, a resistance measurement or a measurement of a stray capacitance. As these characteristics are sensitive to technological and manufacturing process dispersions, it can be considered that the electrical parameter or parameters taken into account are specific to a manufacturing and constitute a "signature" of the integrated circuits resulting from this manufacturing.
- An example of a process using measurement of electrical parameters is described in US Pat. No. 6,161,213.
- One drawback of using an electrical parameter measurement is that these quantities change over time (in the life of the circuit). Consequently, the signature obtained is not stable.
- Another disadvantage is that it is necessary to make the difference between a measured signature (for example, the voltage across a capacitor) and a predefined signature. It is therefore necessary to have an analog / digital converter to convert the measured signals before making the difference allowing the identification.
- the converter In addition to the stability problems, the converter must be very precise because of the small variations which have to be measured. Indeed, these are technological dispersions which, by nature, are very low (for example, for the threshold voltage of an MOS transistor, the dispersion is generally +/- 4 millivolts. For a voltage measurement, it It could be a matter of detecting a difference of less than one millivolt over a value range of around 200 millivolts, for example, a 12-bit converter is required.
- a second family of known solutions uses a time measurement. For example, the read / write time of an EEPROM type memory is measured.
- An example of an identification method using a measurement of the execution time of operations is described in US Patent No. 5,818,738.
- the invention aims to propose a new way of identifying an electronic assembly or element from physical parameters of an integrated circuit chip it contains.
- the invention aims, more particularly, to propose a new identification method as well as a new network type identification circuit of physical parameters which overcomes at least one of the drawbacks of known methods and circuits.
- the invention also aims to propose a solution which avoids the use of analog-digital converters or counters.
- the present invention also aims to propose a solution that requires little integration surface.
- the invention also aims to propose a solution which is particularly sensitive to technological and manufacturing process dispersions, while being stable over time.
- the invention further aims to propose a solution which is compatible with internal or external processing of the identification code obtained.
- the present invention provides a network type identification circuit of physical parameters contained in an integrated circuit chip, comprising: a single input terminal for application of an identification trigger signal; output terminals suitable for delivering a binary identification code; first electrical paths individually connecting said input terminal to each output terminal, each path providing a delay sensitive to dispersions technological and / or manufacturing process of the integrated circuit; and means for simultaneously taking into account the binary states present at the output of the electrical paths.
- each electrical path consists of a delay element and a flip-flop, an input terminal of which is connected at the output of the corresponding delay element and an output terminal of which defines one of identification circuit output terminals.
- said means for taking into account comprise a second electrical path providing a delay corresponding approximately to the average delay of the delays brought by said first paths, said second path being interposed between said input terminal and a trigger terminal for taking into account said binary states.
- the clock inputs of the different flip-flops are all connected to said trigger terminal.
- the electrical paths are chosen to provide delays of the same order of magnitude, despite the technological dispersions.
- the invention also provides a method for identifying an integrated circuit chip on the basis of these physical parameters sensitive to technological dispersion, consisting in comparing an average journey time of a digital signal with respect to at least two others electrical paths of the same digital signal. According to an embodiment of the present invention, the taking into account of the comparisons is synchronized from the digital input signal.
- FIG. 1 represents an embodiment of an integrated identification circuit according to the present invention
- FIGS. 2A and 2B illustrate, in the form of timing diagrams, the operation of the identification circuit of FIG. 1, for two different integrated circuits.
- a characteristic of the present invention is to subject, to the same input signal (logic signal comprising at least one edge), several different delays originating from electrical paths each providing a significant delay to technological and / or manufacturing process dispersions. .
- Another characteristic of the invention is not to measure the effects of technological dispersions in terms of time difference but to provide a direct comparison of the delays brought by the different paths compared to an average delay.
- FIG. 1 represents the electrical diagram of an embodiment of an integrated identification circuit according to the present invention.
- circuit 1 comprises a single input terminal 2 intended to receive a digital signal E triggering an identification.
- the signal E must comprise, as will be seen hereinafter in relation to FIGS. 2A and 2B, at least one edge per identification.
- the role of the identification circuit 1 is to deliver a binary code B ⁇ , B2, ..., 'B ⁇ -i, Bi, ..., N. &- ⁇ , B JJ on a predetermined number of bits, this code being sensitive to technological dispersions and circuit manufacturing process.
- Each bit Bi is delivered on a terminal 3 ⁇ , 32 ••• / 3 il ' 3 i »•••' 3 nl» 3 n ⁇ u circuit 1 which is specific to it. Circuit 1 therefore delivers the identification code in parallel form.
- each bit Bi of the identification code is associated with an electrical path P] _, P2, ..., Pi, ..., P n connecting the common input terminal 2 to a terminal 3i of same rank.
- the delays brought by the different electrical paths Pi are chosen to be slightly different from each other so as to guarantee sensitivity to the technological dispersions of the manufacturing process.
- an average electrical path 4 (C0) is provided for fixing the instant of reading from the appearance of the trigger edge of the input signal.
- each electrical path Pi includes a delay element 6 ⁇ (Cl), 62 (C2) ..., 6 ⁇ (Ci) ..., 6 n (Cn) connecting input 2 of the circuit to input D of the corresponding flip-flop on the path.
- the delay elements 6i are the elements which, according to the present invention, have different delays with respect to each other.
- the flip-flops 5i preferably have the same constitution. However, they participate in the delay brought to the input signal to the respective output terminals of the circuit 1 with respect to the average delay CO brought by the element 4.
- circuit 1 are individually connected at the input of a register 7 for storing the binary code obtained, each bit Bi corresponding to one of the outputs of the circuit.
- the connection and constitution details of the register 7 have not been shown and are not the subject of the present invention. Once the binary code is contained in this register, its exploitation depends on the application, and its implementation is within the reach of those skilled in the art.
- FIGS. 2A and 2B illustrate, in the form of timing diagrams and without respect for scale, the operation of an identification circuit according to the invention.
- FIGS. 2A and 2B show examples of patterns of the signal E, and of the signals at the output of the different delay elements.
- the chronograms have been designated by the references CO, Cl, C2, C3 and C4.
- FIGS. 2A and 2B represents the difference between two circuits 1 integrated on chips from different manufacturers.
- FIG. 2B illustrates the same circuit resulting from a different manufacturing process therefore giving a different chip.
- the code obtained is different. For example, it is the code 0010.
- an instant t5 has been made arbitrarily identical to the case in FIG. 2A.
- the instants t'0, t'1, t'2, t'3 and t'4 at which the edge of the signal E has finished traversing the respective paths C0, Cl, C2, C3 and C4 are different from the case of Figure 2A.
- the retarding element C0 is itself sensitive to technological and manufacturing process dispersions. This does not, however, affect the implementation of the invention since this delay represents an average delay and the identification code sought is arbitrary. Indeed, for an implementation of the invention to a network type identification of physical parameters, what is important is that integrated circuits originating from the same manufacturing process provide the same code. As the retarding elements are sensitive to dispersions in the manufacturing process, this will be the case with the implementation of the invention.
- An advantage of the present invention is that the identification is particularly precise and reliable. In particular, by eliminating the need for a measurement (of voltage or of time), one frees oneself from the problems of accuracy of converters or counters.
- the identification circuit is particularly sensitive.
- the detectable difference of the delays brought by the different paths is of the order of a picosecond.
- the dispersions of the manufacturing or technological processes most often bring differences of the order of at least ten picoseconds.
- Another advantage of the present invention is that in the event of a drift in time of one of the delays provided by the elements, this does not affect the results of the circuit. Indeed, all the delay elements preferably being of similar constitution, the dispersion will be in the same direction for all the elements (paths).
- any integrated elements sensitive to technological dispersions or influenced by the manufacturing process may be used. It could be, for example, series of resistors and / or capacitors.
- resistors it will be possible to use resistors in the thickness of the integrated circuit, but it will be preferable to use resistors in polycrystalline silicon whose value is linked to the geometry and which have the advantage of being less dependent on the temperature.
- an identification phase is triggered by an edge of the input signal E. The number of phases depends on the application and the destination of the identification circuit. If it is a smart card, provision may be made, for example, for an identification for each exchange carried out between this card and an external device, even during the same transaction.
- the present invention is susceptible of various variants and modifications which will appear to one skilled in the art.
- the practical implementation of the retarding elements of the invention may take different forms, provided that they are sensitive to techno-logical dispersions and / or manufacturing processes.
- the number of bits of the code supplied by the circuit of the invention also depends on the desired sensitivity. The higher the number of bits, the more the circuit will be sensitive to code variations.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computer Security & Cryptography (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/473,058 US7178113B2 (en) | 2001-04-04 | 2002-04-04 | Identification of an integrated circuit from its physical manufacture parameters |
EP02730354A EP1397806B1 (fr) | 2001-04-04 | 2002-04-04 | Identification d'un circuit integre a partir de ses parametres physiques de fabrication |
DE60205374T DE60205374D1 (de) | 2001-04-04 | 2002-04-04 | Identifikation einer integrierten schaltung aus ihren physikalischen herstellungsparametern |
JP2002580328A JP3991865B2 (ja) | 2001-04-04 | 2002-04-04 | 物理的製造パラメータによる集積回路の識別 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR01/04585 | 2001-04-04 | ||
FR0104585A FR2823341B1 (fr) | 2001-04-04 | 2001-04-04 | Identification d'un circuit integre a partir de ses parametres physiques de fabrication |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002082448A1 true WO2002082448A1 (fr) | 2002-10-17 |
Family
ID=8861936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2002/001192 WO2002082448A1 (fr) | 2001-04-04 | 2002-04-04 | Identification d'un circuit integre a partir de ses parametres physiques de fabrication |
Country Status (6)
Country | Link |
---|---|
US (1) | US7178113B2 (fr) |
EP (1) | EP1397806B1 (fr) |
JP (1) | JP3991865B2 (fr) |
DE (1) | DE60205374D1 (fr) |
FR (1) | FR2823341B1 (fr) |
WO (1) | WO2002082448A1 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9887721B2 (en) | 2011-03-02 | 2018-02-06 | Nokomis, Inc. | Integrated circuit with electromagnetic energy anomaly detection and processing |
US10475754B2 (en) | 2011-03-02 | 2019-11-12 | Nokomis, Inc. | System and method for physically detecting counterfeit electronics |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2823340A1 (fr) | 2001-04-04 | 2002-10-11 | St Microelectronics Sa | Stockage d'un code binaire immuable dans un circuit integre |
FR2829855A1 (fr) * | 2001-09-14 | 2003-03-21 | St Microelectronics Sa | Identification securisee par donnees biometriques |
US7292019B1 (en) | 2005-10-03 | 2007-11-06 | Zilker Labs, Inc. | Method for accurately setting parameters inside integrated circuits using inaccurate external components |
US9970986B2 (en) * | 2014-03-11 | 2018-05-15 | Cryptography Research, Inc. | Integrated circuit authentication |
CN108008229B (zh) * | 2017-11-03 | 2020-01-31 | 杭州长川科技股份有限公司 | 指纹模组标识码扫描装置及扫描方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3911368A (en) * | 1974-06-20 | 1975-10-07 | Tarczy Hornoch Zoltan | Phase interpolating apparatus and method |
US4023110A (en) * | 1975-12-04 | 1977-05-10 | The United States Of America As Represented By The Secretary Of The Army | Pulse comparison system |
US4675612A (en) * | 1985-06-21 | 1987-06-23 | Advanced Micro Devices, Inc. | Apparatus for synchronization of a first signal with a second signal |
US5204559A (en) * | 1991-01-23 | 1993-04-20 | Vitesse Semiconductor Corporation | Method and apparatus for controlling clock skew |
DE19510038C1 (de) * | 1995-03-20 | 1996-08-14 | Siemens Nixdorf Inf Syst | Anordnung zum Autokalibrieren der Taktverteilung bei synchronen digitalen Schaltungen |
US5608645A (en) * | 1994-03-17 | 1997-03-04 | Vlsi Technology, Inc. | Method of finding a critical path in a circuit by considering the clock skew |
US5686850A (en) * | 1992-01-31 | 1997-11-11 | Konica Corporation | Signal delay method, signal delay device and circuit for use in the apparatus |
EP1148647A2 (fr) * | 2000-04-04 | 2001-10-24 | Infineon Technologies AG | Arrangement de circuit pour la réception d'au moins deux signaux digitaux |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8924203D0 (en) * | 1989-10-27 | 1989-12-13 | Ncr Co | Delay measuring circuit |
JP2776247B2 (ja) * | 1993-11-17 | 1998-07-16 | 日本電気株式会社 | 半導体集積回路及びその製造方法 |
US5663767A (en) * | 1995-10-25 | 1997-09-02 | Thomson Consumer Electronics, Inc. | Clock re-timing apparatus with cascaded delay stages |
TW340262B (en) * | 1996-08-13 | 1998-09-11 | Fujitsu Ltd | Semiconductor device, system consisting of semiconductor devices and digital delay circuit |
JPH1124785A (ja) * | 1997-07-04 | 1999-01-29 | Hitachi Ltd | 半導体集積回路装置と半導体メモリシステム |
US5867453A (en) * | 1998-02-06 | 1999-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-setup non-overlap clock generator |
JP3789247B2 (ja) * | 1999-02-26 | 2006-06-21 | Necエレクトロニクス株式会社 | クロック周期検知回路 |
US6795931B1 (en) * | 1999-09-30 | 2004-09-21 | Micron Technology, Inc. | Method and apparatus for an adjustable delay circuit having arranged serially coarse stages received by a fine delay stage |
US6292024B1 (en) * | 1999-12-14 | 2001-09-18 | Philips Electronics North America Corporation | Integrated circuit with a serpentine conductor track for circuit selection |
-
2001
- 2001-04-04 FR FR0104585A patent/FR2823341B1/fr not_active Expired - Fee Related
-
2002
- 2002-04-04 EP EP02730354A patent/EP1397806B1/fr not_active Expired - Fee Related
- 2002-04-04 US US10/473,058 patent/US7178113B2/en not_active Expired - Lifetime
- 2002-04-04 JP JP2002580328A patent/JP3991865B2/ja not_active Expired - Fee Related
- 2002-04-04 WO PCT/FR2002/001192 patent/WO2002082448A1/fr active IP Right Grant
- 2002-04-04 DE DE60205374T patent/DE60205374D1/de not_active Expired - Lifetime
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3911368A (en) * | 1974-06-20 | 1975-10-07 | Tarczy Hornoch Zoltan | Phase interpolating apparatus and method |
US4023110A (en) * | 1975-12-04 | 1977-05-10 | The United States Of America As Represented By The Secretary Of The Army | Pulse comparison system |
US4675612A (en) * | 1985-06-21 | 1987-06-23 | Advanced Micro Devices, Inc. | Apparatus for synchronization of a first signal with a second signal |
US5204559A (en) * | 1991-01-23 | 1993-04-20 | Vitesse Semiconductor Corporation | Method and apparatus for controlling clock skew |
US5686850A (en) * | 1992-01-31 | 1997-11-11 | Konica Corporation | Signal delay method, signal delay device and circuit for use in the apparatus |
US5608645A (en) * | 1994-03-17 | 1997-03-04 | Vlsi Technology, Inc. | Method of finding a critical path in a circuit by considering the clock skew |
DE19510038C1 (de) * | 1995-03-20 | 1996-08-14 | Siemens Nixdorf Inf Syst | Anordnung zum Autokalibrieren der Taktverteilung bei synchronen digitalen Schaltungen |
EP1148647A2 (fr) * | 2000-04-04 | 2001-10-24 | Infineon Technologies AG | Arrangement de circuit pour la réception d'au moins deux signaux digitaux |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9887721B2 (en) | 2011-03-02 | 2018-02-06 | Nokomis, Inc. | Integrated circuit with electromagnetic energy anomaly detection and processing |
US10475754B2 (en) | 2011-03-02 | 2019-11-12 | Nokomis, Inc. | System and method for physically detecting counterfeit electronics |
US11450625B2 (en) | 2011-03-02 | 2022-09-20 | Nokomis, Inc. | System and method for physically detecting counterfeit electronics |
Also Published As
Publication number | Publication date |
---|---|
EP1397806B1 (fr) | 2005-08-03 |
JP3991865B2 (ja) | 2007-10-17 |
DE60205374D1 (de) | 2005-09-08 |
FR2823341A1 (fr) | 2002-10-11 |
US20040125930A1 (en) | 2004-07-01 |
EP1397806A1 (fr) | 2004-03-17 |
FR2823341B1 (fr) | 2003-07-25 |
US7178113B2 (en) | 2007-02-13 |
JP2004526970A (ja) | 2004-09-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1267248B1 (fr) | Stockage protégé d'une donnée dans un circuit intégré | |
EP1397806B1 (fr) | Identification d'un circuit integre a partir de ses parametres physiques de fabrication | |
WO2002082389A2 (fr) | Extraction d'une donnee privee pour authentification d'un circuit integre | |
EP0875830B1 (fr) | Circuit testable à faible nombre de broches | |
FR2837960A1 (fr) | Entite electronique transactionnelle securisee par mesure du temps | |
FR2833119A1 (fr) | Generation de quantites secretes d'identification d'un circuit integre | |
EP1483763A1 (fr) | Extraction d un code binaire a partir de parametres physique s d un circuit integre | |
EP1359550A1 (fr) | Régéneration d'une quantité secrète à partir d'un identifiant d'un circuit intégré | |
WO2006030160A1 (fr) | Lecture de l'etat d'un element de memorisation non volatile | |
FR2768276A1 (fr) | Generateur d'alea | |
EP0965994B1 (fr) | Dispositif à circuit intégré sécurisé au moyen de lignes complémentaires de bus | |
EP0884704B1 (fr) | Procédé d'authentification de circuit intégré | |
EP1291817B1 (fr) | Détection d'une variation de l'environnement d'un circuit intégré | |
EP1374242B1 (fr) | Stockage d'un code binaire immuable dans un circuit integre | |
EP1420416A1 (fr) | Cellule mémoire à trois états | |
FR2656940A1 (fr) | Circuit integre a microprocesseur fonctionnant en mode rom interne et eprom externe. | |
FR2810438A1 (fr) | Circuit de detection d'usure | |
EP0241086B1 (fr) | Dispositif comportant des circuits accordés sur des fréquences données | |
FR2659767A1 (fr) | Circuit de caracterisation de microcircuits, lecteur enregistreur de carte a microcircuits, et carte a microcircuits associee. | |
FR2901362A1 (fr) | Circuit de qualification et de caracterisation d'une memoire embarquee dans un produit semi-conducteur | |
FR3106424A1 (fr) | Procédé pour générer une donnée unique propre à un circuit intégré en silicium | |
FR2846461A1 (fr) | Compteur par tranches | |
FR2890465A1 (fr) | Procede de generation d'un signal d'horloge | |
FR2837959A1 (fr) | Entite electronique transactionnelle autonome securisee par mesure du temps s'ecoulant entre deux transactions successives | |
WO2003038742A1 (fr) | Carte a microcircuit sans contact incorporant un clavier et procede d'utilisation d'une telle carte |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2002580328 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2002730354 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10473058 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 2002730354 Country of ref document: EP |
|
WWG | Wipo information: grant in national office |
Ref document number: 2002730354 Country of ref document: EP |