WO2002080371A1 - Convertisseur numerique-analogique - Google Patents

Convertisseur numerique-analogique Download PDF

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Publication number
WO2002080371A1
WO2002080371A1 PCT/JP2001/002680 JP0102680W WO02080371A1 WO 2002080371 A1 WO2002080371 A1 WO 2002080371A1 JP 0102680 W JP0102680 W JP 0102680W WO 02080371 A1 WO02080371 A1 WO 02080371A1
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WO
WIPO (PCT)
Prior art keywords
resistance
members
output
switching
control signal
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Application number
PCT/JP2001/002680
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English (en)
Japanese (ja)
Inventor
Kouji Kitagawa
Original Assignee
Yozan Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Yozan Inc. filed Critical Yozan Inc.
Priority to JP2002578659A priority Critical patent/JPWO2002080371A1/ja
Priority to PCT/JP2001/002680 priority patent/WO2002080371A1/fr
Publication of WO2002080371A1 publication Critical patent/WO2002080371A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H03M1/682—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits both converters being of the unary decoded type
    • H03M1/685—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits both converters being of the unary decoded type the quantisation value generators of both converters being arranged in a common two-dimensional array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/76—Simultaneous conversion using switching tree
    • H03M1/765—Simultaneous conversion using switching tree using a single level of switches which are controlled by unary decoded digital signals

Definitions

  • the present invention relates to a DA converter for converting a digital signal into an analog signal, and more particularly to a DA converter having a differential output resistance voltage divider.
  • This type of DA converter connects a large number of resistors in series, connects the output voltage of each resistor to the output via a switch, and opens and closes the switch in response to the digital signal.
  • An analog signal having a size corresponding to the data is generated.
  • the number of switches corresponds to the number of analog signal levels, and increases as the resolution increases.
  • the conventional DA converter could not obtain a sufficient response speed. That is, the conventional differential output resistance voltage dividing DA converter has a problem that the circuit scale is large and the response speed is low.
  • the present invention has been conceived to solve such a conventional problem, and has as its object to provide a differential output resistance voltage dividing DA converter having a small circuit scale.
  • a further object of the present invention is to provide a differential output resistance voltage dividing type DA converter having a high response speed.
  • the DA converter according to the present invention is provided with “2 m” (where m is a natural number) resistance members having substantially the same resistance value connected in series, and provided in correspondence with the respective resistance members.
  • a unit having '2 m' switching members connected to the end of the corresponding resistance member, and '2 m' switching units of the unit provided for each unit An output end to which the other side of the material is connected in common, and a unit assembly consisting of 'n' units (where n is a natural number) connected in series, one side of which is connected to the reference voltage
  • a switching member for connecting an output terminal corresponding to one selected unit in the unit assembly to an output line, and the 2 m switching members provided for each unit are provided.
  • the 'n' switching members located at mutually corresponding arrangement positions among the units in the unit assembly are collectively closed by a common control signal.
  • the resistance members of '2m' connected in series in this unit are characterized in that 'm' pieces of the resistance members are arranged separately for the forward path and the return path.
  • the number of control signal lines can be reduced by using a common control signal by combining the opening and closing of the switching member and the switching of the switching member. Can be scaled down.
  • the DA converter according to the present invention includes “2 ⁇ 2m n” (where m and n are natural numbers) resistance members connected in series with respect to the reference voltage, each of which has substantially the same resistance.
  • '2 X 2mn' switching members which are provided corresponding to the members, and one side is connected to the corresponding resistance member end, and '2m' number of the '2x 2mn' resistance members connected in series '2 ⁇ ' units configured for each of the resistance members and '2m' units provided for each of the '2m' resistance members of the unit
  • Switching switching member to be switched the '2X 2mn' resistance members connected in series, and the resistance portion '2X 2mn' switching members and '2 ⁇ ' switching switching members, which are provided in accordance with, are counted as '2mn'-th and' 2mn + 1'-th resistors, counting from one side of the resistance member connection direction.
  • the DA converter according to the present invention can reduce the number of control signal lines of the switching member by combining the opening and closing of the switching member and the switching of the switching member, and further sharing the control signal of the switching member.
  • the circuit scale can be reduced, and DA conversion with high resolution can be performed with the improvement of the response speed.
  • the DA converter according to the present invention is characterized in that the '2x2mn' series-connected resistance members are arranged in a matrix of 'm, rows' 2 ⁇ 2 ⁇ , columns. Further, in the DA converter according to the present invention, the '2X 2mn' switching members correspond to each other such that a voltage drop between the switching members adjacent to each other in the connection direction of the resistance member is substantially constant. And connected to the end of the resistance member.
  • the “2m” resistance members connected in series are further divided into “m” pieces each of the forward path side and the return path side, and “m” rows, “2”, columns Are arranged in a matrix.
  • the unit in which the '2m' resistance members connected in series are arranged in 'm' rows and '2' columns includes two connection end pairs and a resistance member provided between each of the connection end pairs.
  • a resistance cell having two switching members, two switching members connected to one end of each of the resistance members, and one detection end connected to one of the connection ends of the connection end pair via the switching member is denoted by 'm'. It is characterized in that it is configured by connecting individual components.
  • the switching member is constituted by a 1-input / 3-output multiplexer, the first output and the second output of the multiplexer are respectively connected to two output lines, and the third output is It is characterized by an invalid output that is not connected to either of the two output lines.
  • the '2mn' series-connected resistance members divided into two groups around the virtual line are arranged in 'm' rows and '2 ⁇ ' columns, respectively. It is characterized by being.
  • the '2X 2mn' switching members may be selected from only one switching member for each unit of '2 m' resistance members connected in series. It is characteristically closed.
  • the DA converter according to the present invention is characterized in that the switching control signal and the connection control signal are supplied by converting a digital signal, and generate an analog output with a potential difference between two output lines. .
  • the number of signal lines of the opening / closing control signal for controlling the opening / closing of the '2 X 2mn' switching members is '2m'
  • the '2 ⁇ ' switching switching members have It is characterized in that the number of connection control signal lines for controlling connection is '2 ⁇ '.
  • the number of signal lines of the opening / closing control signal for controlling the opening / closing of the “2 ⁇ 2mn” switching members, “2m”, is defined by the number of outputs of predetermined lower-order bits of the digital signal
  • the number of signal lines of the connection control signal for controlling the connection of the '2 ⁇ ' switching members is defined by the number of outputs of predetermined upper bits of the digital signal.
  • the D / A converter according to the present invention can further reduce the circuit scale, improve the response speed, and is suitable for integration into an integrated circuit.
  • the DA converter according to the present invention is characterized in that a resistor array having the resistance member, the switching unit, the output terminal, and the switching member is provided with a no-pass resistor.
  • each resistance member used in the resistance array can be set so large that the parasitic resistance can be ignored, so that the influence of the parasitic resistance can be reduced and the conversion accuracy can be improved.
  • FIG. 1 is a block diagram showing a configuration of a DA converter according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram illustrating a schematic configuration of the resistor array RARY in the embodiment.
  • FIG. 3 is a circuit diagram showing a control system of the resistor array RARY described in FIG.
  • FIG. 4 is a circuit diagram showing details of the resistance cells LC and RC in the embodiment.
  • FIG. 5 is a diagram showing a relationship between a digital signal DI input and an analog signal DAO output in the above embodiment.
  • FIG. 6 is a block diagram in which the resistor array RARY of the above embodiment is applied to a DA converter for processing a 5-bit digital signal DI.
  • FIG. 7 is a relationship diagram between the digital signal DI in the DA converter and the analog signal DA0 output from the resistor array RARY.
  • FIG. 8 shows another embodiment having a main resistor and a sub resistor.
  • FIG. 1 is a block diagram illustrating a configuration of a DA converter according to an embodiment of the present invention.
  • a digital signal DI of a plurality of bits is
  • control signal is converted into control signal CTL by EC, and the operation of the resistor array RARY is controlled by this control signal CTL.
  • the resistor array RARY is an analog signal DA having a magnitude corresponding to the value of the digital signal DI.
  • the setting of the decoder DEC is determined according to the correspondence between the digital signal DI and the control signal CTL supplied to the resistor array RARY.
  • FIG. 2 is a circuit diagram showing a schematic configuration of the resistor array RARY of the present embodiment.
  • the resistance array RARY has 'mxn' resistance cells LC (i, j) and RC (i, j) (where i and j are integers, l ⁇ i ⁇ m, 1 j ⁇ n). It is composed of
  • the 'mxn' resistance cells LC (i, j) and RC (i, j) are two-dimensionally arranged in 'm' rows and ' ⁇ ' columns, respectively, and the resistance cells LC (1, 1) to LC (m , n), and a resistance cell matrix R composed of resistance cells RC (1, 1) to RC (m, n).
  • the resistance cell matrix LCM and the resistance cell matrix RCM are arranged such that their corresponding rows are aligned in the resistance array RARY, and as a whole of the resistance array RARY, all the resistance cells LC, RC Are two-dimensionally arranged in 'm, row' 2 ⁇ , column, and arranged in a matrix.
  • the ' ⁇ ' column of the resistance cell matrix LCM and the resistance cell There is a column center line X—X in the two-dimensional array between all the resistance cells LC and RC arranged in the above “m” row and “2 ⁇ ” column between the '1' and the column of the matrix RCM. I do.
  • the individual resistance cells LC (i, j) and RC (i, j) have the same configuration, and have a two-terminal pair circuit shape.
  • each of the resistance cells LC (i, j) and RC (i, j) are connected to the outside in the axial direction of each cell, for connection with the outside, by the electric connection terminals ai and bi and the electric connection terminals ao and bo. Are provided as a pair.
  • each of the resistance cells LC (i, j) and RC (i, j) has an electric connection terminal ai, ao, bi, and bo, and an output for extracting the output. An end oup is provided separately.
  • This output terminal 0 up is connected to each terminal pair ai-ao, bi-bo via switching members Sa, Sb, respectively, and the switching members Sa, Sb are connected to resistance members Ra, Rb Is provided in correspondence with.
  • the specific configuration of each resistance cell LC (i, j), RC (i, j) will be described with reference to FIG.
  • the adjacent resistance cells LC (i, j) and LC (i + 1, j) or RC (i, j) and RC (i + 1, j) in the column direction are connected to one resistance cell LC (i, j).
  • RC (i, j) are connected to the connection terminals ai and bi of the other resistance cell LC (i + 1, j) or RC (i + 1, j), respectively. Connected.
  • resistance cells LC (1, j) to LC (m, j) are electrically connected in series.
  • 'M' resistor cells LC (1, j) to linearly arranged in the column direction: LC (m, j), RC (1, j) to RC (m, j), and the other end in the column direction.
  • the connection terminals ao and bo of the resistance cells LC (m, j) and RC (m, j) on the side are electrically connected to each other.
  • the resistance cell matrix LCM For example, in the resistance cell matrix LCM, 'j' linearly arranged in the column direction and 'm' resistance cells LC (1, j) to LC (1, j) to; LC (m, j), the other end in the column direction
  • the connection ends ao and bo of the resistance cell LC (m, j) are electrically connected to each other.
  • the resistance cells LC (1, j) at one end in the column direction are determined.
  • connection terminal ai The current input from the connection terminal ai is converted from the connection terminal a0 of the resistance cell LC (1, j) to the connection terminal ai of the resistance cell LC (2, j) to the connection terminal ai of the resistance cell LC (i, j). Through ao, it flows to the connection end ai of the resistance cell LC (m, j) on the other end in the column direction.
  • connection ends ao and b0 Because of the electrical connection, this time, conversely, from the connection end bi of this resistance cell LC (m, j), the connection end b 0 of the resistance cell LC (m, j) ) Flows through the connection terminals ao and ai of the resistance cell LC (1, j) to the connection terminal bo of the resistance cell LC (1, j), and is output from the connection terminal bi of the resistance cell LC (1, j).
  • 'm' resistance cells LC (1, j) to LC (m, j) and RC (1, j) to RC (m , j) is a resistance cell unit L CU (j) in which '2m pieces of resistance members Ra and Rb having substantially the same resistance value are connected in series in the column direction by' m 'pieces each in a forward direction and a return direction.
  • Configure RCU (J)
  • connection ends ai of the resistance cells LC (1, j), RC (1, j) at one end in the column direction of the resistance cell units LCU (j), RCU (j) in the j-th row are adjacent rows.
  • a certain 'j — resistance cell units LCU (j-1) and RCU (j-1) at one end in the column direction of the resistance cell units LC (1, j-1) and RC (1, j-1) Is electrically connected to the connection end bi.
  • the resistance cell units LCU (1) to LCU (n) and RCU (1) to RCU (n) are also electrically connected in series.
  • resistance members Ra and Rb having substantially the same resistance value are connected in series. It is a two-dimensional array with 'm' rows, '2 ⁇ , columns. Furthermore, the resistance cell units LCU (n) and RCU (1), which are arranged in the row direction across the column center line X—X, are also connected to the resistance cell LC (1, n) at one end in the column direction.
  • the terminal bi is electrically connected to the connection terminal ai of the resistance cell RC (1, 1).
  • the resistance cell matrices LCM and RCM are also electrically connected to each other.
  • the resistance members Ra and Rb having substantially the same resistance value are: 'm, rows' 2 ⁇ 2 ⁇ ' columns are two-dimensionally arranged, and '2x2mn' resistance members with almost the same resistance are electrically connected in series.
  • the resistance of the resistance cell matrix LCM constituting the starting end of the series-connected resistance members Ra and Rb The connection terminal ai of the cell LC (1, 1) is connected to the first reference voltage (high voltage) Vd da.
  • the connection end bi of the resistance cell RC (1, n) of the resistance cell matrix RCM constituting the termination of the series-connected resistance members Ra and Rb is connected to the second reference voltage (low voltage, The low voltage in this case includes the ground potential.) It is connected to V0.
  • the switching members Sa and Sb are provided corresponding to the resistance members Ra and Rb, respectively, via the switching members Sa and Sb, respectively.
  • a pair of terminals ai-ao and bi-bo provided with corresponding resistance members Ra and Rb are connected to the output terminal oup.
  • the output end o up is connected to the output side (current outflow side) of the resistance members Ra and Rb via the switching members Sa and Sb, respectively.
  • the output terminals 0 up of the resistance cells LC (1, j) to (! N, j) and RC (1, j) to (! N, j) are connected to the resistance cell units LCU (j) and RCU, respectively. (j), and a one-input / three-output multiplexer MUXL (j), MUXR () provided via a common output line and provided for each of the resistance cell units LCU (j) and RCU (j). j) is connected to the input terminal.
  • Each multiplexer MUX L (j), MUXR (j) has its first and second output terminals. Are connected to two output lines consisting of the positive output Pout and the negative output Mout, respectively, and the remaining third output is connected to both the positive output Pout and the negative output Mout. Invalid output terminal not connected.
  • the multiplexers MUXL (1) to MUXL (n) and MUXR (1) to MUXR (n) are provided corresponding to the resistance cell units LCU (1) to (! 1) and RCU (1) to (n). , One of the multiplexers MUXL (1) to MUXL (n) and one of the multiplexers MUXR (1) to MUXR (n) based on the control signal CTL supplied from the aforementioned decoder DEC. One input terminal is connected to the positive output Po ut and the negative output Mo ut, respectively, and the input terminals of the other multiplexers are connected to the invalid output terminal.
  • FIG. 3 is a circuit diagram showing a control system of the resistor array RARY described in FIG.
  • the control signal CTL generated by converting the digital signal DI by the above-described decoder DEC includes all the resistance cells LC (1, 1) to LC (m, n) and RC (1, 1) to RC (m, n), and all the multiplexers MUX L (1) to MUXL (n) and MUXR (1) to MUXR (n).
  • each resistance cell LC (i, 1) to LC (i, n) and RC (i, 1;) to RC (i, n) in the same row direction are two control signals CTL ( i) a, CTL (i) b are supplied.
  • Each of the control signals CTL (i) a and CTL (i) b controls the opening and closing of the switching member Sa or Sb, which is based on the ONZOFF signal (open Z close signal).
  • This common two control signals CTL (i) a for each of the resistance cells LC (i, 1) to LC (i, n) and RC (i, 1) to RC (i, n) in the same row direction.
  • the connection method of CTL (i) b is for the resistance cells LC (i, 1) to LC (i, n) and for the resistance cells RC (i, 1) to RC (i, n).
  • the connection of the control signals CTL (i) a and CTL (i) b to the switching members Sa and Sb is switched.
  • the control signal Signal CTL (i) a controls the switching member Sa
  • the control signal CTL (i) b controls the switching member Sb to open and close
  • the resistance cell RC (i, 1 ) To RC (i, n) the control signal CTL (i) a is connected to control the switching member Sb
  • the control signal CTL (i) b is connected to control the switching member Sa to open and close.
  • the switching members Sa and Sb on the resistance cell matrix LCM side and the switching members S on the resistance cell matrix RCM side are changed.
  • the opening and closing relationship of the switching members S a and S b is reversed between a and S b.
  • each of the resistance cells LC (i, 1) to LC (i, For n) are closed, whereas for each resistance cell RC (i, 1) to RC (i, n) on the same row on the resistance cell matrix R CM side, Means that only the respective switching members Sb are closed.
  • each of the resistance cells LC (i, 1) to LC (i, n) in the same row on the resistance cell matrix LCM side has its own switching. While only the member S b side is closed, for each of the resistance cells RC (i, 1) to RC (i, ⁇ ) in the same row on the resistance cell matrix RCM side, each switching member S a Only the side is closed.
  • the resistance cell matrices LCM and RCM each have a configuration in which “m” resistance cells LC and RC are arranged in the column direction, the control signals CTL (i) a and The number of signals of CTL (i) b is '2m' of CTL (1) a to CTL (m) a and CTL (1) b to CTL (m) b.
  • each of the multiplexers MUX L (j) and MUXR (j) receives control signals CTL (j) p and CTL (j) m from the decoder DEC.
  • Each of the control signals CTL (j) p and CTL (j) m is an ONZO FF signal (conduction Z Signal) controls the connection of the input terminals to the first output terminal, the second output terminal, and the invalid output terminal.
  • the two control signals CTL (j) p and CTL (j) m are connected to the multiplexer MUXL (j) of the resistance cell matrix LCM and the multiplexer MUXR (j) of the resistance cell matrix RCM.
  • the connection of the control signals CTL (j) p and CTL (j) m to the first input terminal and the second input terminal is switched. Further, the connection of the control signals CTL (j) p and CTL (j) m to the multiplexer MUX L (j) of the resistance cell matrix LCM and to the multiplexer MUXR (j) of the resistance cell matrix RCM. They are connected in the reverse order.
  • the control signal CTL (j) p is the corresponding ⁇ 'column as in the column Ml of the multiplexers MUXL (1) -MUXL (n).
  • the second multiplexer MUXL (j) is connected to the first output terminal connected to the positive output Pout while the input terminal of the multiplexer MUXL (j) is connected to the first multiplexer MUXL (j).
  • m is connected to the multiplexer MUXL (j) in the 'th column in the same order as the column order' j 'of the multiplexers MUXL (1) to MUXL (n), and the input terminal of the multiplexer MUXL (j) is The second output terminal connected to the negative output Mout is controlled to be turned off.
  • the control signal CTL (j) Connected to the 'n-j + th multiplexer MUXR (n-j + 1) in column order the input of the multiplexer MUXR (n-j + 1) is connected to the second output connected to the negative output Mout.
  • the control signal CTL (j) m is also controlled by the multiplexer MUXR (1) to MUXR (n) in the column order.
  • control signal CTL (j) p is supplied to one of the multiplexers MUXL (j) of the resistance cell matrix LCM, and the input terminal is connected to the first output terminal connected to the positive output Pout. Is connected, the input end of the multiplexer MUXR (n-j + 1) of the resistance cell matrix RCM, which is symmetrical with respect to the column center line X—X, is connected to the negative output Mout. The second output terminal is conducted. Further, the control signal CTL (j) m is supplied to one of the multiplexers MUXL (j) of the resistance cell matrix LCM, and the input terminal of the multiplexer MUXL (j) is connected to the second output terminal connected to the negative output Mout.
  • the input end of the multiplexer MUXR (n-j + 1) of the resistance cell matrix RCM which is symmetrically positioned with respect to the column center line X—X, is connected to the positive output P 0 ut. Is conducted to the first output terminal.
  • the control signals CT L (j) p and CTL (j ) The number of signals of m is' 2 ⁇ ,.
  • FIG. 4 is a circuit diagram showing details of the resistance cells LC and RC in the present embodiment.
  • Each of the resistance cells LC and RC shown in Fig. 4 has a cell configuration including the common output line described in Fig. 2.
  • One resistance cell L C (i, j) is configured in a three-terminal-pair circuit including an electric connection terminal a i, b i, c i and an electric connection terminal a o, b o, c o as a pair thereof.
  • one terminal pair ci—co is short-circuited, and the remaining two terminal pairs ai—a0 and bi—b0
  • Resistors RL (i, j) a and RL (i, j) b are provided. Note that the resistance RL (i, j) a and the resistance RL (i, j) b have substantially the same resistance value.
  • the ao side is connected to the shorted terminal pair ci-co via the switch SL (i, j) a
  • the connection terminal bi of the terminal pair bi — bo connected by the resistor RL (i, j) b is connected to the shorted terminal pair ci-co via the switch SL (i, j) b It has become.
  • connection terminals ao, bo, and co are respectively connected to the connection terminals ai, bi, and ci of one side of another resistance cell LC (i + 1, j) having the same configuration.
  • a plurality of resistance cells LC (1, j) to LC (m, j) are connected to each of the connection terminals ao, bo, and co with the connection terminals ai, bi, and ci. They are arranged so as to form one resistance cell unit LCU (j).
  • the resistance cell RC (i, j), not shown, has the same configuration as the above-described resistance cell LC (i, j), and a plurality of, ie, 'm' linear arrangements are also provided. They are arranged in a row to form one resistance cell unit RCU (j).
  • the plurality of resistance cell units LCU (j) and RCU (j) configured in this manner are further arranged in parallel, each number of which is 'n', and the above-described resistance cell LC (1, 1) LCLC (m, n) to form a resistance cell matrix LCM and resistance cells RC (1, 1) to RC (m, n).
  • the resistance cell matrix LCM having ' ⁇ ' resistance cell units LCU (1) to LCU (n) also has ' ⁇ ' resistance cell units RCU (1 ) To RCU (n) are arranged in parallel, and a total of '2 ⁇ ' resistance cell units LCU and RCU are arranged in parallel as a whole (see FIG. 2).
  • the resistance cells LC (m, j) and RC (m, j) at the last stage (m stage) of each resistance cell unit LCU (j) and RCU (j) have connection terminals ao and bo.
  • the connection is short-circuited, and the connection end co is not connected to any of the connection ends ao and b0.
  • connection end bi of the resistance cell LC (1, j), RC (1, j) of the first stage of one resistance cell unit LCU (j), RCU (j) is connected to the resistance cell unit arranged adjacently.
  • G are connected to the connection terminals ai on one side of the first stage resistance cells LC (1, j + 1) and RC (1, j + 1) of the LCU (j + 1) and RCU (j + 1).
  • connection end ai of the first-stage resistance cells LC (1, j) and RC (1, j) of the resistance cell units LCU (j) and RCU (j) is connected to the adjacently arranged resistance cell units LCU (j-1), connected to one end bi of the resistance cells LC (1, j-1) and RC (1, j-1) in the first stage of RCU (j-1).
  • the resistance cell units LCU (j) and RCU (j) are each 2 m 'Resistors RL and RR (not shown) are connected in series, while a resistance cell matrix LCM composed of resistance cell units L CU (1) to LCU (n), and resistance cell units RCU (1) to RCU ( In the resistor cell matrix RCM consisting of n), '2mxn' resistors RL and RR (not shown) are connected in series.
  • connection terminal bi of the resistance cell LC (1, n) that forms the end of the series-connected resistance RL in the resistance cell matrix LCM is connected to the resistance cell that forms the beginning of the series-connected resistance RR of the resistance cell matrix RCM. Since it is connected to the connection terminal ai of RC (1, j), '2x2mxn' resistors RL and RR are connected in series in the entire resistor array RARY.
  • connection end ai of the resistance cell LC (1, 1) forming the starting end of the series-connected resistances RL and RR is The connection terminal bi of the resistor cell RC (1, n) connected to the first reference voltage (high voltage) Vd da and terminating the resistors RL and RR connected in series is connected to the second reference voltage (low voltage). Voltage, where the low voltage also includes the ground potential) Connected to V0.
  • the resistor cell matrix LCM and the resistor cell matrix RCM are integrated, and the resistors RL and RR are in a matrix of 'm, row' 2 ⁇ 2 ⁇ '.
  • the one-input three-output multiplexer MUX is associated with each of the plurality of resistance cell units LCU (1) to LCU (n) and RCU (1) to RCU (n).
  • L (1) to MUXL (n) and MUXR (1) to MUXR (n) are provided, and each of the resistance cell units LCU (1) to LCU (n) and RCU (1) to RCU (n)
  • the connection ends ci of the first-stage resistance cells LC (1, l) to LC (l, n) and RC (l, 1) to RC (1, n) are the corresponding multiplexers MUXL (1) to M UXL (n) , MUXR (1) to MUXR (n).
  • any one of the resistance cell units LCU (j) and RCU (j) of '1 to' n ' specify one row of' 1 to
  • the switches SL (i, 1) a to SL (i, n) a and SR (i, 1) b to A switch group consisting of SR (i, n) b or switches SL (i, 1) b to SL (i, n) b and SR (i, n) 1)
  • One of the switch groups consisting of a to SR (i, n) a is closed.
  • the control signal CTL (i) a is selected from the '2 ⁇ , resistances RL provided in series for each of the resistance cell units LCU (1) to LCU (n).
  • the control signal CTL (i) is selected from '2m' resistance RRs provided in series for each of the resistance cell units RCU (1) to RCU (n). Only the switch SR corresponding to the resistor RR at the 'k'th (k is a natural number, k ⁇ 2m) position counted from the low voltage V0 connection side, which is specified by a or CTL (i) b, is closed. , Is connected to the input terminal of the multiplexer MUXR via the common output line. As a result, the voltages output to the input terminals of the multiplexers MUXL (1) to (n) and MUXR (1) to (n) change.
  • the voltage at the input terminal of the multiplexer MUX L (1) is in the voltage range from 'Vdd a—Vr' to 'Vd da—2 mVr, in' V r 'steps. Is obtained.
  • the resistance cell units LCU (1) to LCU (n) and RCU (1) to RCU (n) are electrically connected in series, and the resistances RL and RR are arranged in 'm' rows and '2 ⁇ ' columns, respectively. Since the cell matrices LCM and RCM are configured and the resistance cell matrices LCM and RCM are also connected in series, the resistance array RARY as a whole is 'Vdd a — Vr, ⁇ ' Vdd a-2x2mn V In the voltage range of r ', a voltage in increments of V r is obtained.
  • the symmetrical position is set with the aforementioned column center line X—X as the axis of symmetry. Only the input terminals of the related multiplexers MUXL (j) and MUXR (n-j + 1) can be connected to the positive output Pout and the negative output Mout.
  • the multiplexer MUX L (1) is supplied with the control signal CTL (1) p and the multiplexer MUXL (1) is connected to the positive output P 0 ut, the multiplexer MUXL (1) and the column center line X— With X as the axis of symmetry, the control signal CTL (1) p is also supplied to the multiplexer MUXR (n), which is symmetrically positioned, and the multiplexer MUXR (n) is connected to the negative output Mout.
  • MUX L (2) to MUXL (n) and MUXR (1) to MUXR (n-1) are connected to the invalid output terminal, and are not connected to the positive and negative outputs Pout and Mount.
  • control signal CTL (1) m is supplied to the multiplexer MUXL (1) and the multiplexer MUXL (1) is connected to the negative output Mout
  • the other multiplexers MUXL (2) to MUXL (n) and MUXR (1) to MUXR (n-1) are connected to the invalid output terminal, and are not connected to the positive and negative outputs Pout and Mout.
  • the analog signal DAO expressed by the voltage difference between the positive output P out and the negative output Mout is expressed as the voltage of '-(2x2mn-1) Vr, ⁇ ' + (2x2mn-1) Vr '.
  • the voltage value can be output in increments of '2xVr, within the range.
  • Figure 5 shows the relationship between the digital signal DI input and the analog signal D AO output, and the switches SL and SR connected to the common output line and the positive output P out, to obtain this analog signal DAO output.
  • This is a relationship diagram of the multiplexers MUXL and MUXR connected to the negative output Mout.
  • the control signal CTL (1) a is supplied from the decoder DEC, and the switches SL (1, 1) a to SL (1, n) a is closed and switches SR (1, 1) b to SR (1, n) b is closed.
  • control signal CTL (1) m is also input to the multiplexer MUXR (n) having a symmetrical positional relationship with the multiplexer MUXL (1) with the column center line X—X as the axis of symmetry, and the multiplexer MUXL (1 ) To MUXR (n), only the multiplexer MUXR (n) is connected to the positive output P out, and the other multiplexers MUXR (1) to MUXR (n-1) are not connected to either the positive or negative output.
  • the positive output Pout becomes V0 (for example, 0)
  • the negative output Mout becomes '(2 X 2mn-1) Vr'
  • the control signal CTL (2) a is supplied instead of the control signal CTL (1) a, and the switch SL (2, 1) a ⁇ SL (2, n) a is closed and switches SR (2, 1) b ⁇ SR (2, n) b are closed.
  • the values of the digital signal DI are supplied to the multiplexers MUXL (1) to MUXL (n).
  • a control signal CTL (1) m similar to that for the lower limit is supplied, where only multiplexer MUXL (1) is connected to the negative output, and the other multiplexers MUXL (2) to MUXL (n) are either positive or negative. It is not connected to the output.
  • the multiplexers MUXR (1) to MUXR (n) are connected only to the multiplexer MUXR (n) to the positive output port by supplying this control signal CTL (1) m, and the other multiplexers MUXR (1) to MUXR (n-1) are not connected to either positive or negative output.
  • the positive output Pout becomes 'Vr
  • the negative output Mout becomes' (2X 2mn- 1—1) Vr
  • the negative output Mo ut (2 X 2mn- 1-1) V r
  • the decoder DEC outputs the control signal CTL with the increase with respect to the lower limit of' m- ⁇ .
  • the control signal C TL (i) b is supplied instead of the control signal C TL (i) a that was supplied in the state before the power supply exceeds the threshold.
  • the decoder DEC when the increment from the lower limit of the digital signal DI changes from a value corresponding to 'm-' to 'm', the decoder DEC outputs the control signal CTL (m) b instead of the control signal CTL (m) a.
  • the switches SL (m, 1) a to SL (m, n) a and the switches SR (m, 1) b to SR (m, n) b are closed, and the switch SL (m , 1) b to SL (m, n) b and switches SR (m, 1) a to SR (m, n) a are switched to the closed state.
  • the switching between the control signal CTL (i) a and the control signal CTL (i) b by the decoder DEC is performed by the above-mentioned '2m' resistance members Ra and R b having substantially the same resistance value. Due to the configuration of the resistance cell units LCU and RCU, which are connected in series in the column direction by m 'units in the forward direction and the return direction, the increment of the digital signal DI over the lower limit exceeds' (multiple of m) — ⁇ Done in
  • the increment of the digital signal DI with respect to the lower limit is smaller than 'kXm' and equal to or more than '(k-1) m', and when 'k' is an odd number Is the control signal CTL (i) a output from the decoder DEC, and 'i' is'
  • the control signal CTL (1) b is supplied from the decoder DEC, and the switches SL (1, 1) b to SL (1, n) b is closed and switches SR (1, 1) a to SR (1, n) a are closed.
  • the positive output P out becomes' (2m-1) Vr '
  • the negative output Mout becomes' (2X2mn-1-(2m-1)) Vr
  • the decoder DEC issues a control signal CTL (1) instead of the control signal CTL (1) b.
  • a is supplied, switches SL (1, 1) a to SL (1, n) a are closed, and switches SR (1, 1) b to SR (1, n) are closed .
  • the multiplexers MUX L (1) to MUXL (n) have the multiplexer MUX L instead of the multiplexer MUXL (1).
  • (2) is connected to the negative output Mout, and the other multiplexers MUXL (1), MUXL (3) to MUXL (n) are connected to the control signal CTL (2) m so that they are not connected to either the positive or negative output. Supplied.
  • control signal CTL (2) m is also supplied to the multiplexers MUXR (1) to MUXR (n), only the multiplexer MUXR (n-1) is connected to the positive output P out, and The multiplexers MUXR (1) to MUXR (n ⁇ 2) and MUXR (n) are not connected to either the positive or negative output.
  • the positive output Pout becomes '(2 m) XVr
  • the negative output Mout becomes' (2X2mn-l-2m) XVr
  • the analog signal D AO is output from the resistor array RARY.
  • the control signal CTL (1) b is supplied, and the switch SL (1, 1) b to SL (1, n) b are closed, and switches SR (1, 1) a to SR (1, n) a are closed.
  • the value of the increase of the digital signal DI from the lower limit value is' 2 mn—1, (n-1), but smaller than '2mn', the multiplexer MUX L (1) -MUXL (n) has only the multiplexer MUXL (n) connected to the negative output Mout, and the other multiplexers
  • the control signals CTL (n) m are supplied so that MUX L (1) to MUXL (n-1) are not connected to either the positive or negative output.
  • control signal CTL (n) m is also supplied to the multiplexers MUXR (1) to MUXR (n)
  • only the multiplexer MUXR (1) is connected to the positive output P out, and the other multiplexers MUXR (2) ⁇ MUXR (n) is not connected to either positive or negative output.
  • the positive output Pout becomes '(2mn-1) XVr'
  • the negative output Mout becomes '(2X2mn-1-(2mn-1)) XVr'
  • the decoder DEC supplies the control signal CTL (1) b, and the switches SL (1, 1) b to SL (1 , N) b are closed, and switches SR (1, 1) a to SR (1, n) a are closed.
  • the multiplexers MUXL (1) to MUXL (n) output only the multiplexer M UXL (n) to the negative output Mout. Instead, it is connected to the positive output Pout, and the control signal CTL (n) p is supplied so that the other multiplexers MUXL (1) to MUXL (n-1) are not connected to either the positive or negative output.
  • the multiplexers MUXR (1) to MUXR (n) are also supplied with the control signal CTL (n) p, and only the multiplexer MUXR (1) receives the negative output Mo instead of the positive output P 0 ut. ut, the other multiplexer MUXR (2) " ⁇ MU XR (n) will not be connected to either the positive or negative output.
  • the positive output Pout becomes '2mnXVr,' and the negative output Mout becomes '(2X2mn-1-2mn) XVr'.
  • the digital signal DI is connected to the negative output Mout based on the control signal CTL (j) m from the decoder DEC.
  • Multiplexers MUXL (1) to MUXL (n) which were controlled to be connected / disconnected to the second output terminal connected to the positive output Pout based on the control signal CTL (j) p from the decoder DEC Communication / shutoff control is performed for the first output terminal that is set.
  • the increment of the lower limit of the digital signal DI exceeds' 2 mn- ⁇ , until then, it is connected to the positive output P out based on the control signal CTL (j) m from the decoder DEC.
  • the multiplexers MUXR (1) to MUXR (n), which were controlled to be disconnected from the first output terminal, are connected to the negative output Mout based on the control signal CTL (j) p from the decoder DEC. Communication / shutoff control is performed for the second output terminal.
  • the control signal CTL (j) m is output from the decoder DEC, and the' j 'is represented by' [(digital signal DI 2111] + ⁇ (where [] represents a Gaussian symbol). If the increase is larger than '2 ⁇ -1', the control signal CTL (j ) p is output, and its 'j,' becomes ' ⁇ -([(increase from the lower limit of digital signal DI) 2m]-n)'.
  • the resistance cell matrix LCM The multiplexer MUXL (j) whose input terminal is connected to the negative output Mot is shifted to 'j', the column order of '1 to' n ', and corresponds to the resistance cell matrix RCM.
  • the resistance cell matrix LCM will be used every time the digital signal DI further increases by the increment of '2m' with respect to the lower limit.
  • the multiplexer MUXL (j) whose input terminal is connected to the positive output P 0 ut is shifted in the reverse order of the column order 'j' of ' ⁇ to' ⁇ ',
  • the multiplexer MUXR (j) whose input end is connected to the negative output Mut corresponding to the anti-cell matrix RCM is shifted in the column order 'j' of ' ⁇ to' ⁇ , '.
  • the decoder DEC supplies the control signal CTL (2) b and the switch SL (2, 1) b ⁇ SL (2, n) b is closed and switches SR (2,1) a ⁇ SR (2, n) a are closed.
  • the multiplexers MUXL (1) to MUXL (n) include the multiplexer MUXL (n ) To the positive output P 0 ut, and the control signal CTL (n) p is supplied so that the other multiplexers M UXL (1) to MUXL (n-1) are not connected to either the positive or negative output.
  • the multiplexers MUXR (1) to MUXR (n) also connect only the multiplexer MUXR (1) to the negative output Mout by supplying this control signal C TL (n) p, and the other multiplexers MUXR (2) ⁇ MUXR (n) will not be connected to either the positive or negative output.
  • the value of the increase in the digital signal DI with respect to the lower limit exceeds '2mn-—, and further exceeds' 2mn + 2m (n-1)-1, so that the multiplexers MUXL (1) to MUXL ( In (n), only multiplexer MUXL (1) is connected to positive output P out, and other multiplexers MUXL (2) to MUXL (n) are connected to both positive and negative outputs.
  • the control signal CTL (1) p is supplied to prevent this.
  • the multiplexers MUXR (1) to MUXR (n) also connect only the multiplexer MUXR (n) to the negative output M out, and the other multiplexers MUXR (1) to MUXR (n— 1) is not connected to either the positive or negative output.
  • FIG. 6 is a block diagram in which the resistor array RARY of the above embodiment is applied to a DA converter for processing a 5-bit digital signal DI.
  • Each resistance cell unit LCU, RCU has '8' resistance switch sets RS each consisting of a resistance member Ra or Rb and a corresponding switch member Sa or Sb, that is, 1 byte. Configuration.
  • the numbers 0 to 31 assigned to each resistor ZSW (switch) set RS correspond to the corresponding resistors / SW set RS by closing the switch (not shown in FIG. 6).
  • the first reference voltage (high voltage) supplied from the resistance cell units LCU and RCU including the resistance / SW set RS to the input terminal of the corresponding multiplexer MUX is corresponding to the level of the voltage drop with respect to Vdda. I have.
  • the DA converter uses control signals CTL (1) p, CTL (1) m, C TL (2) p, and CTL ( 2) Generate Hi, multiplexer MUX of resistor array RAR Y L (1), MUXL (2), MUXR (1), and MUXR (2) are used to select the connection switching of the input terminals to the first to third output terminals.
  • the decoder DEC generates the control signals CTL (1) a to CTL (4) a and CTL (1) b to CTL (4) b using the lower 3 bits of binary data of the digital signal DI, and outputs the resistance in the same row.
  • the resistor / SW set RS at which the switch is closed is selected.
  • FIG. 7 is a relationship diagram between the digital signal DI and the analog signal DA0 output from the resistor array RARY in the DA converter of the present embodiment.
  • control signals CTL (1) m, CTL (2) m, CTL (2) p, CTL (1) p, and the control signal CTL (1) b as shown in FIG. ⁇ CTL (4) b, CTL (1) a ⁇ CTL (4) a are generated.
  • the digital signal DI when the lower 3 bits of the digital signal DI are directly associated with the control signals CTL (1) p, CTL (2) p, CTL (2) m, and CTL (1) m, the digital signal DI
  • the order of the resistor switch set RS selected to be closed in the resistor cell units LCU and RCU when the value of '0' to '15' corresponds to that of '16' to '31' Will change.
  • the numbers of '0' to '15' are increased in accordance with the increase of the value of the digital signal DI.
  • the value of the digital signal DI exceeds '15'
  • the switch of the resistor ZSW set RS is selected and closed
  • the value of '15' is set according to the subsequent increase of the value of the digital signal DI.
  • the switches of the resistor ZSW set RS are selected and closed in the descending order of the numbers ⁇ 0.
  • the resistance / matrix LCM and the resistance / SW set RS on the RCM side are connected to the positive output P out by the multiplexers MUXL and MUXR from the column center line X—X of the resistance array RARY.
  • the selection order of the columns of the resistance switch SW set RS in the resistance cell units LCU and RCU is switched between the case of connection to the negative output Mout and that of connection.
  • the selection of the rows of '0, to' 3, 'in the resistance / SW set RS and the selection of the columns of the resistance / SW set RS,' 4 'to' 7 ' The cell unit LCU (1) is connected to the positive output P out and the negative output Mo u It is interchanged when connected to t.
  • the digital signal DI becomes' 0 , ⁇ '15', and '16, ⁇ '31', the selected column changes.
  • the lower three bits of the digital signal DI are directly controlled by the decoder DEC.
  • the decoder DEC instead of associating signals CTL (1) a to CTL (4) a and CTL (1) b to CTL (4) b, invert the lower three bits of the digital signal DI input to the decoder DEC before controlling Signals CTL (1) a to CTL (4) a and CTL (1) b to CTL (4) b are associated with each other.
  • Whether the digital signal DI exceeds or does not exceed the intermediate value '15' (corresponding to the column center line X—X) (reversal condition) is determined by a change in the value of the most significant bit of the digital signal DI.
  • a predetermined lower bit sequence of the digital signal DI used for the control signals CTL (i) a and CTL (i) b is represented by the most significant bit.
  • the exclusive OR (XOR) to generate the control signals CTL (i) a and CTL (i) b.
  • the DA converter includes a plurality of series-connected resistance members RL and RR, and switching members SL and SR provided to correspond to the resistances RL and RR for extracting output.
  • the resistance cell units LCU and RCU each have a resistance array arranged on both sides of the center line X--X, and if there are a plurality of resistance cell units LCU and RCU, respectively, a plurality of unit LCUs (or RCU), the switching members in the corresponding positional relationship in the unit are activated and selected by the common control signal, and the center between the center line X--X is located between the resistance cell unit LCU and the RCU.
  • Line X—Switching members that are symmetrically positioned with X as the axis of symmetry are selected to be activated by a common control signal, so that control signals can be shared and the layout area is reduced. You.
  • the resistance cell units LCU and RCU each use a common output line, the parasitic capacitance on the output line is reduced, and the current supplied to the resistance array RARY is suppressed. I can do it.
  • multiplexers MUX L and MUXR for connecting and controlling the outputs of the resistance cell units LCU and RCU to positive and negative outputs are provided for each resistance cell unit LCU and RCU, and are symmetrical with the center line X—X as the axis of symmetry. Since a pair of multiplexers MUX L and MUXR in a positional relationship are connected to the positive / negative output by a common control signal, control signals can be shared, the layout area can be reduced, and the difference can be reduced. The dynamic output ratio accuracy can be improved.
  • FIG. 8 shows another embodiment having a main resistor and a sub resistor.
  • each resistor used in the resistor array can be set so large that the parasitic resistance can be ignored, so that the effect of the parasitic resistance can be reduced. This improves the conversion accuracy.
  • the DA converter according to the present invention has an excellent effect that the control signal can be shared, the layout area is reduced, and the circuit scale for the conversion range of the digital signal is reduced.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention concerne un convertisseur numérique-analogique, NA, pourvu d'un ensemble comprenant 'n' unités reliées en série à une tension de référence, chacune constituée de '2m' éléments de résistance reliés en série et '2m' éléments commutateurs destinés à relier les éléments de résistance à une extrémité de sortie commune. L'extrémité de sortie commune d'une unité choisie de l'ensemble est reliée à une ligne de sortie par le biais d'un élément de commutation. Disposés en positions de réseau correspondant à chacune des unités, tous les 'n' éléments commutateurs sont fermés simultanément par un signal de commande commun. En conséquence, les lignes des signaux de commande sont peu nombreuses, et l'échelle de circuit est petite.
PCT/JP2001/002680 2001-03-29 2001-03-29 Convertisseur numerique-analogique WO2002080371A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012195825A (ja) * 2011-03-17 2012-10-11 Ricoh Co Ltd 抵抗ストリング型ｄ／ａコンバータ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059978A (en) * 1990-12-20 1991-10-22 Vlsi Technology, Inc. Resistor-string digital to analog converters with auxiliary coarse ladders
JPH05145388A (ja) * 1991-11-20 1993-06-11 Toshiba Corp トランスフアーゲートスイツチ回路
JPH08213911A (ja) * 1994-10-21 1996-08-20 At & T Corp 電流源により駆動された変換器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059978A (en) * 1990-12-20 1991-10-22 Vlsi Technology, Inc. Resistor-string digital to analog converters with auxiliary coarse ladders
JPH05145388A (ja) * 1991-11-20 1993-06-11 Toshiba Corp トランスフアーゲートスイツチ回路
JPH08213911A (ja) * 1994-10-21 1996-08-20 At & T Corp 電流源により駆動された変換器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012195825A (ja) * 2011-03-17 2012-10-11 Ricoh Co Ltd 抵抗ストリング型ｄ／ａコンバータ

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