Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
  • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the present invention relates generally to computer processor power management, and more specifically to an improved method for determining optimum performance level transition points.
• the PMS might be an embedded part of the OS.
• the user might input a preference toward battery life or toward system performance.
• the user might indicate energy conservation for DC operation and system performance optimization for AC operation.
• the reduction in power consumption had a linear relationship to the reduction in system performance. For example, a system running at 500 Mhz and using 10 watts could be throttled down to 250Mhz and use 5 watts.
• a PMS exhibiting this linear relationship provides little benefit in the way of prolonged battery life. That is, a system running at half the speed for twice as long will accomplish the same amount for the expended energy. The system will run cooler, but no more work is accomplished.
• the user could also provide input to the system and, if desired, chose not to switch to low performance mode.
• the PMS software may be incorporated within the OS and indicates to an application and driver that the power source has changed, the driver then communicates with the firmware that switches modes. [0005] Although such a PMS prolongs battery life, it does not address the issue of reduced performance. While on battery the system runs at a lower frequency and the user does not get the full benefit of system performance. If the user places the system into a high performance mode the battery life is diminished.
• Figure 1 is a diagram illustrating a computing system for implementing the present invention
• Figure 2 is a block diagram of a power control circuit for implementing the present invention.
• Figure 3 depicts typical processor utilization graphs.
• An embodiment of the present invention provides a method for transition of processor performance levels in a demand-based system.
• a performance level is a specified operating frequency and its associated voltage. Automatic transition may use less transition overhead, thereby extending battery life.
• An embodiment of the invention provides for the automatic adjustment of processor frequency while preserving system responsiveness.
• the processor may be transitioned to multiple performance levels.
• Figure. 1 is a diagram illustrating an exemplary computer system 100 for implementing the present invention. The sampling of processor utilization, the detection of a change in processor utilization, and the transition of the processor to a different performance level, described herein, may be implemented and utilized within computing system 100.
• Computing system 100 may represent a general-purpose computer, portable computer, or other like device. The components of computing system 100 are exemplary in which one or more components may be omitted or added.
• computing system 100 includes a central processing unit 102 coupled to a display circuit 105, main memory 104, static memory 106, and mass storage device 107 via bus 101.
• Computing system 100 may also be coupled to a display 121, keypad input 122, cursor control 123, hard copy device 124, and input/output (I/O) devices 125 via bus 101.
• Computing system 100 may contain frequency and voltage regulation circuitry as described below.
• Bus 101 is a standard system bus for communicating information and signals.
• Processor 102 is a processing unit for computing system 100. Processor 102 may be used to process information for computing system 100.
• Processor 102 includes a control unit 131, an arithmetic logic unit (ALU) 132, and several registers 133, which are used to process information.
• ALU arithmetic logic unit
• Main memory 104 may be, e.g., a random access memory (RAM) or some other dynamic storage device, for storing information or instructions (program code), which are used by processor 102. Main memory 104 may also store temporary variables or other intermediate information during execution of instructions by processor 102.
• Static memory 106 may be, e.g., a read only memory (ROM) and/or other static storage devices, for storing information or instructions, which may also be used by processor 102.
• Mass storage device 107 may be, e.g., a hard or floppy disk drive or optical disk drive, for storing information or instructions for computing system 100.
• Display 121 may be, e.g., a cathode ray tube (CRT) or liquid crystal display (LCD). Display device 121 displays information or graphics to a user.
• Computing system 100 may interface with display 121 via display circuit 105.
• Keypad input 122 is a alphanumeric input device for communicating information and command selections to computing system 100.
• Cursor control 123 may be, e.g., a mouse, a trackball, or cursor direction keys, for controlling movement of an object on display 121.
• Hard copy device 124 may be, e.g., a laser printer, for printing information on paper, film, or some other like medium.
• a number of input/output devices 125 may be coupled to computing system 100.
• processor 102 may also contain power management software 134 to allow user control of operating voltage and operating frequency.
• the power management software 134 may configure an I/O controller 150 to facilitate voltage and frequency scaling upon the occurrence of specified conditions.
• I/O controller 150 programs a register 136 within a clock generation circuit 135. The programmed information indicates how the operating frequency of the clocking signal is to be altered.
• the clock generation circuit 135 monitors the register 136 and modifies the frequency of the clocking signals accordingly. After determining that the operating frequency has been reduced the I/O controller 150 generates a voltage modification control signal to a power supply circuit, not shown. The power supply circuit then reduces the voltage accordingly.
• the processor performance level transition policy algorithm may be implemented by hardware and/or software contained within computing system 100.
• processor 102 may execute code or instructions stored in a machine- readable medium, e.g., main memory 104, to decide when to transition the processor performance level on a processor that supports multiple performance levels.
• the machine-readable medium may include a mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine such as computer.
• a machine-readable medium may include a read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices.
• the code or instructions may be represented by carrier wave signals, infrared signals, digital signals, and by other like signals.
• PMS may have several inputs into the software.
• the software may use these inputs to determine a performance level for the processor.
• the inputs include "power source”, high performance level for AC and low performance level for DC; "thermal”, an overriding environmental concern which will transition the processor to a lower (i.e., cooler) performance level if the processor overheats; and "user preference", whereby a user may chose between conserving energy and increased performance.
• a demand-based PMS includes the input of "processor utilization” to allow for a transition to a higher performance level if the user has need of a higher level of performance.
• An embodiment of the present invention employs a fast up/slow down (FUSD) transition policy to monitor user demand upon the processor (i.e. processor utilization).
• FUSD fast up/slow down
• An alternative embodiment may employ a slow up/fast down (SUFD) transition policy.
• the monitoring may be done by periodically reading the processor's Time Stamp Counter (TSC) and a high-resolution timer or utilizing existing native OS mechanisms.
• TSC Time Stamp Counter
• the TSC provides information about processor activity when the processor is not in a sleep state.
• the calculation of processor activity and frequency provides the utilization over a given period.
• Exemplary graphs of processor utilization for some typical workloads are shown in Figure 2.
• Figure 2a shows the processor utilization graph of, for example, a rendering. As shown the processor utilization rises quickly to near 100% and remains at a high level until the processing is complete.
• Figure 2b shows the processor graph for a digital video disc (DVD).
• the processor utilization rises to a high level for extended periods and occasionally drops to significantly lower levels.
• Figure 2c shows the processor graph for an idle system. As shown the processor utilization is at low level with the exception of spikes due to periodic OS housekeeping. An embodiment of the present invention will quickly detect a high processor utilization level and automatically switch the system to a high frequency performance level. When processor utilization drops off, the system is automatically switched to a low performance level.
• the ability to quickly transition between performance levels is not critical for a workload having a processor utilization graph as shown in Figures 2a and 2c. For workload such as that shown in Figure 2b, however, quickly detecting changes in processor utilization and transitioning to an optimum performance level, may significantly improve energy efficiency.
• processor utilization is measured every T seconds.
• the processor-utilization monitoring period, T should be small enough so that increased processor utilization is detected quickly, this maintains the responsiveness of the system. T should not be so small, however, as to overly tax the processor resources.
• processor utilization is detected above a given threshold the system is automatically switched to a higher performance level.
• processor utilization is detected below a given threshold the system is automatically switched to a lower performance level. Frequent switching between higher and lower performance levels taxes the processor, therefore the FUSD transition policy allows for less frequent switching from a high performance level to a lower one so that quick reversals in processor utilization will not result in frequent switching.
• the processor utilization reaches a switch-up threshold of, for example, 95% at time Ti.
• the system automatically transitions to a higher performance level.
• the processor utilization drops below a switch-down threshold, for example 75%, but the system does not transition to a lower performance level. Instead, current performance level is maintained until processor utilization is monitored at time T 3 .
• the processor utilization is again above the switch-up threshold so the higher performance level is maintained.
• the system is then transitioned to a lower performance level. The system remains at this lower performance level until the processor utilization once again rises above the switch-up threshold (i.e., until time T ).
• FIG. 3 is a process flow diagram in accordance with one embodiment of the present invention.
• the process 300 shown in Figure 3 begins at operation 305 in which the processor utilization is calculated for the current performance level (i.e., at the current frequency). This calculation may be completed every T seconds.
• T is selected to be small enough to quickly detect an increase in processor utilization while not being so small as to unduly tax processor resources. Empirically, for one embodiment, a value of 150 milliseconds (ms) for T has been found to be adequate for typical systems with typical processor utilization graphs.
• the system determines if processor utilization is above a specified switch-up threshold. For one embodiment of the present invention the switch-up threshold is specified as 95% of the current performance level.
• the switch-up period may be equal to one or more processor- utilization monitoring periods T.
• the processor monitoring period is equal to 150 ms and the switch-up period is equal to 300 ms.
• processor utilization has not been above the switch-up threshold longer than the switch-up period, the system waits until the next processor-utilization monitoring period, T, expires at operation 325 and returns to operation 305. If processor utilization has been above the switch-up threshold longer than the switch-up period the system automatically transitions to the next higher performance level at operation 320 and then proceeds to operation 325 as described above.
• the system determines if processor utilization is below a specified switch-down threshold at operation 330.
• the switch-down threshold is specified as 95% of the next lower performance level. If processor utilization is below the specified switch-down threshold, the system determines if processor utilization has been below the switch-down threshold longer than the switch-down period at operation 335.
• the switch-down period may be different than the switch-up period. For one embodiment the switch-up period is equal to 300 ms and the switch-down period is equal to 1000 ms. If processor utilization has not been below the switch-down threshold longer than the switch-down period, the system waits until the next processor-utilization monitoring period, T, expires at operation
• processor utilization has been below the switch-down threshold longer than the switch-down period the system automatically transitions to the next lower performance level at operation 340 and then proceeds to operation 325 as described above.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Power Sources (AREA)
• Debugging And Monitoring (AREA)

Priority Applications (5)

Applications Claiming Priority (2)

Publications (2)

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Family Applications (1)

Country Status (9)

Cited By (13)

Families Citing this family (54)

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• 2001
  • 2001-03-19 US US09/812,411 patent/US7017060B2/en not_active Expired - Lifetime
• 2002
  • 2002-01-24 KR KR1020037012174A patent/KR100740289B1/ko not_active Expired - Lifetime
  • 2002-01-24 DE DE10296549T patent/DE10296549T5/de not_active Ceased
  • 2002-01-24 WO PCT/US2002/002028 patent/WO2002074046A2/en not_active Ceased
  • 2002-01-24 GB GB0324178A patent/GB2391094B/en not_active Expired - Fee Related
  • 2002-01-24 JP JP2002572773A patent/JP4191488B2/ja not_active Expired - Lifetime
  • 2002-01-24 CN CNB028068165A patent/CN1292327C/zh not_active Expired - Fee Related
  • 2002-01-24 AU AU2002235460A patent/AU2002235460A1/en not_active Abandoned
  • 2002-03-15 TW TW091104936A patent/TWI224254B/zh not_active IP Right Cessation

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