WO2002064495A3 - Enhanced sacrificial layer etching technique for microstructure release - Google Patents

Enhanced sacrificial layer etching technique for microstructure release Download PDF

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Publication number
WO2002064495A3
WO2002064495A3 PCT/IB2002/000395 IB0200395W WO02064495A3 WO 2002064495 A3 WO2002064495 A3 WO 2002064495A3 IB 0200395 W IB0200395 W IB 0200395W WO 02064495 A3 WO02064495 A3 WO 02064495A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
enhanced
sacrificial layer
etching technique
layer etching
Prior art date
Application number
PCT/IB2002/000395
Other languages
French (fr)
Other versions
WO2002064495A2 (en
Inventor
Michel Despont
Ute Drechsler
Gregoire Genolet
Peter Vettiger
Original Assignee
Ibm
Michel Despont
Ute Drechsler
Gregoire Genolet
Peter Vettiger
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Michel Despont, Ute Drechsler, Gregoire Genolet, Peter Vettiger filed Critical Ibm
Priority to KR10-2003-7009865A priority Critical patent/KR20030086989A/en
Publication of WO2002064495A2 publication Critical patent/WO2002064495A2/en
Publication of WO2002064495A3 publication Critical patent/WO2002064495A3/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
    • B81C1/00468—Releasing structures
    • B81C1/00476—Releasing structures removing a sacrificial layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0102—Surface micromachining
    • B81C2201/0105—Sacrificial layer
    • B81C2201/0109—Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)
  • Weting (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

A method for at least partially releasing microstructures from a substrate is provided. The method comprises the steps of: a) providing a substrate (2); b) depositing onto said substrate (2) a first layer (4) and a second layer (6), the first layer (4) and the second layer (6) each comprising an electrically conducting material and each having a different oxido-reduction potential; c) electrically connecting the first layer (4) and the second layer (6); d) forming a microstructure (8) on the first (4) and second (6) layers deposited in step b) to produce an intermediate structure (10); and e) electrochemically etching said second layer (6) by immersing the intermediate structure (10) formed in step d) in an electrolyte (12).
PCT/IB2002/000395 2001-02-12 2002-02-08 Enhanced sacrificial layer etching technique for microstructure release WO2002064495A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-2003-7009865A KR20030086989A (en) 2001-02-12 2002-02-08 Enhanced sacrificial layer etching technique for microstructure release

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01810141 2001-02-12
EP01810141.0 2001-02-12

Publications (2)

Publication Number Publication Date
WO2002064495A2 WO2002064495A2 (en) 2002-08-22
WO2002064495A3 true WO2002064495A3 (en) 2003-06-05

Family

ID=8183726

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/000395 WO2002064495A2 (en) 2001-02-12 2002-02-08 Enhanced sacrificial layer etching technique for microstructure release

Country Status (3)

Country Link
KR (1) KR20030086989A (en)
TW (1) TW535232B (en)
WO (1) WO2002064495A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100586675B1 (en) * 2004-09-22 2006-06-12 주식회사 파이컴 Manufacture method of vertical-type electric contactor and vertical-type electric contactor thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262000A (en) * 1989-09-26 1993-11-16 British Telecommunications Public Limited Company Method for making micromechanical switch
US5374792A (en) * 1993-01-04 1994-12-20 General Electric Company Micromechanical moving structures including multiple contact switching system
US5652559A (en) * 1993-12-20 1997-07-29 General Electric Company Method of micromachining electromagnetically actuated current switches with polyimide reinforcement seals, and switches produced thereby
US6117694A (en) * 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262000A (en) * 1989-09-26 1993-11-16 British Telecommunications Public Limited Company Method for making micromechanical switch
US5374792A (en) * 1993-01-04 1994-12-20 General Electric Company Micromechanical moving structures including multiple contact switching system
US5652559A (en) * 1993-12-20 1997-07-29 General Electric Company Method of micromachining electromagnetically actuated current switches with polyimide reinforcement seals, and switches produced thereby
US6117694A (en) * 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same

Also Published As

Publication number Publication date
WO2002064495A2 (en) 2002-08-22
TW535232B (en) 2003-06-01
KR20030086989A (en) 2003-11-12

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