KR20030086989A - Enhanced sacrificial layer etching technique for microstructure release - Google Patents

Abstract

A method is provided for at least partially leaving a microstructure from a substrate. The method comprises the steps of (a) providing a substrate (2), and (b) a first layer (4) comprising a first electrically conductive material in the substrate (2), each having a different oxidative-reduction potential; Depositing the second layer 6, (c) electrically connecting the first layer 4 and the second layer 6, and (d) the first layer 4 deposited in step (b). ) And forming a microstructure on the second layer 6 to produce an intermediate structure, and (e) dipping the intermediate structure 10 formed in step (d) into the electrolyte 12 to form a second layer ( Electrochemically etching 6).

Description

Improved Sacrificial Layer Etching Technique for Leaving Microstructures {ENHANCED SACRIFICIAL LAYER ETCHING TECHNIQUE FOR MICROSTRUCTURE RELEASE}

Sacrificial layer technology is of considerable importance in microengineering. The entire structure or part of the device that needs to be free-standing by sacrificial layer technology may be displaced or supported.

The sacrificial material is used as a "form" or "spacer" to produce the desired form, which is later removed. In a sense, when a photoresist is used to define a pattern, the photoresist is almost a sacrificial layer because it is almost always removed. However, in this context, sacrificial process refers to a process used to make independent or flotation structures.

Standard escape techniques use chemical means, such as by plasma or wet etching, to etch away layers. This technique is an isotropic etch so that the lateral under etching of the sacrificial layer is very dependent on its thickness. Since these sacrificial layers are usually in the range of micrometers, it is very difficult and sometimes impossible to deviate from the large structure.

U. S. Patent No. 5,286, 335 discloses a process for providing flotation of thin film semiconductors with thicknesses typically between 1 and 20 micrometers. An epitaxial layer is deposited on a sacrificial layer (made of aluminum arsenide (AlAs)) located on a growth substrate. After coating the epitaxial layer with a transparent carrier layer, the sacrificial layer is etched away to remove the combination of the transparent carrier layer and the epitaxial layer from the growth substrate. Etching is done using standard HF: H ₂ O (1:10) etching solution.

US Pat. No. 5,465,009 discloses a similar process in which flotation is facilitated by consistently patterning the carrier layer by perforation over an array of devices. During etching of the sacrificial layer, since the maximum distance at which the sacrificial layer etching should proceed laterally is less than the distance between the devices, the time to leave the device from the growth substrate is shorter, more constant, and the size of the device array It becomes irrelevant. The process described above can be applied to the processing of macroscopic pieces of semiconductors with thicknesses ranging from sub-microns to tens of microns, perhaps up to 50 microns. The diameter can range from tens of microns to hundreds of microns, and may be close to or exceed 1 mm.

However, in most cases the etching time is still very long because of the large amount of side under etching required compared to the thickness of the sacrificial layer, and there is also a risk of corroding the detached microstructure. This is especially true when it is not possible to have perforations in the device layer. In addition, under etching may be impossible because it is difficult to supply a fresh etching solution to the etching interface.

To dislodge the device entirely, one may use that loss of adhesion at the interface between the device and the substrate while pulling off the device. However, it is difficult to control the special adhesion level at the interface because the adhesion must on the one hand be good enough to process the structure prior to flotation and on the other hand weak enough to break off the structure. In addition, specific adhesion control is extremely sensitive to process parameters.

The present invention generally relates to the formation of microstructures. In particular, the present invention relates to the release or lift-off of microstructures. More specifically, the present invention relates to an exit technique based on sacrificial layer technology.

1A-1C illustrate process steps for completely leaving a microstructure from a substrate or making a portion of the microstructure independent in accordance with the method of the present invention.

2A-2C are diagrams showing process steps such as FIGS. 1A-1C for non-flat substrates.

3A-3B illustrate a process step of etching a very thin prestructured sacrificial material in accordance with the method according to the present invention.

4 illustrates the placement of a structure in a suitable electrolyte in accordance with the method of the present invention.

5 shows the complete flotation of a huge photo plastic tip array in accordance with the process of the present invention.

Summary of the Invention

It is therefore an object of the present invention to provide a simple method of leaving microstructures from a substrate which avoids the disadvantages in known processes.

Another object of the present invention is to provide a method of improving the under etching of a microstructure by increasing the etching rate of the sacrificial layer.

It is yet another object of the present invention to provide a method of electroetching a sacrificial layer without the need for an external power source.

These and other objects and advantages are achieved by the method disclosed in claim 1.

Preferred embodiments of the invention are described in the dependent claims.

Preferred embodiments of the invention will be described in more detail hereinafter only by way of example in conjunction with the drawings.

The present invention seeks to facilitate the departure of the microstructure using the improved etch rate of the sacrificial layer through electrical etching without the need for an external power source. The microstructures may be comprised of microelectronics and / or micromechanical devices and the like. In addition, the term "microstructure" is not limited to structures in the micrometer range, and will generally refer to very small structures, such as structures in the nanometer range (nano structures) and the like. However, hereinafter, the term "micro structure" will be used as an aggregate of all these kinds of structures.

Referring together to FIGS. 1 and 2, improved etching may be used to isolate a portion of the microstructure from the substrate or completely leave the microstructure. Referring to FIG. 3, by etching a very thin prestructured sacrificial material, improved sacrificial layer etching may also be used to define very thin cavities or channels under the microstructure.

In a preferred embodiment of the present invention, an internal cell or galvanic which imparts a sufficiently high electrochemical potential to significantly improve the chemical etching of the sacrificial layer by a film combination of electrically conductive materials at the interface between the substrate and the device on the substrate. The battery is generated. This allows for a faster and more controlled underetch process even if the area to be escaped is very large in the centimeter range.

Since the adhesion between the substrate, the sacrificial layer and the microstructure to be released is strongly maintained, preferred embodiments of the present invention allow for a more robust treatment even if a relatively high temperature step or mechanical pressure is applied.

In order to take advantage of the improved etch rate of the sacrificial layer by electrical etching, it is preferred in the preferred embodiment of the present invention to combine the electrically conductive layers with two different oxido-reduction potentials forming two electrodes. Used. Electrodes with higher oxy-reduction potentials form cathodes, and electrodes with lower oxy-reduction potentials form anodes.

The electrode is formed from an electrically conductive material such as a conductor or a doped semiconductor. However, in a particularly preferred embodiment of the invention, the layers are formed of metal. Preferably, the anode comprises a noble metal (Au, Pd, Pt, Ag, Cu, etc.) and the cathode comprises one metal or doped semiconductor selected from the group comprising Al, Zn, Cr, Fe, Co, and the like. .

Cathode / anode oxido-reduction potential differences should be as large as possible to achieve maximum electrical etch efficiency.

The electrically coupled layers are immersed in a suitable electrolyte, i.e. a solution or vapor environment, to form a galvanic cell and generate a potential high enough to enhance or etch the cathode. This is shown in FIG. In a particularly preferred embodiment of the invention, the electrolyte used is an acidic solution known to etch the negative electrode material.

Depending on the electrolyte and the material chemistry used, the electrode potential difference can change, increasing the etch rate of the sacrificial layer or generating a reaction that does not normally occur. When semiconductors are used as cathodes (eg, Si, SiGe or GaAs), electrochemical etching can be improved due to the light generation of electron-hole pairs in the semiconductor.

Hundreds of times more etching improvement is observed compared to the chemical wet etching, resulting in the successful removal of several centimeters of microstructure.

As shown in Fig. 1, when a bilayer conductive material is deposited on a substrate under the microstructure to be released, the cathode portion of the galvanic cell (one of the layers having a lower oxy-reduction potential) serves as a sacrificial layer and Etched from the side of the microstructure that supports the fast under etching that rapidly leaves the microstructure.

It is noteworthy that the film can be very thin (approximately 10 nm range) and still produce a very well controlled and fast under etch that is also suitable for forming thin gaps. This is not intended to fully support the structure, but is useful in situations where a gap is formed between the structure and the substrate by not inducing only part of the structure.

Another advantage is that because the substrate does not need to be flat, devices fabricated on the full structure substrate can also be displaced as shown in FIGS. 2A-2C.

This sacrificial layer technique can also be used to transfer structures from a substrate of any material that is easy to process. This makes it possible to depart all or part of the device of any material.

1A-1C show process steps according to the method of practicing the present invention. First, the substrate 2 is provided. The substrate may be composed of any suitable material, for example silicon, glass, quartz, ceramics, plastics and the like. The substrate need not be flat and can have any shape.

In the next step, two layers 4, 6 of conductive material are deposited on the substrate. One of the layers consists of a material having a high oxidative-reduction potential, such as noble metals such as Au, Pd, Pt, Ag, Cu and the like. In the following this layer 4 will act as an anode.

The second layer 6 is composed of a material having a lower oxidative-reduction potential than the layer 4, for example Al, Zn, Cr, Fe, Co and the like. In the following this second layer will act as a cathode. Deposition of the two layers must be performed such that electrical contact is present between the two layers.

In a preferred embodiment of the invention, the anode is deposited first and then the cathode acting as a sacrificial layer is deposited after the top of the anode so that the anode does not deviate from the buoyant portion of the microstructure.

After depositing two electrodes on the substrate 2, the microstructure 8 to be separated is formed on top of this structure by standard deposition and structuring techniques of the material which constitutes the desired structure (FIG. 1A).

The second layer 6 will then be electrochemically etched when immersing this structure 10 in a suitable electrolyte 12 as shown in FIG. 4. The electrolyte 12 is preferably composed of a solution or a vapor environment. Thus, a galvanic cell is formed, creating a potential high enough to cause etching or significantly improve the cathode acting as a sacrificial layer.

FIG. 1B shows the final product after only a portion of the microstructure 8 has been dislodged from the substrate, while FIG. 1C shows the disengagement of the complete microstructure 8.

2A-2C show the same process steps for the non-flat substrate 2.

The process shown in FIGS. 1 and 2 may also be used to define very thin cavities or grooves under the microstructure by etching the very thin prestructure sacrificial material as shown in FIGS. 3A and 3B. The sacrificial material is first structured to define the portion that needs to be released. Thus, controlled sized gaps 16 and microgrooves 14 can be fabricated. Embodiments of the present invention are directed to devices such as mechanical oscillators, micro switches, cantilevers, microfluidic channels, micro actuators, suspended coils for RF electronic circuits, and the like. While not only useful for manufacture, it will be understood to be particularly useful for their manufacture.

The present invention can be used in many departure processes in the field of Micro Electro-Mechanical Structure (MEMS), integrated optics or microelectronics. 5 shows a complete departure of a huge photo plastic tip array, for example 1.6 × 6 mm.

When embodiments of the present invention are used with a flip-chip process, even if the technology is incompatible (MEMS, integrated optics, CMOS, III-V, Si-Ge, etc.), any kind of microfabrication structure or device Even the integration into other microstructures or microdevices is possible. In integrated optics, for example, it may be possible to incorporate different devices into different substrates from different technologies (waveguides, mirrors, deflectors, detectors, micro lenses, laser diodes, etc.).

A possible application of the present invention is to integrate cantilevers in CMOS chips. When the cantilever is mounted on a CMOS chip (post CMOS), the process that can be used for the MEMS component is practically limited, and also a problem of some yield is added. A simple process may be to separate the CMOS circuit and the MEMS component. The entire cantilever array can then be dislodged and "flipped" at the end on the CMOS chip. In this case, well controlled flotation of the lever is preferred. Therefore, a preferred embodiment of the present invention is particularly suitable for this process.

Epoxy-based Scanning Near-Field Optical Microscopy (SNOM) probes are made in photosensitive epoxy resist. Pyramid templates previously etched with silicon are used to form the tips. Once the epoxy probe is made, the optical fiber enters the guiding structure and bonds. The entire structure is then suspended from the substrate. This is possible by etching the sacrificial layer. In this case, an interface consisting of an Au layer, a Cr layer, a TaO layer and an Al layer 100 nm thick was designed. The Al layer is used as a light coating on the SNOM tip to prevent light loss caused by light down to the tip tip. The Cr-Au layer forms a galvanic cell with Cr as the negative electrode which is etched away. The TaO layer is an insulating film that electrically insulates the Al film to prevent the formation of a second galvanic cell (formed of the Au film and the Al film), which may lead to unwanted etching.

Claims (15)

In the method of at least partially leaving the microstructure (8) from the substrate (2), (a) providing a substrate 2, (b) depositing a first layer (4) and a second layer (6) each comprising an electrically conductive material on the substrate (2), each having a different oxidative-reduction potential; (c) electrically connecting the first layer 4 and the second layer 6, (d) forming a microstructure on the first layer 4 and the second layer 6 deposited in step (b) to produce an intermediate structure, (e) electrochemically etching the second layer 6 by immersing the intermediate structure 10 formed in step (d) in an electrolyte 12. Micro structure leaving method comprising a. The method of claim 1, And said first layer (4) and said second layer (6) are deposited sequentially and electrically connected before forming said microstructure (8). The method according to claim 1 or 2, And said substrate (2) comprises a material selected from the group consisting of silicon, glass, quartz, ceramics, plastics and the like. The method according to any one of claims 1 to 3, And said substrate (2) is substantially flat. The method according to any one of claims 1 to 4, And said first layer (4) comprises a noble metal. The method of claim 5, Wherein said noble metal is selected from the group comprising Au, Pd, Pt, Ag and Cu. The method according to any one of claims 1 to 6, Said second layer (6) comprises at least one metal selected from the group comprising Al, Zn, Cr, Fe and Co. The method according to any one of claims 1 to 4, And the layers comprise a conductor or a doped semiconductor. The method according to any one of claims 1 to 8, The first layer (4) is characterized in that it has a higher oxidative-reduction potential than the second layer (6). The method according to any one of claims 1 to 9, The first layer (4) is characterized in that the act as a cathode (cathode). The method according to any one of claims 1 to 10, The second layer (6) is a method for leaving the microstructure, characterized in that acts as the anode (anode). The method according to any one of claims 1 to 11, Wherein said first layer (4) and said second layer (6) collectively form a galvanic cell when immersed in said electrolyte (12). The method according to any one of claims 1 to 12, Forming one or more microchannels, cavities (14) and gaps (16) under the microstructure (8). The method according to any one of claims 1 to 13, Wherein said microstructure (8) comprises a microelectronic device. Microstructure formed by the method according to claim 1.