WO2002049082A2 - Traitement de substrats de semi-conducteurs et de masques de gravure - Google Patents

Traitement de substrats de semi-conducteurs et de masques de gravure Download PDF

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Publication number
WO2002049082A2
WO2002049082A2 PCT/US2001/048031 US0148031W WO0249082A2 WO 2002049082 A2 WO2002049082 A2 WO 2002049082A2 US 0148031 W US0148031 W US 0148031W WO 0249082 A2 WO0249082 A2 WO 0249082A2
Authority
WO
WIPO (PCT)
Prior art keywords
silicon wafer
shaping
flatness
polishing
wafer
Prior art date
Application number
PCT/US2001/048031
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English (en)
Other versions
WO2002049082A3 (fr
Inventor
Jeffrey J. Hendron
Arthur Richard Baker, Iii
James Bopp
Todd Crkvenac
Original Assignee
Rodel Holdings, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rodel Holdings, Inc. filed Critical Rodel Holdings, Inc.
Publication of WO2002049082A2 publication Critical patent/WO2002049082A2/fr
Publication of WO2002049082A3 publication Critical patent/WO2002049082A3/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
    • B24B1/005—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes using a magnetic polishing agent
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/22—Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof
    • G03F1/24—Reflection masks; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/60—Substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68707—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a robot blade, or gripped by a gripper for conveyance

Definitions

  • This invention relates, generally, to polishing systems and methods to obtain a substantially flat surface profile and, more particularly, to polishing systems and processes using Magnetorheological finishing, MRF.
  • CMP chemical- mechanical-polishing
  • a common requirement of all CMP processes is that the substrate be uniformly polished. Uniform polishing can be difficult because, typically, there is a strong dependence of the polish removal rate on localized variations in the surface topography of the substrate. For example, the polishing rate at the center of substrate may differ from the polishing rate at the edge of the substrate. Uniform polishing of the entire surface of the substrate is important, because semiconductor manufacturers seek to use as much of each substrate as possible in order to maximize the number of integrated circuit devices, IC devices, that can be built on a useable area of the surface of each substrate.
  • the useable area of a semiconductor substrate is reduced by an unusable region along an edge of the substrate, at a perimeter of the surface, referred to as the edge exclusion area.
  • the edge exclusion area Prior to the invention, was 2mm-3mm wide, as measured diametrically from the perimeter of the substrate surface.
  • the edge exclusion area defines a boundary or perimeter that encircles the useable area available for fabrication of IC devices thereon.
  • the useable area is known as the FQA, flatness quality area, which is manufactured by polishing a major surface of a bare silicon wafer to provide a flat planar surface on the wafer, followed by, successive layers of materials that are deposited onto the surface of the wafer, constructed with a damascene architecture of circuit interconnects and conducting vias, and then planarized by respective CMP operations.
  • the planarized layers of damascene architecture are of nonuniform planarity or flatness, particularly at the unusable edge region of the substrate, which contributes further to the edge exclusion area. There has been a need to reduce the edge exclusion area, which would increase the FQA on the wafer for supporting an increased number of manufactured IC devices.
  • the unusable edge region along the edge of a substrate surface is partly due to nonuniform edge polishing of the cylindrical perimeter of a bare silicon wafer, further referred to as, a silicon substrate or semiconductor substrate.
  • edge polishing was a time consuming process, since the edge regions on both sides of a bare silicon wafer must be polished, one side at a time.
  • the unusable edge regions along the edge of a substrate is partly due to nonuniform polishing of a surface of the silicon wafer in preparation for manufacture of IC devices thereon.
  • the surface of the wafer undergoes a rough polishing operation.
  • Rough polishing intends to provide the wafer surface with a desired global planarity or global flatness.
  • IC devices can not be fabricated on the roll off 3, because the roll off 3 is not flat and coplanar with the central region of the surface 1, and further, the roll off 3 extends below the elevation of the central region of the surface 1. It would be desirable to lower the surface 1 to a lower elevation while maintaining its desired planarity, thus, substantially removing the roll off 3, and desirably increasing the total useable area of the surface 1 on which IC devices can be fabricated.
  • the roll off 3 contributes to the unusable edge region along an edge of the substrate.
  • successive layers of materials are deposited onto the prepared surface 1 of the wafer 2.
  • the materials which deposit onto the roll off 3, are unusable.
  • the cumulative build up of the successive layers on the roll off 3 increase the prominence of the roll off 3.
  • the wafer 2 is subjected to an intermediate step of polishing that provides a useable area of the surface 1 with a desired local flatness and nanotopography. Nanotopography is expressed by, a manufacturing specification of nanometer scale surface height variations of the surface 1 within a unit distance of millimeter scale.
  • the intermediate step of polishing improves the smoothness or texture of the surface 1.
  • the intermediate step of polishing prior to the invention, was capable of introducing further roll off, enhanced dopant striations and a degraded global flatness that was obtained by the previous rough polishing operation.
  • the wafer 2 undergoes a final step of polishing, which further improves the smoothness of the surface 1 in conformance with a manufacturing specification of Angstrom scale RMS roughness of the surface 1 within a unit distance of millimeter scale.
  • the appearance of the surface 1 changes from a haze covered surface 1 to a surface 1 that is smooth, planar and haze free with a reflective finish.
  • Magnetorheological Finishing has been recently developed for shaping optical components to measurement levels well below the capabilities of current methods (e.g., lapping, grinding, polishing).
  • Some of the major advantages of an MRF system include: less than 50 nm (0.5 microns) peak-to-valley flatness capability, conformal polishing media, and deterministic polishing on a variety of materials.
  • Figs. 5 and 6 illustrate the
  • An MRF system is a computer numerically controlled (CNC) polishing tool that can be used to remove sub-surface damage and improve surface features on a variety of materials.
  • CNC computer numerically controlled
  • the MRF system is designed to improve the shape of a previously polished workpiece to metrology levels of measurement well below the capabilities of current methods, such as lapping, grinding and polishing.
  • the polishing media includes a magnetorheological fluid for MRF that mimics a fixed abrasive polishing pad as it comes in contact with the workpiece.
  • the MRF system incorporates the flow of a polishing fluid onto a substrate to be polished.
  • the substrate and polishing fluid are positioned within a magnetic field having a form field shaped by mathematical modeling.
  • the fluid contains a slurry of abrasive particles and ferromagnetic particles, which are aligned by the magnetic field.
  • an optimized MRF system for polishing bare silicon wafers can significantly reduce defects of global flatness scale and defects of site flatness scale, reduce edge polishing cycle time, and can planarize and polish the surface 1.
  • MRF technology can be applied to the polishing of appliances, such as glass reticles and blank glass masks, and ceramic magnetic heads, to provide uniform flatness across the entire working surface of appliance.
  • a process for shaping a semiconductor wafer comprises; positioning a silicon wafer having a surface in a fixturing device; contacting the surface with a magnetorheological fluid in the presence of a magnetic field; and shaping the surface of the silicon wafer to a predetermined degree of flatness.
  • a process for shaping a perimeter surface of a semiconductor wafer comprises; positioning a silicon wafer having a perimeter surface in a fixturing device, wherein the wafer has opposing surfaces; contacting at least the perimeter surface of the silicon wafer with a magnetorheological fluid in the presence of a magnetic field; and simultaneously shaping the opposing surfaces and the perimeter surface to a predetermined degree of flatness.
  • an MRF system is used to polish a surface of a bare silicon wafer, while maintaining its desired planarity, to substantially remove its roll off, and desirably increase the FQA on which IC devices can be fabricated.
  • FIG. 1 illustrates a partial cross-sectional view of a semiconductor substrate in the form of a rough polished wafer, for example, a wafer of silicon;
  • FIG. 2 is a schematic diagram of an edge polishing technique in accordance with the invention.
  • FIG. 3 illustrates experimental results for polishing a glass substrate carried out in accordance with the invention using an MRF system
  • FIG. 4 illustrates experimental results obtained subsequent to the invention by using an MRF system for polishing a semiconductor substrate
  • FIG. 5 illustrates experimental results for polishing an amorphous glass substrate carried out in accordance with the invention using an MRF system
  • FIG. 6 illustrates experimental results for polishing a crystalline glass substrate carried out in accordance with the invention using an MRF system.
  • a semiconductor wafer 2 is shaped to a flatness of surface 1 substantially the same degree as that of a glass substrate using an MRF system.
  • High end, prime silicon manufacturers are capable of consistently producing 200mm wafers with global and site flatness levels to
  • a fixturing device that can be used for positioning a semiconductor substrate or wafer 2 in an MRF system includes, a vacuum plate (grooved or porous plate, ceramic or metal), an electrostatic chuck, a clamp mount, a template assembly mount and the like. Also, a semiconductor substrate or wafer 2 can be wax mounted to an appropriate support surface. An MRF process is then carried out to form a uniformly flat surface across the entire surface of the substrate or wafer 2.
  • the process includes, positioning a substrate or wafer 2 having a surface in a fixturing device and contacting the surface 1 with a magnetorheological fluid in the presence of a magnetic field.
  • the magnetorheological fluid imparts abrasive action on the wafer 2 by flowing in the magnetic field, such that relative motion of the surface 1 and the fluid polishes and shapes the surface 1 with a predetermined site flatness having a nanometer scale topography.
  • Conveying successive portions of the surface 1 in contact with the fluid distributes the polishing and shaping operations onto successive portions of the surface 1.
  • the entire surface 1 to be polished is in contact with the fluid.
  • the fluid is subjected to a magnetic field having a form field that is mathematically configured to conform the fluid while the fluid polishes and shapes the surface 1 being polished.
  • an MRF system is used to edge polish a bare silicon wafer 2, simultaneously polishing a cylindrical perimeter surface 4 and the edge regional areas on opposing surfaces, including the surface 1, on respective sides of the bare silicon wafer 2, which reduces the manufacturing time for attaining an edge polished silicon wafer 2, as well as, increases the FQA by minimization of the edge effect due to edge polishing.
  • a bare silicon wafer 2 that has been edge polished by MRF has a perimeter surface 4 of increased strength to resist breaking off of fragments of particulate material.
  • the surface 4 has a smooth polished finish to reduce contamination-related defects.
  • the conformal polishing media in an MRF system is used to polish the complete substrate edge (both sides and the perimeter surface 4) at one time with good finishing control.
  • a bare silicon wafer 2 i.e. semiconductor substrate
  • a magnetorheological fluid during an MRF process.
  • the entire edge of the substrate or wafer 2 is polished at a controlled material removal rate, with a minimized manufacturing time duration.
  • the wafer 2 is rotated about its central axis to convey successive portions of the wafer 2 into contact with the fluid, which distributes the polishing and flattening operations over the successive portions of the wafer 2.
  • the entire periphery of the wafer 2 can be immersed in contact with the fluid, while conforming the fluid by a magnetic field that is mathematically shaped to polish and conform the perimeter surface 4 and the edge regions that are polished by the MRF system.
  • an MRF system is used to edge polish a bare silicon wafer 2, simultaneously polishing the cylindrical perimeter surface 4 and the edge regional areas on the surfaces 1 on both sides of the bare silicon wafer 2, which reduces the manufacturing time for attaining an edge polished silicon wafer 2.
  • an MRF system and operation supplements the rough polish operation by replacing the intermediate polish operation used prior to the invention to prepare a bare silicon wafer 2 for manufacture of IC devices thereon.
  • the intermediate polishing operation tended to produce a surface 1 with waviness, ripples or undulations having spatial wavelengths ranging from about 0.5mm to about 20mm, which comprise nanometer scale waviness detrimental to the desired smoothness of the FQA of the surface 1 on which IC devices are manufactured.
  • the MRF operation in place of the intermediate polishing operation does not introduce nanometer scale defects in the surface 1 in the form of waviness, and, instead, smoothes the surface 1 by minimizing nanometer scale waviness.
  • the MRF operation in place of the intermediate polishing operation substantially eliminates roll off 3, and improves the site flatness of the surface 1.
  • the FQA is maximized to increase the number of IC devices that can be manufactured on the surface 1.
  • the MRF operation increases the FQA of the surface 1 substantially to as near the perimeter surface 4 of the wafer 2 as can be measured by existing metrology, for example, by capacitance gauge metrology. Improving the site flatness, as measured by standard site flatness metrology, reduces the occurrence of nonplanar or rough surface areas, thus improving the yield of IC devices.
  • the MRF operation leaves a surface texture of nanometer scale height variations that tailors the surface 1 for removal of the surface texture to a smooth finish by a final polishing operation.
  • the MRF system benefits a semiconductor substrate polishing process by replacing the traditional intermediate polishing operation with an MRF flattening operation that does not create or enhance nanotopography surface features in the substrate.
  • the flatness of a semiconductor substrate or wafer 1 is improved using the MRF system to shape a substrate carrier plate (polishing plate) of apparatus for performing rough polishing of a wafer 2, to compensate for the shape induced during a typical rough polishing process.
  • the polishing plate is typically made of a ceramic or metal material.
  • an MRF system is programmed to shape the carrier plate to match the desired substrate shape. This technique can be used with wax oi ⁇ free-mount (template assembly) fixturing.
  • an MRF system is used to polish large glass sample materials, such as blank lithographic masks, and in particular lithographic masks used in ultra-violet (UN) lithography, to extremely flat tolerances.
  • Reflective masks such as those used for enhanced extreme Ultra-Niolet (EUV) lithography must meet a much higher standard of flatness than conventional transmissive masks.
  • a blank glass mask is polished to a TIR measurement, i.e. a peak to valley flatness of no more than about 0.050 ⁇ m.
  • conventional grinding, shaping, and polishing systems will not meet this standard, which typically provides about a TIR measurement of flatness on the order of about 500 nm.
  • a blank glass mask can be prepared having a satisfactory Angstrom scale surface roughness.
  • An additional benefit of glass mask processing using an MRF system is that the surface can remain free of polishing induced defects, which will result in fewer defects in subsequent coatings applied to the mask.
  • EXAMPLE 1 A glass sample was pre-measured for flatness, polished, and post-measured using a Q22 MRF system commercially available from QED Technologies, Rochester, New York, and a Zygo GPI interferometer. The glass sample was placed in the system, and a polish site size of about 100mm diameter was polished for about 30 minutes.
  • FIG. 3 The results from the test are illustrated in FIG. 3. From left to right, the plots of FIG. 3 show the pre-polish flatness, the computer predicted values, and the actual post-polish flatness. Based on the data the following conclusions can be made: (1) the peak-to-valley flatness was reduced from the original value of about 1.01 ⁇ m to about 0.14 ⁇ m; (2) the RMS measurement of flatness was reduced from the original value of about 0.214 ⁇ m to about 0.020 ⁇ m.
  • an MRF system is used to polish a surface of a bare silicon wafer, while maintaining its desired planarity, to substantially remove its roll off, and desirably increase the FQA on which IC devices can be fabricated.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Robotics (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

L'invention concerne un système et un procédé de traitement de semi-conducteurs par finition magnétorhéologique (MRF). Ce procédé consiste à polir les substrats de semi-conducteurs, de corps céramique et de masques de gravure sur verre, jusqu'à obtention d'un degré élevé de planéité par l'action abrasive d'un fluide magnétorhéologique s'écoulant dans un champ magnétique.
PCT/US2001/048031 2000-12-11 2001-12-11 Traitement de substrats de semi-conducteurs et de masques de gravure WO2002049082A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25504000P 2000-12-11 2000-12-11
US60/255,040 2000-12-11

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WO2002049082A2 true WO2002049082A2 (fr) 2002-06-20
WO2002049082A3 WO2002049082A3 (fr) 2002-10-10

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US (1) US20020081943A1 (fr)
WO (1) WO2002049082A2 (fr)

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CN103495908A (zh) * 2013-10-11 2014-01-08 中国科学院微电子研究所 一种对InP基RFIC晶圆进行磁流变减薄抛光的方法
CN110883608A (zh) * 2019-10-22 2020-03-17 中国工程物理研究院机械制造工艺研究所 一种磁流变抛光边缘去除函数建模与边缘效应抑制方法

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US20050236358A1 (en) * 2004-04-26 2005-10-27 Shen Buswell Micromachining methods and systems
US7514016B2 (en) * 2004-07-30 2009-04-07 Hitachi Global Storage Technologies Netherlands, Bv Methodology of chemical mechanical nanogrinding for ultra precision finishing of workpieces
JP5402391B2 (ja) * 2009-01-27 2014-01-29 信越化学工業株式会社 半導体用合成石英ガラス基板の加工方法
US8271120B2 (en) * 2009-08-03 2012-09-18 Lawrence Livermore National Security, Llc Method and system for processing optical elements using magnetorheological finishing
US8780440B2 (en) * 2009-08-03 2014-07-15 Lawrence Livermore National Security, Llc Dispersion compensation in chirped pulse amplification systems
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US20130225049A1 (en) * 2012-02-29 2013-08-29 Aric Bruce Shorey Methods of Finishing a Sheet of Material With Magnetorheological Finishing
GB201313054D0 (en) * 2013-07-22 2013-09-04 Bergen Teknologioverforing As Method of forming a desired pattern on a substrate
US9941433B2 (en) * 2014-12-11 2018-04-10 Vadient Optics, Llc Composite quantum-dot materials for photonic detectors
RU2617697C1 (ru) * 2016-03-04 2017-04-26 Акционерное общество "Научно-исследовательский институт "Полюс" им. М.Ф. Стельмаха" Способ упрочнения оптического контакта диэлектрических поверхностей лазерного гироскопа и генератор струи плазмы для его реализации
JP6803186B2 (ja) * 2016-09-30 2020-12-23 Hoya株式会社 マスクブランク用基板、多層反射膜付き基板、マスクブランク、転写用マスク及び半導体デバイスの製造方法
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WO2000068332A1 (fr) * 1999-05-06 2000-11-16 Mpm Ltd. Fluides de polissage magnetique
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CN110883608A (zh) * 2019-10-22 2020-03-17 中国工程物理研究院机械制造工艺研究所 一种磁流变抛光边缘去除函数建模与边缘效应抑制方法

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