WO2002047377A1 - Photosensor and photosensing method - Google Patents

Photosensor and photosensing method Download PDF

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Publication number
WO2002047377A1
WO2002047377A1 PCT/JP2001/010737 JP0110737W WO0247377A1 WO 2002047377 A1 WO2002047377 A1 WO 2002047377A1 JP 0110737 W JP0110737 W JP 0110737W WO 0247377 A1 WO0247377 A1 WO 0247377A1
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WO
WIPO (PCT)
Prior art keywords
charge
conversion circuit
output
voltage conversion
voltage
Prior art date
Application number
PCT/JP2001/010737
Other languages
French (fr)
Japanese (ja)
Inventor
Seiichiro Mizuno
Original Assignee
Hamamatsu Photonics K.K.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hamamatsu Photonics K.K. filed Critical Hamamatsu Photonics K.K.
Priority to AU2002221085A priority Critical patent/AU2002221085A1/en
Publication of WO2002047377A1 publication Critical patent/WO2002047377A1/en

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Classifications

    • H01L27/14609
    • H01L27/14643
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50Control of the SSIS exposure
    • H04N25/53Control of the integration time
    • H04N25/533Control of the integration time by using differing integration times for different sensor regions
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/621Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/76Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present invention relates to an apparatus and a method for detecting the intensity of incident light.
  • the light detection device includes one or more light detection elements, and a charge-voltage conversion circuit that outputs a voltage output according to the amount of charge output from the light detection elements.
  • the charge output from the photodetector in response to the incidence of light is accumulated in the charge-voltage conversion circuit, and a voltage output corresponding to the amount of the accumulated charge is output from the charge-voltage conversion circuit. Output, and an incident light intensity is obtained based on the output voltage output value.
  • a photodetection device can be manufactured by the CMOS technology.
  • a P-type semiconductor region is formed on a P-type semiconductor substrate, and an N-type impurity region is formed in the P-type semiconductor region, thereby forming a photodiode (photodetector) having a PN junction.
  • a first N-type impurity region (source region) and a second N-type impurity region (drain region) are formed in the P-type well region, and a gate electrode is formed therebetween. As a result, a switch element is formed.
  • This switch element is provided between the output terminal of the photodiode and the input terminal of the charge-to-voltage conversion circuit, and opens and closes based on the voltage value applied to the gate electrode, and the charge voltage of the charge generated by the photodiode Controls the flow into the conversion circuit. Further, the N-type impurity region of the photodiode and the source region of the switch element may be common.
  • a set of photodiodes and switch elements is arranged in M rows and N columns (M is an integer of 1 or more, N is an integer of 2 or more).
  • N charge-voltage conversion circuits are provided, and N photodiodes in the m-th row have switch elements at the input terminals of the m-th charge-voltage conversion circuit (m is any integer from 1 to M). Connected through.
  • Each of the N switch elements is sequentially closed, and the charge generated by the photodiode corresponding to the closed switch element flows into the charge-voltage conversion circuit and is accumulated, and the amount of the accumulated charge is Is output from the charge-voltage conversion circuit. In this way, the intensity of light incident on each photodiode for each row is sequentially detected, and a one-dimensional or two-dimensional light image is captured.
  • the charge generated by the photodiode in response to the incident light flows into the charge-to-voltage conversion circuit when the switch element closes, and the charge-to-voltage conversion occurs.
  • the charge is stored by the circuit, and a voltage output corresponding to the amount of the stored charge is output from the charge-voltage conversion circuit.
  • a switch element has a PN junction between a P-type well region and a drain region, so that charge is generated when light enters. Then, the charge generated by the switch element flows into the charge-voltage conversion circuit and is accumulated by the charge-voltage conversion circuit regardless of the open / closed state of the switch element. That is, not only the charge generated by the photodiode but also the charge generated by the switch element is accumulated by the charge-voltage conversion circuit.
  • the amount of charge generated in the switch element is smaller than the amount of charge generated in the photodiode, and the ratio between the two is smaller. It is constant. Therefore, in the normal case, the influence of the charge generated in the switch element is small.
  • the present invention has been made in order to solve the above problems, and an object of the present invention is to provide a light detection device and a light detection method capable of detecting an accurate incident light intensity while suppressing the influence of a blooming phenomenon.
  • the photodetector comprises: (1) a photodetector that generates an amount of electric charge according to the intensity of incident light; and (2) a switch element that controls the output of the electric charge generated by the photodetector. (3) a charge-to-voltage conversion circuit that accumulates the electric charge generated by the photodetector and arrives via the switch element in the integration capacitance section, and outputs a voltage output corresponding to the amount of electric charge accumulated in the integration capacitance section; (4) control means for terminating the charge accumulation in the integration capacitance section before the time when the saturation charge is accumulated in the integration capacitance section of the charge-voltage conversion circuit when the charge generated in the photodetector is saturated. , Is provided.
  • the charge generated according to the intensity of the light incident on the photodetector reaches the charge-to-voltage conversion circuit via the switch element, and is accumulated in the integration capacitance section of the charge-to-voltage conversion circuit .
  • a voltage output corresponding to the amount of charge stored in the integration capacitance section is output from the charge-voltage conversion circuit.
  • the charge accumulation in the integration capacitance section is controlled by the control means, and if the charge generated in the photodetector is temporarily saturated, the charge before the time when the saturated charge is accumulated in the integration capacitance section of the charge-voltage conversion circuit is obtained. To end.
  • This time substantially corresponds to the time at which the amount of charge generated in the switch element starts to be accumulated in the integration capacitance unit. That is, from the time when the charge exceeding the saturation charge of the photodetector was accumulated in the integration capacitor, the charge was generated in each switch element. Although the charge starts to be accumulated in the integration capacitance section, which affects the output accuracy of the charge-voltage conversion circuit, according to the device of the present invention, the charge accumulation ends before this time. As described above, since the charge accumulation in the integration capacitance section is completed before the charge accumulation by the switch element is started, the influence of the blooming phenomenon is suppressed, and the accurate incident light intensity is detected.
  • the photodetector includes: (1) a saturated charge generating means for generating a saturated charge at a time when the switch element is closed; and (2) operating characteristics equivalent to those of the charge-voltage conversion circuit, A dummy charge-to-voltage converter that accumulates the generated charges and outputs a voltage output according to the amount of the accumulated charges; and (3) a voltage output value and a threshold value output from the dummy charge-to-voltage converter. And a comparison circuit that outputs a saturation signal indicating that the value of the voltage output reaches a threshold value when the voltage output value reaches a threshold value.
  • the control means terminates the charge accumulation in the integration capacitance section of the charge-voltage conversion circuit based on the saturation signal output from the comparison circuit.
  • the saturated charge generated by the saturated charge generating means at the time when the switch element is closed is accumulated by the dummy charge-to-voltage conversion circuit, and a voltage output corresponding to the amount of the accumulated charge is output from the dummy charge-to-voltage conversion circuit. Is output.
  • the value of the voltage output output from the dummy charge voltage conversion circuit and the threshold value are compared by the comparison circuit, and when the value of the voltage output reaches the threshold value, a saturation signal indicating that fact is output from the comparison circuit. Then, based on the saturation signal output from the comparison circuit, the control means terminates the charge accumulation in the integration capacitance section of the charge-voltage conversion circuit.
  • the photodetection method includes a photodetection element that generates and outputs an amount of charge corresponding to the intensity of incident light, and a scan that controls output of the charge generated by the photodetection element.
  • a switch element, and a charge-to-voltage conversion circuit that accumulates the electric charge generated by the light detection element and arrives via the switch element in the integration capacitance section and outputs a voltage output according to the amount of electric charge accumulated in the integration capacitance section.
  • the charge generated according to the intensity of the light incident on the photodetector reaches the charge-voltage converter via the switch, and is integrated by the charge-voltage converter. It is stored in the capacity part. A voltage output corresponding to the amount of charge stored in the integration capacitance section is output from the charge-voltage conversion circuit. Then, the charge accumulation in the integration capacitance unit ends before the time when the saturation charge is accumulated in the integration capacitance unit of the charge-voltage conversion circuit when the charge generated in the photodetector is temporarily saturated. Therefore, similarly to the above, the charge accumulation is completed before the time corresponding to the charge from the switch element is accumulated in the integration capacitance portion, thereby suppressing the effect of the plumming phenomenon and reducing the accurate incident light intensity. Is detected.
  • FIG. 1 is a configuration diagram of a photodetector 1 according to the present embodiment.
  • FIGS. 2A and 2B are explanatory diagrams of the photodiode PD mn and the switch element SW mn of the photodetector 1 according to the present embodiment.
  • Figure 3 is a circuit diagram of a charge-voltage conversion circuit 1 1 O m of the photodetector 1 according to the present embodiment.
  • FIG. 4 is a circuit diagram of the timing detection circuit 300 of the photodetector 1 according to the present embodiment.
  • FIGS. 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H are timing charts for explaining the operation of the light detection device 1.
  • FIG. 6 is a circuit diagram of another configuration example of the charge-voltage conversion circuit 1 1 o m of the photodetector 1 according to the present embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a configuration diagram of a photodetector 1 according to the present embodiment.
  • This photodetector 1 is composed of M (M is an integer of 1 or more) cuts 10 ( ⁇ to ⁇ 0 0 M AZD conversion circuit 200, timing detection circuit 30) on one semiconductor substrate. 0 and a control circuit 400.
  • M is an integer of 1 or more
  • N is an integer of 2 or more
  • photodiodes photodetectors
  • a PD ML PD N number of switch elements SW ⁇ SW ⁇ charge-voltage conversion circuit 1 1 0 M and Suitsuchi element 1 2 0 M.
  • MX N photodiode PDUs PDMN are arrayed in M rows and N columns in the imaging area.
  • the photodiode PD mn is located at the m-th row and the n-th column, and generates an amount of electric charge according to the intensity of incident light.
  • Switch element SW MN is compatible with photodiode PD MN, is provided between the input end of Fotodaiodo PD MN and the charge-voltage conversion circuit 1 1 0 m, generated in the photodiode PD MN Controls the output of charges.
  • the input end of the charge-voltage conversion circuit 1 1 0 M is connected to the N switch elements SW ⁇ SW ⁇ by A 1 line 1 9 0 M.
  • Charge-voltage converting circuit 1 1 0 M is to accumulate the charges arriving via generated in the photo die Odo PD MN Suitsuchi element SW MN in the integral capacitance part, corresponding to the amount of charge accumulated in the integral capacitance part Outputs voltage output.
  • Switch element 1 2 0 M is provided between the input of the charge-voltage conversion circuit 1 1 0 M output terminal and the A / D converter circuit 2 00.
  • the switch elements 120 M of each unit 100 M are controlled by the control circuit 400 and closed sequentially, and the voltage output from the charge-voltage conversion circuit 110 m is converted to the A / D conversion circuit 2. 0 Input to 0.
  • a / D conversion circuit 2 0 each Interview - Enter the Tsu preparative 1 0 0 RA charge-voltage conversion circuit 1 1 0 M voltage output sequentially arrive via the switch element 1 2 0 RA from, the voltage output To A Performs ZD conversion and outputs digital output.
  • the timing detection circuit 300 is a circuit for detecting the opening / closing timing of each switch element SWmn .
  • the control circuit 400 controls the opening and closing of the switch elements SW mn based on the closing timing detected by the timing detection circuit 300, controls the charge storage operation in the charge-voltage converting circuit 11 O m, each Suitsuchi element 12 and controlling the opening and closing of O m, also, AZD conversion circuit 20
  • FIG. 2A and 2B are explanatory diagrams of the photodiode PD ran and the switch element SW mn of the photodetector 1 according to the present embodiment.
  • FIG. 2A shows the photodiode PD mn and the switch element SW mn formed.
  • FIG. 2B shows an equivalent circuit including a photodiode PD mn and a switch element SW mn , schematically showing a cross section of a P-type semiconductor substrate.
  • P-type Ueru region 90 l mn on the surface of the P-type semiconductor substrate 900 is formed, the P-type Ueru region 90 :!
  • an N + type impurity region 91 l mn and an N + type impurity region 912 mn are formed at a certain interval from each other, and extend over a part of each of the N + type impurity region 91 l ran and the N + type impurity region 912 mn.
  • a gate electrode 920 mn is formed on the insulating film on the surface of the P-type semiconductor substrate 900.
  • PN junctions are formed between the P-type semi-conductor substrate 900 mn of P-type Ueru region 90 l mn and the N + -type impurity regions 91 l mn, photodiode PD mn is formed by the PN junction.
  • the N + type impurity region (source region) 911 ran , the N + type impurity region (drain region) 912 mn and the gate electrode 920 mn constitute a switch element SW mn having an M ⁇ S-FET structure. Further, 190 m of A1 wiring (parasitic capacitance value Cv) is formed on the surface including a part of N + type impurity region 912 mn .
  • the A1 wiring 190 ra electrically connects the N + type impurity region 912 mn of each of the N switch elements SW ml to SW mN in the m-th row and the input terminal of the charge-voltage conversion circuit 110 m .
  • a PN junction is also formed between the P-type well region 901 mn and the N + -type impurity region (drain region) 912 mn of the P-type semiconductor substrate 900.
  • a photodiode equivalent (hereinafter referred to as “photodiode PD dmey ”) is configured. Accordingly, N + -type When light is incident on the impurity region 9 1 2 mn, P-type PN junction between the P-type Uweru region 90 l mn and the N + -type impurity region 9 12 mn of the semiconductor substrate 900 (Fotodaiodo PD dy ), A charge is generated.
  • FIG. 3 is a circuit diagram of the charge-voltage conversion circuit 11 Ora of the photodetector 1 according to the present embodiment.
  • Each charge-voltage converting circuit 1 1 o m includes an amplifier 1 1 1, the capacitor (the integral capacitance part) 1 1 2 and switch element 1 1 3.
  • the inverting input terminal of the amplifier 111 is connected to the N + -type impurity region (drain region) 91 2 mn of each of the N switch elements SW ⁇ SW ⁇ in the m-th row via the A 1 line 19 O m. It is connected. Further, a capacitive element 112 and a switch element 113 are provided in parallel between the inverting input terminal and the output terminal of the amplifier 111.
  • the reference voltage Vref is supplied to the non-inverting input terminal of the amplifier 111.
  • the charge-voltage conversion circuit 1 1 O ra when the switch element 1 1 3 closes, the capacitor element 1 12 is discharged, the voltage output is outputted from the output is initialized.
  • the charge-voltage conversion circuit 1 1 O m when Suitsuchi element 1 13 is open, the input The charge that has flowed into the terminal is stored in the capacitor 112, and a voltage output corresponding to the amount of the stored charge is output from the output terminal.
  • V of voltage output that is output from the output terminal of the charge-voltage conversion circuit 1 1 o m at time t is expressed by the following equation.
  • V Q / Cf
  • Q mn indicates the amount of charge flowing from the photodiode PD drapecorresponding to the closed switch element SW mn among the N photodiodes PD ml to PD rt in the m-th row. shows the total amount of the first 111 rows of] ⁇ number of switch element 3 "1-3 respectively generated per unit time in Oke Ru photodiode PD DUMY charge (or current). Further, C 112 is the capacitance element This is the capacitance value of 1 1 2.
  • FIG. 4 is a circuit diagram of the timing detection circuit 300 of the photodetector 1 according to the present embodiment.
  • the timing detection circuit 300 includes a charge-voltage conversion circuit 310, a capacitance element 320, a comparison circuit 330, and a D latch circuit 340.
  • Charge-voltage converting circuit 310 of the timing detection circuit 300 has been made in view of the charge-voltage conversion circuit 1 1 O ra equivalent operating characteristics of each Yunitto 10 O m, amplifier 1 1 1 and the amplifier 31 1 of the same, etc., the capacity It has a capacitive element 312 equivalent to the element 112 and a switch element 313 equivalent to the switch element 113.
  • the inverting input terminal of the amplifier 311 is connected to the capacitive element 320 via the A1 wiring 390.
  • a capacitor 312 and a switch element are connected between the inverting input terminal and the output terminal of the amplifier 311. 3 1 3 are provided in parallel.
  • the reference voltage Vref is supplied to the non-inverting input terminal of the amplifier 311.
  • the charge-to-voltage conversion circuit 310 In the charge-voltage conversion circuit 310, when the switch element 313 is closed, the capacitance element 312 is discharged, and the voltage output output from the output terminal is initialized. On the other hand, when the switch element 313 is open, the charge-to-voltage conversion circuit 310 accumulates the electric charge flowing into the input terminal into the capacitive element 312, and generates a voltage corresponding to the amount of the accumulated electric charge. Output from the output terminal.
  • One terminal of the capacitive element 320 is connected to the input terminal of the charge-voltage conversion circuit 31 via the A1 wiring 390, and the other terminal is connected to the control circuit 400.
  • AV′C 32 is input to the input terminal of the charge-voltage conversion circuit 310 . Only charge flows in. Where C 32 . Is the capacitance value of the capacitor 320.
  • the charge amount AV′C 320 is made equal to the saturation charge amount in each photodiode PD mn .
  • the parasitic capacitance of the A 1 line 3 9 0 timing detection circuit 3 0 0 is equal to the parasitic capacitance value Cv of the A 1 line 1 9 O m of each Yunitto 1 0 O ra.
  • the amount of charge accumulated in the capacitance element 312 of the charge-voltage conversion circuit 310 is represented by the parasitic capacitance value Cv of the A1 wiring 390 and the capacitance value C32 of the capacitance element 320 .
  • the capacitive element 320 acts as a saturated charge generating means for generating a saturated charge when the voltage value applied from the control circuit 400 decreases by ⁇ .
  • the comparison circuit 330 inputs the voltage output output from the charge-voltage conversion circuit 310 to the inverting input terminal, and inputs the threshold voltage Vth to the non-inverting input terminal. Then, the comparison circuit 330 outputs a logical output of a logical value H when the voltage output value is smaller than the threshold voltage Vth, and outputs a logical output of a logical value L when the voltage output value is larger than the threshold voltage Vth.
  • the threshold voltage Vth is the saturation charge AV.C 32 in the capacitor 312. Is set to a value that is somewhat smaller than the value of the voltage output output from the output terminal of the charge-voltage conversion circuit 310 when the charge of the charge is accumulated.
  • the logic output (saturation signal) output from the output terminal of the comparison circuit 330 changes from the logical value H to the logical value L at a time slightly earlier than the time at which the charge accumulation in 312 is saturated.
  • the D latch circuit 340 inputs the logical output (saturation signal) output from the comparison circuit 330 to the C1r terminal, and determines the voltage value applied to the capacitive element 320 from the control circuit 400.
  • the logical value L is output from the Q terminal of the D latch circuit 340, and the voltage applied to the capacitive element 320 from the control circuit 400 is ⁇ V only.
  • the logical output input to the C 1 r terminal from the comparison circuit 330 is the logical value H, and after this time, the logical value H is output from the Q terminal of the D latch circuit 340.
  • the logic output input to the C1r terminal from the comparison circuit 330 changes to a logic value L
  • the logic value L is output from the Q terminal of the D latch circuit 340 after this time.
  • the logical output output from the Q terminal of the D latch circuit 340 of the timing detection circuit 300 configured as described above indicates the opening / closing timing of each switch element SW mn .
  • the control circuit 400 changes the voltage value applied to the capacitive element 320 of the timing detection circuit 300 at a predetermined timing, and outputs the voltage from the Q terminal of the D latch circuit 340 of the timing detection circuit 300. Input logical output.
  • control circuitry 4 0 0 controls the opening and closing of the switch elements SW mn based on a logical output which is output from the timing detection circuit 3 0 0, the charge storage operation in the charge-voltage conversion circuit 1 1 0 m To control the opening and closing of each switch element 120 m , and the AZD conversion operation in the AZD conversion circuit 200.
  • the operation of the light detection device 1 according to the present embodiment will be described, and the light detection method according to the present embodiment will be described. The following operation is performed based on the control by the control circuit 400.
  • M units 10 ( ⁇ to ⁇ 00 M operate in parallel at the same timing.
  • N switch elements SW ml to SW mN are closed in order, and N units In each of the photodiodes PD ⁇ PD ⁇ , the charges generated due to the incidence of light are sequentially input to the charge-voltage conversion circuit 11 1 o m via the A 1 wiring 190 ra .
  • 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H are timing charts for explaining the operation of the photodetector 1 according to the present embodiment. is there. In this figure, a case will be described in which a charge generated by light incidence in the photodiode PD mn located in the m-th row and the eleventh column is input to the charge-voltage conversion circuit 11ora .
  • the voltage output value output from 0 becomes the reset level (Fig. 5D).
  • the N switch elements SW ⁇ SW ⁇ are open (Fig. 5G).
  • a predetermined voltage value is supplied from the control circuit 400 to the capacitive element 320 of the timing detection circuit 300 (FIG. 5C).
  • the logical output output from the comparison circuit 330 becomes a logical value H (FIG. 5E)
  • the logical output output from the Q terminal of the D latch circuit 340 is a logical value L) (FIG. 5F).
  • the switch element 113 of the charge-voltage conversion circuit 110 is opened (FIG. 5A), and the charge can be accumulated in the capacitance element 112 of the charge-voltage conversion circuit 110 m .
  • the switch element 313 of the charge-voltage conversion circuit 310 is opened (FIG. 5B), and the charge is stored in the capacitance element 312 of the charge-voltage conversion circuit 310.
  • the voltage value supplied from the control circuit 400 to the capacitive element 320 of the timing detection circuit 300 decreases by AV (FIG. 5C).
  • the logical output output from the Q terminal of the D latch circuit 340 changes to the logical value H (FIG. 5F).
  • the saturation charge ⁇ V ⁇ C32 is also be closed.
  • each of the charge-voltage conversion circuit 110 m and the charge-voltage conversion circuit 310 have the same operating characteristics as each other, and the parasitic capacitance value of each of the A1 wiring 190 m and the A1 wiring 390 Are the same as each other. Therefore, charges generated in the photodiode PD mn is be saturated charge amount, the charge storage prior to time accumulated saturation charge in the capacitor 1 1 2 of the charge-voltage conversion circuit 1 1 O m is completed . At this time, the charge accumulation in the capacitive element 112 of the integration capacitance section is controlled by the control means, and if the charge generated in the photodiode PD mn is temporarily saturated, the saturated charge is integrated by the charge-voltage conversion circuit.
  • this time substantially corresponds to the time when the amount of charge generated in the switch element SWmn starts to be accumulated in the capacitance element 112 of the integration capacitance section.
  • this time ends before.
  • the charge accumulation in the capacitive elements 112 ends before the charge accumulation by the switch element SWmn starts, the influence of the blooming phenomenon is suppressed, and the accurate incident light intensity is detected. Is done.
  • the threshold voltage Vth is set appropriately.
  • the operating characteristics are also the same.
  • a control signal for controlling the opening / closing timing of the switch element SWmn may be externally provided to the photodetector 1.
  • the switch element sw mn is closed only during the period in which the effect of the blooming phenomenon is suppressed when the light with high intensity is incident on the photodetector 1.
  • the charge-voltage conversion circuit 1 1 O m may be configured as shown in FIG.
  • the charge voltage shown in FIG conversion circuit 1 1 0 ra comprises an amplifier 1 1 1, capacitor element 1 1 2 il 1 2 4 and switch element 1 1 3 1 1 3 4.
  • Amplifier 1 1 between the first inverting input terminal and the output terminal, the capacitive element 1 1 2 serially connected capacitance element 1 1 2 2 mutually And switch element 1 1 3 2, capacitor element 1 1 2 3 and sweep rate Tutsi element 1 1 3 3 connected in series with each other, the capacitive element 1 1 2 4 and switch element 1 1 3 4 connected in series with each other, as well as switch Elements 113 i are provided in parallel.
  • the capacitance value of the integral capacitance part of the charge-voltage conversion circuit 1 1 0 m is determined according to the switch device 1 1 3 2-1 1 3 4 closed state of their respective. By doing so, the capacitance value of the integration capacitance section can be appropriately set according to the incident light intensity.
  • the present invention can be used for an apparatus and a method for detecting the intensity of incident light.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A photo sensor (1) comprises M units (1001 to 100M), an A/D conversion circuit (200), a timing detecting circuit (300), and a control circuit (400). Each unit (100m) has N photodiodes (PDm1 to PDmN), N switching elements (SWm1 to SWmN), charge voltage conversion circuit (110m), and a switching element (120m). If the charge produced in the photodiode (PDmn) and detected by the timing detecting circuit (300) is saturated, the control circuit (400) controls the switching of each switching element (SWmn) at the timing at which the charge accumulation in an integration capacitor of the charge voltage conversion circuit (110m) is stopped before the time when the saturated charge is accumulated in the integration capacitor. As a result, the influence of the blooming is suppressed and the intensity of the incident light can be accurately measured.

Description

明糸田書  Akitoda
光検出装置およぴ光検出方法  Photodetector and photodetection method
技術分野 Technical field
本発明は、 入射した光の強度を検出する装置および方法に関するものである。 背景技術  The present invention relates to an apparatus and a method for detecting the intensity of incident light. Background art
光検出装置は、 1または複数の光検出素子と、 光検出素子から出力された電荷 の量に応じた電圧出力を出力する電荷電圧変換回路と、 を備えている。 この光検 出装置では、 光の入射に応じて光検出素子から出力された電荷が電荷電圧変換回 路に蓄積され、 この蓄積された電荷の量に応じた電圧出力が電荷電圧変換回路か ら出力されて、 この出力された電圧出力の値に基づいて入射光強度が得られる。 このような光検出装置は C M O S技術により製造することが可能である。 例え ば、 P型半導体基板に P型ゥエル領域が形成され、 この P型ゥエル領域内に N型 不純物領域が形成されて、 これにより P N接合を有するフォトダイオード (光検 出素子)が形成される。また、上記 P型ゥエル領域内に第 1の N型不純物領域(ソ ース領域) と第 2の N型不純物領域 (ドレイン領域) とが形成され、 これらの間 にゲート電極が形成されて、 これによりスィッチ素子が形成される。 このスイツ チ素子は、 フォトダイオードの出力端と電荷電圧変換回路の入力端との間に設け られ、 ゲート電極に印加される電圧値に基づいて開閉して、 フォトダイオードで 発生した電荷の電荷電圧変換回路への流入を制御する。 また、 フォトダイオード の N型不純物領域と、 スィッチ素子のソース領域とは、 共通のものであってもよ い。  The light detection device includes one or more light detection elements, and a charge-voltage conversion circuit that outputs a voltage output according to the amount of charge output from the light detection elements. In this photodetector, the charge output from the photodetector in response to the incidence of light is accumulated in the charge-voltage conversion circuit, and a voltage output corresponding to the amount of the accumulated charge is output from the charge-voltage conversion circuit. Output, and an incident light intensity is obtained based on the output voltage output value. Such a photodetection device can be manufactured by the CMOS technology. For example, a P-type semiconductor region is formed on a P-type semiconductor substrate, and an N-type impurity region is formed in the P-type semiconductor region, thereby forming a photodiode (photodetector) having a PN junction. . Further, a first N-type impurity region (source region) and a second N-type impurity region (drain region) are formed in the P-type well region, and a gate electrode is formed therebetween. As a result, a switch element is formed. This switch element is provided between the output terminal of the photodiode and the input terminal of the charge-to-voltage conversion circuit, and opens and closes based on the voltage value applied to the gate electrode, and the charge voltage of the charge generated by the photodiode Controls the flow into the conversion circuit. Further, the N-type impurity region of the photodiode and the source region of the switch element may be common.
また、 1次元または 2次元の光像を撮像する光検出装置では、 フォトダイォー ドおよびスィッチ素子の組が M行 N列 (Mは 1以上の整数、 Nは 2以上の整数) に配列され、 M個の電荷電圧変換回路が設けられていて、 第 m番目 (mは 1以上 M以下の任意の整数) の電荷電圧変換回路の入力端に第 m行の N個のフォトダイ オードがスィッチ素子を介して接続されている。 この光検出装置では、 各行につ いて、 N個のスィッチ素子それぞれが順次に閉じて、 その閉じたスィッチ素子に 対応するフォトダイォードで発生した電荷が電荷電圧変換回路に流入して蓄積さ れて、 その蓄積された電荷の量に応じた電圧出力が電荷電圧変換回路から出力さ れる。 このようにして、 各行について各フォトダイオードに入射した光の強度が 順次に検出されて、 1次元または 2次元の光像が撮像される。 In a photodetector that captures a one-dimensional or two-dimensional optical image, a set of photodiodes and switch elements is arranged in M rows and N columns (M is an integer of 1 or more, N is an integer of 2 or more). N charge-voltage conversion circuits are provided, and N photodiodes in the m-th row have switch elements at the input terminals of the m-th charge-voltage conversion circuit (m is any integer from 1 to M). Connected through. In this photodetector, Each of the N switch elements is sequentially closed, and the charge generated by the photodiode corresponding to the closed switch element flows into the charge-voltage conversion circuit and is accumulated, and the amount of the accumulated charge is Is output from the charge-voltage conversion circuit. In this way, the intensity of light incident on each photodiode for each row is sequentially detected, and a one-dimensional or two-dimensional light image is captured.
発明の開示 Disclosure of the invention
以上のように C MO S技術により構成される光検出装置では、 光の入射に応じ てフォトダイォードで発生した電荷は、 スイツチ素子が閉じることにより電荷電 圧変換回路へ流入して電荷電圧変換回路により蓄積され、 この蓄積された電荷の 量に応じた電圧出力が電荷電圧変換回路から出力される。  As described above, in the photodetector configured by the CMOS technology, the charge generated by the photodiode in response to the incident light flows into the charge-to-voltage conversion circuit when the switch element closes, and the charge-to-voltage conversion occurs. The charge is stored by the circuit, and a voltage output corresponding to the amount of the stored charge is output from the charge-voltage conversion circuit.
—方、 上述したように、 スィッチ素子でも、 P型ゥエル領域とドレイン領域と の間に P N接合を有していることから、光が入射すると電荷が発生する。そして、 このスィッチ素子で発生した電荷は、 スィッチ素子の開閉状態に拘わら 、 電荷 電圧変換回路へ流入して電荷電圧変換回路により蓄積される。 すなわち、 フォト ダイオードで発生した電荷だけでなく、 スィッチ素子で発生した電荷も、 電荷電 圧変換回路により蓄積される。  On the other hand, as described above, even a switch element has a PN junction between a P-type well region and a drain region, so that charge is generated when light enters. Then, the charge generated by the switch element flows into the charge-voltage conversion circuit and is accumulated by the charge-voltage conversion circuit regardless of the open / closed state of the switch element. That is, not only the charge generated by the photodiode but also the charge generated by the switch element is accumulated by the charge-voltage conversion circuit.
スィツチ素子のドレイン領域における接合容量は、 フォトダイォードにおける 接合容量と比べて小さいことから、 スィッチ素子で発生する電荷の量は、 フォト ダイオードで発生する電荷の量と比べて少なく、 両者の比が一定である。 したが つて、 通常の場合には、 スィッチ素子で発生する電荷の影響は小さい。  Since the junction capacitance in the drain region of the switch element is smaller than the junction capacitance in the photodiode, the amount of charge generated in the switch element is smaller than the amount of charge generated in the photodiode, and the ratio between the two is smaller. It is constant. Therefore, in the normal case, the influence of the charge generated in the switch element is small.
しかし、 1次元または 2次元の光像を撮像する光検出装置の場合には、 配列さ れるフォトダイオードの個数の増加 (高解像度化) が要求されており、 この高解 像度化に伴い、 各フォトダイオードにおける光検出面積が小さくなり接合容量が 小さくなつて、 飽和電荷量が小さくなる。 また、 高解像度化に伴い、 各電荷電圧 変換回路の入力端に接続されるスィッチ素子の個数 Nが大きくなつて、 各行の N 個のスィツチ素子の全てで発生する電荷の総量が多くなる。 これらの結果、 各電荷電圧変換回路に流入する電荷のうち、 各行の N個のスィ ツチ素子の全てで発生した電荷の総量は、 各行の N個のフォトダイォードのうち で対応するスイツチ素子が閉じている何れか 1つのフォトダイオードで発生した 電荷の量と比較して、 無視し得ないほど大きくなる。 そして、 上記のような現象 が起きると、 電荷電圧変換回路から出力される電圧出力の値が飽和し易くなり、 光検出装置で得られる M行 N列の画素からなる光像が不正確なものとなる。 この 現象をブルーミング現象と呼ぶ。 However, in the case of a photodetector that captures a one-dimensional or two-dimensional light image, an increase in the number of arranged photodiodes (higher resolution) is required. As the photodetection area of each photodiode becomes smaller and the junction capacitance becomes smaller, the saturation charge becomes smaller. Also, with the increase in resolution, the number N of switch elements connected to the input terminal of each charge-voltage conversion circuit increases, and the total amount of charges generated in all N switch elements in each row increases. As a result, of the charges flowing into each charge-to-voltage conversion circuit, the total amount of charges generated in all of the N switch elements in each row is determined by the corresponding switch element among the N photodiodes in each row. Compared to the amount of electric charge generated by any one of the photodiodes that are closed, it becomes so large that it cannot be ignored. When the above phenomenon occurs, the value of the voltage output output from the charge-to-voltage conversion circuit is likely to be saturated, and the light image composed of pixels of M rows and N columns obtained by the photodetector is inaccurate. Becomes This phenomenon is called blooming phenomenon.
本発明は、 上記問題点を解消する為になされたものであり、 ブルーミング現象 の影響を抑制して正確な入射光強度を検出することができる光検出装置および光 検出方法を提供することを目的とする。  The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a light detection device and a light detection method capable of detecting an accurate incident light intensity while suppressing the influence of a blooming phenomenon. And
本発明に係る光検出装置は、 (1) 入射した光の強度に応じた量の電荷を発生す る光検出素子と、 (2) 光検出素子で発生した電荷の出力を制御するスィッチ素子 と、 (3) 光検出素子で発生しスィッチ素子を経て到達した電荷を積分容量部に蓄 積して、 積分容量部に蓄積した電荷の量に応じた電圧出力を出力する電荷電圧変 換回路と、 (4) 光検出素子で発生する電荷が仮に飽和した場合に当該飽和電荷が 電荷電圧変換回路の積分容量部に蓄積される時刻より前に、 積分容量部における 電荷蓄積を終了させる制御手段と、 を備えることを特徴とする。  The photodetector according to the present invention comprises: (1) a photodetector that generates an amount of electric charge according to the intensity of incident light; and (2) a switch element that controls the output of the electric charge generated by the photodetector. (3) a charge-to-voltage conversion circuit that accumulates the electric charge generated by the photodetector and arrives via the switch element in the integration capacitance section, and outputs a voltage output corresponding to the amount of electric charge accumulated in the integration capacitance section; (4) control means for terminating the charge accumulation in the integration capacitance section before the time when the saturation charge is accumulated in the integration capacitance section of the charge-voltage conversion circuit when the charge generated in the photodetector is saturated. , Is provided.
この光検出装置によれば、 光検出素子に入射した光の強度に応じて発生した電 荷は、 スィッチ素子を経て電荷電圧変換回路に到達し、 電荷電圧変換回路の積分 容量部に蓄積される。 積分容量部に蓄積された電荷の量に応じた電圧出力が電荷 電圧変換回路より出力される。 そして、 積分容量部における電荷蓄積は、 制御手 段により制御されて、 光検出素子で発生する電荷が仮に飽和した場合に当該飽和 電荷が電荷電圧変換回路の積分容量部に蓄積される時刻より前に終了する。  According to this photodetector, the charge generated according to the intensity of the light incident on the photodetector reaches the charge-to-voltage conversion circuit via the switch element, and is accumulated in the integration capacitance section of the charge-to-voltage conversion circuit . A voltage output corresponding to the amount of charge stored in the integration capacitance section is output from the charge-voltage conversion circuit. The charge accumulation in the integration capacitance section is controlled by the control means, and if the charge generated in the photodetector is temporarily saturated, the charge before the time when the saturated charge is accumulated in the integration capacitance section of the charge-voltage conversion circuit is obtained. To end.
この時刻は、 スィツチ素子で発生する電荷量相当分が積分容量部に蓄積され始 める時刻に略対応する。 すなわち、 光検出素子の飽和電荷量を超えたくらいの電 荷が積分容量部に蓄積された時刻ぐらいから、 各スィツチ素子において発生した 電荷が積分容量部に蓄積され始め、 電荷電圧変換回路の出力精度に影響が与えら れるが、 本発明の装置によれば、 この時刻以前に電荷蓄積が終了する。 このよう に、 スィッチ素子による電荷蓄積が開始される前に、 積分容量部における電荷蓄 積が終了するので、 これにより、 ブルーミング現象の影響が抑制されて、 正確な 入射光強度が検出される。 This time substantially corresponds to the time at which the amount of charge generated in the switch element starts to be accumulated in the integration capacitance unit. That is, from the time when the charge exceeding the saturation charge of the photodetector was accumulated in the integration capacitor, the charge was generated in each switch element. Although the charge starts to be accumulated in the integration capacitance section, which affects the output accuracy of the charge-voltage conversion circuit, according to the device of the present invention, the charge accumulation ends before this time. As described above, since the charge accumulation in the integration capacitance section is completed before the charge accumulation by the switch element is started, the influence of the blooming phenomenon is suppressed, and the accurate incident light intensity is detected.
本発明に係る光検出装置は、 (1) スィッチ素子が閉じる時刻に飽和電荷を発生 させる飽和電荷発生手段と、 (2) 電荷電圧変換回路と同等の動作特性であって、 飽和電荷発生手段により発生させられた電荷を蓄積して、 この蓄積した電荷の量 に応じた電圧出力を出力するダミー電荷電圧変換回路と、 (3) ダミー電荷電圧変 换回路から出力される電圧出力の値と閾値とを比較して、 電圧出力の値が閾値に 達したときに、 その旨を示す飽和信号を出力する比較回路と、 を更に備えること を特徴とする。 そして、 制御手段は、 比較回路から出力される飽和信号に基づい て、 電荷電圧変換回路の積分容量部における電荷蓄積を終了させることを特徴と する。  The photodetector according to the present invention includes: (1) a saturated charge generating means for generating a saturated charge at a time when the switch element is closed; and (2) operating characteristics equivalent to those of the charge-voltage conversion circuit, A dummy charge-to-voltage converter that accumulates the generated charges and outputs a voltage output according to the amount of the accumulated charges; and (3) a voltage output value and a threshold value output from the dummy charge-to-voltage converter. And a comparison circuit that outputs a saturation signal indicating that the value of the voltage output reaches a threshold value when the voltage output value reaches a threshold value. The control means terminates the charge accumulation in the integration capacitance section of the charge-voltage conversion circuit based on the saturation signal output from the comparison circuit.
この場合には、 スィッチ素子が閉じる時刻に飽和電荷発生手段により発生させ られた飽和電荷はダミー電荷電圧変換回路により蓄積され、 この蓄積した電荷の 量に応じた電圧出力がダミー電荷電圧変換回路より出力される。 ダミー電荷電圧 変換回路から出力される電圧出力の値と閾値とは比較回路により比較され、 電圧 出力の値が閾値に達したときに、 その旨を示す飽和信号が比較回路より出力され る。 そして、 比較回路から出力される飽和信号に基づいて、 制御手段により、 電 荷電圧変換回路の積分容量部における電荷蓄積が終了させられる。 ここで、 ダミ 一電荷電圧変換回路は、 電荷電圧変換回路と同等の動作特性を有している。 した がって、 以上のようにして電荷電圧変換回路の積分容量部における電荷蓄積を終 了させることにより、 ブルーミング現象の影響が抑制されて、 正確な入射光強度 が検出される。 本発明に係る光検出方法は、 入射した光の強度に応じた量の電荷 を発生し出力する光検出素子と、 光検出素子で発生した電荷の出力を制御するス ィツチ素子と、 光検出素子で発生しスィツチ素子を経て到達した電荷を積分容量 部に蓄積して積分容量部に蓄積した電荷の量に応じた電圧出力を出力する電荷電 圧変換回路と、 を備える光検出装置を用いて、 入射した光の強度を検出する方法 であって、 光検出素子で発生する電荷が仮に飽和した場合に当該飽和電荷量が電 荷電圧変換回路の積分容量部に蓄積される時刻より前に、 積分容量部における電 荷蓄積を終了させることを特徴とする。 In this case, the saturated charge generated by the saturated charge generating means at the time when the switch element is closed is accumulated by the dummy charge-to-voltage conversion circuit, and a voltage output corresponding to the amount of the accumulated charge is output from the dummy charge-to-voltage conversion circuit. Is output. The value of the voltage output output from the dummy charge voltage conversion circuit and the threshold value are compared by the comparison circuit, and when the value of the voltage output reaches the threshold value, a saturation signal indicating that fact is output from the comparison circuit. Then, based on the saturation signal output from the comparison circuit, the control means terminates the charge accumulation in the integration capacitance section of the charge-voltage conversion circuit. Here, the dummy-to-charge-to-voltage conversion circuit has the same operating characteristics as the charge-to-voltage conversion circuit. Therefore, by terminating the charge accumulation in the integration capacitance section of the charge-voltage conversion circuit as described above, the effect of the blooming phenomenon is suppressed, and the accurate incident light intensity is detected. The photodetection method according to the present invention includes a photodetection element that generates and outputs an amount of charge corresponding to the intensity of incident light, and a scan that controls output of the charge generated by the photodetection element. A switch element, and a charge-to-voltage conversion circuit that accumulates the electric charge generated by the light detection element and arrives via the switch element in the integration capacitance section and outputs a voltage output according to the amount of electric charge accumulated in the integration capacitance section. A method for detecting the intensity of incident light using a photodetector provided with the photodetector.If the charge generated in the photodetector is temporarily saturated, the amount of the saturated charge is accumulated in the integration capacitance section of the charge-voltage conversion circuit. It is characterized in that the charge accumulation in the integration capacitance section is terminated before the time when the charge is made.
この光検出方法によれば、 光検出装置において、 光検出素子に入射した光の強 度に応じて発生した電荷は、 スィッチ素子を経て電荷電圧変換回路に到達し、 電 荷電圧変換回路の積分容量部に蓄積される。 積分容量部に蓄積された電荷の量に 応じた電圧出力が電荷電圧変換回路より出力される。 そして、 積分容量部におけ る電荷蓄積は、 光検出素子で発生する電荷が仮に飽和した場合に当該飽和電荷が 電荷電圧変換回路の積分容量部に蓄積される時刻より前に終了する。したがって、 上記と同様にスィツチ素子からの電荷相当分が積分容量部に蓄積される時刻より 前に電荷蓄積が終了するので、 これにより、 プルーミング現象の影響が抑制され て、 正確な入射光強度が検出される。  According to this photodetection method, in the photodetector, the charge generated according to the intensity of the light incident on the photodetector reaches the charge-voltage converter via the switch, and is integrated by the charge-voltage converter. It is stored in the capacity part. A voltage output corresponding to the amount of charge stored in the integration capacitance section is output from the charge-voltage conversion circuit. Then, the charge accumulation in the integration capacitance unit ends before the time when the saturation charge is accumulated in the integration capacitance unit of the charge-voltage conversion circuit when the charge generated in the photodetector is temporarily saturated. Therefore, similarly to the above, the charge accumulation is completed before the time corresponding to the charge from the switch element is accumulated in the integration capacitance portion, thereby suppressing the effect of the plumming phenomenon and reducing the accurate incident light intensity. Is detected.
図面の簡単な説明 BRIEF DESCRIPTION OF THE FIGURES
図 1は本実施形態に係る光検出装置 1の構成図である。  FIG. 1 is a configuration diagram of a photodetector 1 according to the present embodiment.
図 2 A、 図 2 Bは本実施形態に係る光検出装置 1のフォトダイオード P Dmnお よびスィツチ素子 S Wmnの説明図である。 2A and 2B are explanatory diagrams of the photodiode PD mn and the switch element SW mn of the photodetector 1 according to the present embodiment.
図 3は本実施形態に係る光検出装置 1の電荷電圧変換回路 1 1 Omの回路図で ある。 Figure 3 is a circuit diagram of a charge-voltage conversion circuit 1 1 O m of the photodetector 1 according to the present embodiment.
図 4は本実施形態に係る光検出装置 1のタイミング検知回路 3 0 0の回路図で める。  FIG. 4 is a circuit diagram of the timing detection circuit 300 of the photodetector 1 according to the present embodiment.
図 5 A、 図 5 B、 図 5 C、 図 5 D、 図 5 E、 図 5 F、 図 5 G、 図 5 Hは、 光検 出装置 1の動作を説明するタイミングチャートである。 図 6は本実施形態に係る 光検出装置 1の電荷電圧変換回路 1 1 o mの他の構成例の回路図である。 発明を実施するための最良の形態 FIGS. 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H are timing charts for explaining the operation of the light detection device 1. FIG. 6 is a circuit diagram of another configuration example of the charge-voltage conversion circuit 1 1 o m of the photodetector 1 according to the present embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 添付図面を参照して本発明の実施の形態を詳細に説明する。 なお、 図面 の説明において同一の要素には同一の符号を付し、 重複する説明を省略する。 図 1は、本実施形態に係る光検出装置 1の構成図である。この光検出装置 1は、 1つの半導体基板上に、 M個(Mは 1以上の整数)のュ-ット 1 0 (^〜丄 0 0M AZD変換回路 2 0 0、 タイミング検知回路 3 0 0および制御回路 4 0 0を備え ている。 各ュュット 1 0 0M (mは 1以上 M以下の任意の整数) は、 N個 (Nは 2 以上の整数) のフォトダイオード (光検出素子) PDML PD N個のスィッチ 素子 SW^ SW^ 電荷電圧変換回路 1 1 0Mおよびスィツチ素子 1 2 0Mを備え ている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description. FIG. 1 is a configuration diagram of a photodetector 1 according to the present embodiment. This photodetector 1 is composed of M (M is an integer of 1 or more) cuts 10 (^ to 丄 0 0 M AZD conversion circuit 200, timing detection circuit 30) on one semiconductor substrate. 0 and a control circuit 400. Each input 100 M (m is an integer of 1 or more and M or less) is N (N is an integer of 2 or more) photodiodes (photodetectors). and a PD ML PD N number of switch elements SW ^ SW ^ charge-voltage conversion circuit 1 1 0 M and Suitsuchi element 1 2 0 M.
MX N個のフォトダイォード PDU PDMNは、撮像領域に M行 N列にアレイ配 置されている。 フォトダイオード PDmnは、 第 m行第 n列に位置しており、 入射 した光の強度に応じた量の電荷を発生する。 スィッチ素子 SWMNは、 フォトダイ オード PDMNに対応していて、フォトダイォード PDMNと電荷電圧変換回路 1 1 0 mの入力端との間に設けられており、 フォトダイオード PDMNで発生した電荷の出 力を制御する。 MX N photodiode PDUs PDMN are arrayed in M rows and N columns in the imaging area. The photodiode PD mn is located at the m-th row and the n-th column, and generates an amount of electric charge according to the intensity of incident light. Switch element SW MN is compatible with photodiode PD MN, is provided between the input end of Fotodaiodo PD MN and the charge-voltage conversion circuit 1 1 0 m, generated in the photodiode PD MN Controls the output of charges.
電荷電圧変換回路 1 1 0Mの入力端は、 A 1配線 1 9 0Mにより N個のスィッチ 素子 SW^ SW^と接続されている。 電荷電圧変換回路 1 1 0Mは、 フォトダイ ォード P DMNで発生しスィツチ素子 S WMNを経て到達した電荷を積分容量部に蓄 積して、 この積分容量部に蓄積した電荷の量に応じた電圧出力を出力する。 スィッチ素子 1 2 0Mは、 電荷電圧変換回路 1 1 0Mの出力端と A/D変換回路 2 00の入力端との間に設けられている。各ュニット 1 0 0Mのスィツチ素子 1 2 0Mは、制御回路 4 0 0により制御されて順次に閉じて、電荷電圧変換回路 1 1 0 mから出力された電圧出力を A/D変換回路 2 0 0へ入力させる。 The input end of the charge-voltage conversion circuit 1 1 0 M is connected to the N switch elements SW ^ SW ^ by A 1 line 1 9 0 M. Charge-voltage converting circuit 1 1 0 M is to accumulate the charges arriving via generated in the photo die Odo PD MN Suitsuchi element SW MN in the integral capacitance part, corresponding to the amount of charge accumulated in the integral capacitance part Outputs voltage output. Switch element 1 2 0 M is provided between the input of the charge-voltage conversion circuit 1 1 0 M output terminal and the A / D converter circuit 2 00. The switch elements 120 M of each unit 100 M are controlled by the control circuit 400 and closed sequentially, and the voltage output from the charge-voltage conversion circuit 110 m is converted to the A / D conversion circuit 2. 0 Input to 0.
A/D変換回路 2 0 0は、 各ュ-ット 1 0 0RAの電荷電圧変換回路 1 1 0Mから スィッチ素子 1 2 0RAを経て順次に到達した電圧出力を入力し、この電圧出力を A ZD変換して、 デジタル出力を出力する。 タイミング検知回路 300は、 各スィ ツチ素子 SWmnの開閉タイミングを検知するための回路である。 制御回路 400 は、 タイミング検知回路 300により検知された開閉タイミングに基づいて各ス イッチ素子 SWmnの開閉を制御し、電荷電圧変換回路 11 Omにおける電荷蓄積動 作を制御し、各スィツチ素子 12 Omの開閉を制御し、 また、 AZD変換回路 20A / D conversion circuit 2 0 0, each Interview - Enter the Tsu preparative 1 0 0 RA charge-voltage conversion circuit 1 1 0 M voltage output sequentially arrive via the switch element 1 2 0 RA from, the voltage output To A Performs ZD conversion and outputs digital output. The timing detection circuit 300 is a circuit for detecting the opening / closing timing of each switch element SWmn . The control circuit 400 controls the opening and closing of the switch elements SW mn based on the closing timing detected by the timing detection circuit 300, controls the charge storage operation in the charge-voltage converting circuit 11 O m, each Suitsuchi element 12 and controlling the opening and closing of O m, also, AZD conversion circuit 20
0における AZD変換動作を制御する。 Controls the AZD conversion operation at 0.
図 2A、 図 2Bは、 本実施形態に係る光検出装置 1のフォトダイオード PDran およびスィッチ素子 SWmnの説明図であり、 図 2 Aは、 フォトダイオード PDmn およびスィツチ素子 SWmnが形成された P型半導体基板の断面を模式的し、 図 2 Bは、 フォトダイオード PDmnおよびスィッチ素子 SWmnを含む等価回路を示す。 図 2 Aに示すように、 P型半導体基板 900の表面に P型ゥエル領域 90 lmn が形成され、 この P型ゥエル領域 90:!^內に N+型不純物領域 91 lmnおよび N +型不純物領域 912mnが互いに一定間隔を隔てて形成され、 N+型不純物領域 9 1 lranおよび N+型不純物領域 912mnそれぞれの一部領域にまたがって P型半導 体基板 900の表面の絶縁膜上にゲート電極 920mnが形成されている。 P型半 導体基板 900mnの P型ゥエル領域 90 lmnと N+型不純物領域 91 lmnとの間に PN接合が形成されていて、 この PN接合によりフォトダイオード PDmnが構成 されている。 N+型不純物領域 (ソース領域) 911ran、 N+型不純物領域 (ドレ イン領域) 912mnおよびゲート電極 920mnにより、 M〇S- FET構造のスィ ツチ素子 SWmnが構成されている。 また、 N+型不純物領域 91 2mnの一部領域を 含む表面上に A 1配線 190m (寄生容量値 Cv) が形成されている。 この A 1配 線 190raは、第 m行の N個のスィッチ素子 SWml〜SWmNそれぞれの N+型不純物 領域 912 mnおよび電荷電圧変換回路 110mの入力端を電気的に接続している。 このような構成において、 N+型不純物領域 91 lran表面に光が入射すると、 P型 半導体基板 900の P型ゥエル領域 901 mnと N+型不純物領域 911 mnとの間の PN接合 (フォトダイオード PDJ において電荷が発生し、 その電荷はフォト ダイオード PDmnの PN接合容量部 Cdに蓄えられる。そして、ゲート電極 920 mnに所定の電圧が印加されると、 N+型不純物領域 (ソース領域) 91 lmnと N + 型不純物領域 (ドレイン領域) 91 2mnとの間が導通状態となり (すなわち、 ス イッチ素子 SWmnが閉じて) 、 フォトダイオード PDmnの PN接合容量部 Cdに蓄 えられていた電荷は、 N+型不純物領域 91 lmnから N+型不純物領域 912mnを 経て A 1配線 1 90mへ流れ、 電荷電圧変換回路 1 1 Omの入力端に到達する。 また、 図 2 Aから判るように、 P型半導体基板 900の P型ゥエル領域 901 mnと N+型不純物領域 (ドレイン領域) 912mnとの間にも PN接合が形成されて いて、 この PN接合によりフォトダイオードと同等のもの (以下では 「フォトダ ィオード PDdmey」 という。 ) が構成されている。 したがって、 N+型不純物領域 9 1 2mnに光が入射すると、 P型半導体基板 900の P型ゥヱル領域 90 lmnと N +型不純物領域 9 12mnとの間の P N接合 (フォトダイォード P Dd y) において 電荷が発生する。 そして、第 m行の N個のスィッチ素子 SW^ SW^それぞれに おけるフォトダイォード P Ddu で発生した電荷の全ては、スイツチ素子 S Wmnの 開閉状態に拘わらず、 A 1配線 19 Omへ流れ、 電荷電圧変換回路 1 1 Omの入力 端に到達する。 2A and 2B are explanatory diagrams of the photodiode PD ran and the switch element SW mn of the photodetector 1 according to the present embodiment. FIG. 2A shows the photodiode PD mn and the switch element SW mn formed. FIG. 2B shows an equivalent circuit including a photodiode PD mn and a switch element SW mn , schematically showing a cross section of a P-type semiconductor substrate. As shown in FIG. 2 A, P-type Ueru region 90 l mn on the surface of the P-type semiconductor substrate 900 is formed, the P-type Ueru region 90 :! On the other hand, an N + type impurity region 91 l mn and an N + type impurity region 912 mn are formed at a certain interval from each other, and extend over a part of each of the N + type impurity region 91 l ran and the N + type impurity region 912 mn. Thus, a gate electrode 920 mn is formed on the insulating film on the surface of the P-type semiconductor substrate 900. And PN junctions are formed between the P-type semi-conductor substrate 900 mn of P-type Ueru region 90 l mn and the N + -type impurity regions 91 l mn, photodiode PD mn is formed by the PN junction. The N + type impurity region (source region) 911 ran , the N + type impurity region (drain region) 912 mn and the gate electrode 920 mn constitute a switch element SW mn having an M〇S-FET structure. Further, 190 m of A1 wiring (parasitic capacitance value Cv) is formed on the surface including a part of N + type impurity region 912 mn . The A1 wiring 190 ra electrically connects the N + type impurity region 912 mn of each of the N switch elements SW ml to SW mN in the m-th row and the input terminal of the charge-voltage conversion circuit 110 m . In such a configuration, when light is incident on the N + -type impurity regions 91 l ran surface, PN junction between the P-type Ueru region 901 mn and the N + -type impurity regions 911 mn of P-type semiconductor substrate 900 (in the photodiode PDJ Charge is generated and the charge Stored in the PN junction capacitance Cd of the diode PD mn . When a predetermined voltage is applied to the gate electrode 920 mn , a conduction state is established between the N + -type impurity region (source region) 91 l mn and the N + -type impurity region (drain region) 921 mn (ie, When the switch element SW mn is closed), the charge stored in the PN junction capacitance Cd of the photodiode PD mn is transferred from the N + type impurity region 91 lmn to the N + type impurity region 912 mn through the A1 wiring 190 It flows into m, and reaches the input end of the charge-voltage conversion circuit 1 1 O m. As can be seen from FIG. 2A, a PN junction is also formed between the P-type well region 901 mn and the N + -type impurity region (drain region) 912 mn of the P-type semiconductor substrate 900. A photodiode equivalent (hereinafter referred to as “photodiode PD dmey ”) is configured. Accordingly, N + -type When light is incident on the impurity region 9 1 2 mn, P-type PN junction between the P-type Uweru region 90 l mn and the N + -type impurity region 9 12 mn of the semiconductor substrate 900 (Fotodaiodo PD dy ), A charge is generated. Then, all the charges generated by the photodiode PD du in each of the N switch elements SW ^ SW ^ in the m-th row flow to the A1 wiring 19 O m irrespective of the open / closed state of the switch element SW mn. Reaches the input terminal of the charge-voltage conversion circuit 11 Om.
図 3は、本実施形態に係る光検出装置 1の電荷電圧変換回路 1 1 Oraの回路図で ある。 各電荷電圧変換回路 1 1 omは、 アンプ 1 1 1、 容量素子 (積分容量部) 1 1 2およびスィッチ素子 1 1 3を含む。 アンプ 1 1 1の反転入力端子は、 A 1配 線 1 9 Omを介して、 第 m行の N個のスィッチ素子 SW^ SW^それぞれの N + 型不純物領域 (ドレイン領域) 91 2 mnと接続されている。 また、 アンプ 1 1 1 の反転入力端子と出力端子との間に容量素子 1 12およびスィッチ素子 1 1 3が 並列的に設けられている。 アンプ 1 1 1の非反転入力端子には基準電圧値 Vref が供給される。この電荷電圧変換回路 1 1 Oraは、スィッチ素子 1 1 3が閉じると、 容量素子 1 12が放電され、 出力端より出力される電圧出力が初期化される。 一 方、 この電荷電圧変換回路 1 1 Omは、 スィツチ素子 1 13が開いていると、入力 端に流入した電荷を容量素子 1 12に蓄積して、 この蓄積した電荷の量に応じた 電圧出力を出力端より出力する。 FIG. 3 is a circuit diagram of the charge-voltage conversion circuit 11 Ora of the photodetector 1 according to the present embodiment. Each charge-voltage converting circuit 1 1 o m includes an amplifier 1 1 1, the capacitor (the integral capacitance part) 1 1 2 and switch element 1 1 3. The inverting input terminal of the amplifier 111 is connected to the N + -type impurity region (drain region) 91 2 mn of each of the N switch elements SW ^ SW ^ in the m-th row via the A 1 line 19 O m. It is connected. Further, a capacitive element 112 and a switch element 113 are provided in parallel between the inverting input terminal and the output terminal of the amplifier 111. The reference voltage Vref is supplied to the non-inverting input terminal of the amplifier 111. The charge-voltage conversion circuit 1 1 O ra, when the switch element 1 1 3 closes, the capacitor element 1 12 is discharged, the voltage output is outputted from the output is initialized. Hand, the charge-voltage conversion circuit 1 1 O m, when Suitsuchi element 1 13 is open, the input The charge that has flowed into the terminal is stored in the capacitor 112, and a voltage output corresponding to the amount of the stored charge is output from the output terminal.
電荷電圧変換回路 1 1 Omのスィッチ素子 1 1 3が開いた時刻から時間 tだけ 経過した時刻 tにおいて、第 m行の N個のスィツチ素子 SWml〜SW„i(のうち第 n 列にあるスィッチ素子 SWmnのみが閉じているとすると、 この時刻 tにおいて電 荷電圧変換回路 1 1 Omの容量素子 1 1 2に蓄積されている電荷の量 Qは、以下の 式で表される。 At time t when the time t has elapsed from the time when the switch element 1 13 of the charge-voltage conversion circuit 1 1 O m is opened, the N switch elements SW ml to SW „ i in the m-th row ( in the n-th column). When only certain switch element SW mn is closed, the amount Q of electric charge accumulated in the capacitor element 1 1 2 of the load voltage conversion circuit 1 1 O m conductive at time t is expressed by the following formula .
Q = Qmn+ I d- t …ひ) Q = Q mn + I d- t ... h)
また、この時刻 tにおいて電荷電圧変換回路 1 1 omの出力端から出力される電 圧出力の値 Vは、 以下の式で表される。 The value V of voltage output that is output from the output terminal of the charge-voltage conversion circuit 1 1 o m at time t is expressed by the following equation.
V = Q/Cf  V = Q / Cf
= (Qm+ Id- t)/C112 -(2) = (Q m + Id- t) / C 112 - (2)
ここで、 Qmnは、 第 m行の N個のフォトダイオード PDml〜PDrtのうち、 閉じ ているスィッチ素子 S Wmnに対応するフォトダイオード P D„から流入した電荷 の量を示す。 1(1は、 第111行の]^個のスィッチ素子3 „1〜3 それぞれにぉけ るフォトダイオード P D dumyで単位時間当たりに発生する電荷の総量 (すなわち 電流) を示す。 また、 C112は容量素子 1 1 2の容量値である。 Here, Q mn indicates the amount of charge flowing from the photodiode PD „corresponding to the closed switch element SW mn among the N photodiodes PD ml to PD rt in the m-th row. shows the total amount of the first 111 rows of] ^ number of switch element 3 "1-3 respectively generated per unit time in Oke Ru photodiode PD DUMY charge (or current). Further, C 112 is the capacitance element This is the capacitance value of 1 1 2.
図 4は、 本実施形態に係る光検出装置 1のタイミング検知回路 300の回路図 である。 このタイミング検知回路 300は、 電荷電圧変換回路 310、 容量素子 320、 比較回路 330および Dラッチ回路 340を含む。  FIG. 4 is a circuit diagram of the timing detection circuit 300 of the photodetector 1 according to the present embodiment. The timing detection circuit 300 includes a charge-voltage conversion circuit 310, a capacitance element 320, a comparison circuit 330, and a D latch circuit 340.
タイミング検知回路 300の電荷電圧変換回路 310は、 各ュニット 10 Om の電荷電圧変換回路 1 1 Oraと同等の動作特性のものであって、アンプ 1 1 1と同 等のアンプ 31 1、 容量素子 1 12と同等の容量素子 312、 および、 スィツチ 素子 1 1 3と同等のスィツチ素子 3 1 3を有している。 アンプ 311の反転入力 端子は、 A 1配線 390を介して容量素子 320と接続されている。 また、 アン プ 3 1 1の反転入力端子と出力端子との間に容量素子 3 12およびスィッチ素子 3 1 3が並列的に設けられている。 アンプ 3 1 1の非反転入力端子には基準電圧 値 Vref が供給される。 この電荷電圧変換回路 3 1 0は、 スィッチ素子 3 1 3が 閉じると、 容量素子 3 1 2が放電され、 出力端より出力される電圧出力が初期化 される。 一方、 この電荷電圧変換回路 3 1 0は、 スィッチ素子 3 1 3が開いてい ると、 入力端に流入した電荷を容量素子 3 1 2に蓄積して、 この蓄積した電荷の 量に応じた電圧出力を出力端より出力する。 Charge-voltage converting circuit 310 of the timing detection circuit 300 has been made in view of the charge-voltage conversion circuit 1 1 O ra equivalent operating characteristics of each Yunitto 10 O m, amplifier 1 1 1 and the amplifier 31 1 of the same, etc., the capacity It has a capacitive element 312 equivalent to the element 112 and a switch element 313 equivalent to the switch element 113. The inverting input terminal of the amplifier 311 is connected to the capacitive element 320 via the A1 wiring 390. A capacitor 312 and a switch element are connected between the inverting input terminal and the output terminal of the amplifier 311. 3 1 3 are provided in parallel. The reference voltage Vref is supplied to the non-inverting input terminal of the amplifier 311. In the charge-voltage conversion circuit 310, when the switch element 313 is closed, the capacitance element 312 is discharged, and the voltage output output from the output terminal is initialized. On the other hand, when the switch element 313 is open, the charge-to-voltage conversion circuit 310 accumulates the electric charge flowing into the input terminal into the capacitive element 312, and generates a voltage corresponding to the amount of the accumulated electric charge. Output from the output terminal.
容量素子 3 2 0は、 一方の端子が A 1配線 3 9 0を介して電荷電圧変換回路 3 1ひの入力端と接続されており、他方の端子が制御回路 4 0 0に接続されている。 制御回路 4 0 0より容量素子 3 2 0へ印加されている電圧値が Δ Vだけ低下す ると、 電荷電圧変換回路 3 1 0の入力端の入力端には A V ' C32。だけの電荷が流 入する。 ここで、 C 32。は容量素子 3 2 0の容量値である。 上記電荷量 A V ' C320 は、 各フォトダイオード P Dmnにおける飽和電荷量と等しくされる。 また、 タイ ミング検知回路 3 0 0の A 1配線 3 9 0の寄生容量値は、各ュニット 1 0 O raの A 1配線 1 9 O mの寄生容量値 Cvと等しくされている。電荷電圧変換回路 3 1 0の 容量素子 3 1 2に蓄積されていく電荷の量は、 A 1配線 3 9 0の寄生容量値 Cv、 容量素子 3 2 0の容量値 C32。、 および、 アンプ 3 2 0の帯域により定まる時定数 に従って増加していき、 やがて飽和電荷量 A V - C32()となる。 すなわち、 容量素 子 3 2 0は、制御回路 4 0 0より印加されている電圧値が Δ νだけ低下すること により飽和電荷を発生させる飽和電荷発生手段として作用する。 One terminal of the capacitive element 320 is connected to the input terminal of the charge-voltage conversion circuit 31 via the A1 wiring 390, and the other terminal is connected to the control circuit 400. . When the value of the voltage applied to the capacitive element 320 from the control circuit 400 decreases by ΔV, AV′C 32 is input to the input terminal of the charge-voltage conversion circuit 310 . Only charge flows in. Where C 32 . Is the capacitance value of the capacitor 320. The charge amount AV′C 320 is made equal to the saturation charge amount in each photodiode PD mn . Further, the parasitic capacitance of the A 1 line 3 9 0 timing detection circuit 3 0 0 is equal to the parasitic capacitance value Cv of the A 1 line 1 9 O m of each Yunitto 1 0 O ra. The amount of charge accumulated in the capacitance element 312 of the charge-voltage conversion circuit 310 is represented by the parasitic capacitance value Cv of the A1 wiring 390 and the capacitance value C32 of the capacitance element 320 . , And increases according to the time constant determined by the band of the amplifier 320 , and eventually reaches the saturated charge amount AV- C32 () . That is, the capacitive element 320 acts as a saturated charge generating means for generating a saturated charge when the voltage value applied from the control circuit 400 decreases by Δν.
比較回路 3 3 0は、 電荷電圧変換回路 3 1 0から出力された電圧出力を反転入 力端子に入力し、 閾値電圧 Vthを非反転入力端子に入力する。 そして、 比較回路 3 3 0は、電圧出力値が閾値電圧 Vthより小さいときには論理値 Hの論理出力を 出力し、電圧出力値が閾値電圧 Vthより大きいときには論理値 Lの論理出力を出 力する。 閾値電圧 Vthは、 容量素子 3 1 2に飽和電荷量 A V . C32。の電荷が蓄積 されたときに電荷電圧変換回路 3 1 0の出力端より出力される電圧出力の値より 幾らか小さい値に設定される。 したがって、 電荷電圧変換回路 3 1 0の容量素子 3 1 2における電荷蓄積が飽和する時刻より幾らか早い時刻に、 比較回路 3 3 0 の出力端より出力される論理出力(飽和信号)は論理値 Hから論理値 Lに転じる。 The comparison circuit 330 inputs the voltage output output from the charge-voltage conversion circuit 310 to the inverting input terminal, and inputs the threshold voltage Vth to the non-inverting input terminal. Then, the comparison circuit 330 outputs a logical output of a logical value H when the voltage output value is smaller than the threshold voltage Vth, and outputs a logical output of a logical value L when the voltage output value is larger than the threshold voltage Vth. The threshold voltage Vth is the saturation charge AV.C 32 in the capacitor 312. Is set to a value that is somewhat smaller than the value of the voltage output output from the output terminal of the charge-voltage conversion circuit 310 when the charge of the charge is accumulated. Therefore, the capacitance element of the charge-voltage conversion circuit 310 The logic output (saturation signal) output from the output terminal of the comparison circuit 330 changes from the logical value H to the logical value L at a time slightly earlier than the time at which the charge accumulation in 312 is saturated.
Dラッチ回路 3 4 0は、 比較回路 3 3 0より出力される論理出力 (飽和信号) を C 1 r端子に入力し、 制御回路 4 0 0より容量素子 3 2 0へ印加される電圧値 を C 1 k端子に入力し、電源電圧値 Vddを D端子に入力する。 Dラッチ回路 3 4 0は、 C I r端子に入力する論理値が Lであれば、 Q端子より論理値 Lを出力す る。 一方、 Dラッチ回路 3 4 0は、 C I r端子に入力する論理値が Hであれば、 C 1 k端子に入力する電圧値が立ち下がるタイミングで、 D端子に入力する論理 値をラッチして Q端子より出力する。  The D latch circuit 340 inputs the logical output (saturation signal) output from the comparison circuit 330 to the C1r terminal, and determines the voltage value applied to the capacitive element 320 from the control circuit 400. C 1 Input to the k terminal and supply voltage Vdd to the D terminal. If the logical value input to the C Ir terminal is L, the D latch circuit 340 outputs a logical value L from the Q terminal. On the other hand, if the logical value input to the CI r terminal is H, the D latch circuit 340 latches the logical value input to the D terminal at the timing when the voltage value input to the C 1 k terminal falls. Output from Q terminal.
したがって、制御回路 4 0 0より容量素子 3 2 0へ印加されている電圧値が Δ Therefore, the voltage value applied to the capacitive element 320 from the control circuit 400 becomes Δ
Vだけ低下する時刻より前は、 Dラッチ回路 3 4 0の Q端子より論理値 Lが出力 されており、制御回路 4 0 0より容量素子 3 2 0へ印加されている電圧値が Δ V だけ低下した時刻には、 比較回路 3 3 0より C 1 r端子に入力する論理出力は論 理値 Hであるので、 この時刻以降、 Dラッチ回路 3 4 0の Q端子より論理値 Hが 出力される。 その後、 比較回路 3 3 0より C 1 r端子に入力する論理出力が論理 値 Lに転じると、 この時刻以降、 Dラッチ回路 3 4 0の Q端子より論理値 Lが出 力される。 Before the time when the voltage drops by V, the logical value L is output from the Q terminal of the D latch circuit 340, and the voltage applied to the capacitive element 320 from the control circuit 400 is ΔV only. At the time of the drop, the logical output input to the C 1 r terminal from the comparison circuit 330 is the logical value H, and after this time, the logical value H is output from the Q terminal of the D latch circuit 340. You. Thereafter, when the logic output input to the C1r terminal from the comparison circuit 330 changes to a logic value L, the logic value L is output from the Q terminal of the D latch circuit 340 after this time.
以上のように構成されるタイミング検知回路 3 0 0の Dラッチ回路 3 4 0の Q 端子より出力される論理出力は、 各スィツチ素子 SWmnの開閉タイミングを示す ものである。 制御回路 4 0 0は、 所定のタイミングでタイミング検知回路 3 0 0 の容量素子 3 2 0 へ印加する電圧値を変化させ、 タイミング検知回路 3 0 0の D ラッチ回路 3 4 0の Q端子より出力される論理出力を入力する。 そして、 制御回 路 4 0 0は、 タイミング検知回路 3 0 0から出力された論理出力に基づいて各ス イッチ素子 S Wmnの開閉を制御し、電荷電圧変換回路 1 1 0mにおける電荷蓄積動 作を制御し、各スィツチ素子 1 2 0 mの開閉を制御し、 また、 AZD変換回路 2 0 0における AZD変換動作を制御する。 次に、 本実施形態に係る光検出装置 1の動作について説明するとともに、 本実 施形態に係る光検出方法について説明する。 以下の動作は、 制御回路 400によ る制御に基づいて行われる。 M個のュ-ット 10 (^〜丄 00Mは同一タイミング で並列動作する。 各ュニット 100raでは、 N個のスィツチ素子 SWml〜SWmNそ れぞれが順次に閉じて、 N個のフォトダイオード PD^ PD^それぞれにおいて 光入射に伴い発生した電荷が順次に A 1配線 1 90raを経て電荷電圧変換回路 1 1 omに入力する。 The logical output output from the Q terminal of the D latch circuit 340 of the timing detection circuit 300 configured as described above indicates the opening / closing timing of each switch element SW mn . The control circuit 400 changes the voltage value applied to the capacitive element 320 of the timing detection circuit 300 at a predetermined timing, and outputs the voltage from the Q terminal of the D latch circuit 340 of the timing detection circuit 300. Input logical output. Then, the control circuitry 4 0 0 controls the opening and closing of the switch elements SW mn based on a logical output which is output from the timing detection circuit 3 0 0, the charge storage operation in the charge-voltage conversion circuit 1 1 0 m To control the opening and closing of each switch element 120 m , and the AZD conversion operation in the AZD conversion circuit 200. Next, the operation of the light detection device 1 according to the present embodiment will be described, and the light detection method according to the present embodiment will be described. The following operation is performed based on the control by the control circuit 400. M units 10 (^ to 丄 00 M operate in parallel at the same timing. In each unit 100 ra , N switch elements SW ml to SW mN are closed in order, and N units In each of the photodiodes PD ^ PD ^, the charges generated due to the incidence of light are sequentially input to the charge-voltage conversion circuit 11 1 o m via the A 1 wiring 190 ra .
図 5A、 図 5 B、 図 5 C、 図 5D、 図 5 E、 図 5 F、 図 5 G、 図 5Hは、 本実 施形態に係る光検出装置 1の動作を説明するタイミングチヤ一トである。 この図 では、 第 m行第 11列に位置するフォトダイオード PDmnにおいて光入射に伴い発 生した電荷が電荷電圧変換回路 1 1 oraに入力する場合について説明する。 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H are timing charts for explaining the operation of the photodetector 1 according to the present embodiment. is there. In this figure, a case will be described in which a charge generated by light incidence in the photodiode PD mn located in the m-th row and the eleventh column is input to the charge-voltage conversion circuit 11ora .
時刻 tOに、電荷電圧変換回路 1 10„のスィッチ素子 1 1 3が閉じて(図 5A)、 容量素子 1 1 2が放電され、電荷電圧変換回路 1 10mから出力される電圧出力の 値がリセットレベルとなる (図 5H) 。 電荷電圧変換回路 310のスィッチ素子 31 3が閉じて (図 5 B) 、 容量素子 312が放電され、 電荷電圧変換回路 31At time tO, closes switch element 1 1 3 of the charge-voltage conversion circuit 1 10 "(FIG. 5A), the capacitive element 1 1 2 is discharged, the value of the voltage output that is output from the charge-voltage conversion circuit 1 10 m The reset level is reached (Fig. 5H) .The switch element 313 of the charge-voltage conversion circuit 310 is closed (Fig. 5B), and the capacitance element 312 is discharged.
0から出力される電圧出力の値がリセットレベルとなる (図 5D) 。 この時刻で は、 N個のスィッチ素子 SW^ SW^は開いている (図 5G) 。 また、 制御回路 400よりタイミング検知回路 300の容量素子 320に所定の電圧値が供給さ れる (図 5 C) 。 そして、 比較回路 330から出力される論理出力は論理値 Hに なり (図 5 E) 、 Dラッチ回路 340の Q端子から出力される論理出力は論理値 Lである) 図 5 F) 。 The voltage output value output from 0 becomes the reset level (Fig. 5D). At this time, the N switch elements SW ^ SW ^ are open (Fig. 5G). Further, a predetermined voltage value is supplied from the control circuit 400 to the capacitive element 320 of the timing detection circuit 300 (FIG. 5C). Then, the logical output output from the comparison circuit 330 becomes a logical value H (FIG. 5E), and the logical output output from the Q terminal of the D latch circuit 340 is a logical value L) (FIG. 5F).
時刻 tlに、電荷電圧変換回路 1 10 のスィッチ素子 1 1 3が開いて(図 5A)、 電荷電圧変換回路 1 10mの容量素子 1 12における電荷の蓄積が可能な状態と なる。 At time tl, the switch element 113 of the charge-voltage conversion circuit 110 is opened (FIG. 5A), and the charge can be accumulated in the capacitance element 112 of the charge-voltage conversion circuit 110 m .
また、 電荷電圧変換回路 3 10のスィッチ素子 31 3が開いて (図 5 B) 、 電 荷電圧変換回路 3 10の容量素子 31 2における電荷の蓄積が可能な状態となる。 時刻 t2に、 N個のスィツチ素子 SWml〜SWmNのうちの 1つのスィツチ素子 S Wranのみが閉じる (図 5G) 。 また、 制御回路 400よりタイミング検知回路 3 00の容量素子 320に供給される電圧値が AVだけ低下する (図 5 C) 。 これ により、 Dラッチ回路 340の Q端子から出力される論理出力は論理値 Hに転じ る (図 5 F) 。 また、 飽和電荷量 Δ V· C32。が電荷電圧変換回路 310の入力端 に流入していき容量素子 3 1 2に蓄積されていく。 容量素子 3 12に蓄積されて いく電荷の量は、 時定数に従って増加していき、 やがて飽和電荷量 Δ V*C32。と なる。したがって、電荷電圧変換回路 310の出力端から出力される電圧出力も、 次第に増加していき、 やがて飽和値となる (図 5D) 。 In addition, the switch element 313 of the charge-voltage conversion circuit 310 is opened (FIG. 5B), and the charge is stored in the capacitance element 312 of the charge-voltage conversion circuit 310. At time t2, only one Suitsuchi elements SW ran of the N Suitsuchi element SW ml to SW mN is closed (FIG. 5G). Further, the voltage value supplied from the control circuit 400 to the capacitive element 320 of the timing detection circuit 300 decreases by AV (FIG. 5C). As a result, the logical output output from the Q terminal of the D latch circuit 340 changes to the logical value H (FIG. 5F). Also, the saturation charge ΔV · C32 . Flows into the input terminal of the charge-voltage conversion circuit 310 and is accumulated in the capacitive element 312. The amount of charge accumulated in the capacitor 312 increases according to the time constant, and eventually reaches the saturated charge amount ΔV * C 32 . And Therefore, the voltage output output from the output terminal of the charge-voltage conversion circuit 310 also gradually increases, and eventually reaches a saturation value (FIG. 5D).
時刻 t3に、 電荷電圧変換回路 310の出力端から出力される電圧出力の値が 閾値電圧 Vthに達すると (図 5D) 、 比較回路 330から出力される論理出力は 論理値 Lに転じ (図 5 E) 、 Dラッチ回路 340の Q端子から出力される論理出 力も論理値 Lに転じる (図 5 F) 。 そして、 この論理出力が論理値 Lに転じたこ とを認、識した制御回路 400により制御されてスイツチ素子 S Wranが開き( 5 G)、 電荷電圧変換回路 1 1 Omの容量素子 1 12における電荷の蓄積が終了する。 At time t3, when the value of the voltage output output from the output terminal of the charge-voltage conversion circuit 310 reaches the threshold voltage Vth (FIG. 5D), the logic output output from the comparison circuit 330 changes to a logic value L (FIG. 5). E), the logical output output from the Q terminal of the D latch circuit 340 also changes to the logical value L (FIG. 5F). Then, sure that you this logical output is turned to a logical value L, is controlled by the identification and control circuit 400 opens switch element SW ran (5 G), the capacitive element 1 12 of the charge-voltage conversion circuit 1 1 O m The accumulation of the charge ends.
本実施形態では、各電荷電圧変換回路 1 10mおよび電荷電圧変換回路 310は 互いに同等の動作特性を有していて、また、 A 1配線 1 90mおよび A 1配線 39 0それぞれの寄生容量値が互いに同一である。 したがって、 フォトダイオード P Dmnで発生した電荷が飽和電荷量であっても、 その飽和電荷が電荷電圧変換回路 1 1 Omの容量素子 1 1 2に蓄積される時刻より前に電荷蓄積が終了する。 また、 この時刻は、 積分容量部の容量素子 1 12における電荷蓄積は、 制御手段により 制御され、 フォトダイオード PDmnで発生する電荷が仮に飽和した場合に当該飽 和電荷が電荷電圧変換回路の積分容量部に蓄積される時刻に略対応する。 すなわ ち、 この時刻は、 スィッチ素子 SWmnで発生する電荷量相当分が積分容量部の容 量素子 11 2に蓄積され始める時刻に略対応する。 すなわち、 フォトダイオード PDの飽和電荷量を超えたくらいの電荷が容量素子 1 1 2に蓄積された時刻ぐら いから、各スィッチ素子 S Wmnにおいて発生した電荷が容量素子 1 1 2に蓄積さ れ始め、 電荷電圧変換回路 1 1 O mの出力精度に影響が与えられるが、 本装置に よれば、 この時刻以前に電荷蓄積が終了する。 このように、 スィッチ素子 S Wm n による電荷蓄積が開始される前に、 容量素子 1 1 2における電荷蓄積が終了する ので、 これにより、 ブルーミング現象の影響が抑制されて、 正確な入射光強度が 検出される。 In the present embodiment, each of the charge-voltage conversion circuit 110 m and the charge-voltage conversion circuit 310 have the same operating characteristics as each other, and the parasitic capacitance value of each of the A1 wiring 190 m and the A1 wiring 390 Are the same as each other. Therefore, charges generated in the photodiode PD mn is be saturated charge amount, the charge storage prior to time accumulated saturation charge in the capacitor 1 1 2 of the charge-voltage conversion circuit 1 1 O m is completed . At this time, the charge accumulation in the capacitive element 112 of the integration capacitance section is controlled by the control means, and if the charge generated in the photodiode PD mn is temporarily saturated, the saturated charge is integrated by the charge-voltage conversion circuit. It roughly corresponds to the time stored in the capacity unit. That is, this time substantially corresponds to the time when the amount of charge generated in the switch element SWmn starts to be accumulated in the capacitance element 112 of the integration capacitance section. In other words, around the time when the charge exceeding the saturation charge of the photodiode PD is accumulated in the capacitor 1 1 2 Good to, charges generated in each switch element SW mn begins to be accumulated in the capacitor 1 1 2, is given effect in the output accuracy of the charge-voltage conversion circuit 1 1 O m, according to the present device, this time The charge accumulation ends before. As described above, since the charge accumulation in the capacitive elements 112 ends before the charge accumulation by the switch element SWmn starts, the influence of the blooming phenomenon is suppressed, and the accurate incident light intensity is detected. Is done.
これにより、 プルーミング現象の影響が抑制されて、 正確な入射光強度が検出 される。 なお、電荷電圧変換回路 1 1 O mのスィッチ素子 1 1 3が開いている期間 (時亥 U t l以降) は、 第 m行の N個のスィッチ素子 S W^ S W^それぞれにおけ るフォトダイオード P Ddu yで発生する電荷の総て (上記(1)式の右辺第 2項) も 電荷電圧変換回路 1 1 O mの容量素子 1 1 2に蓄積される力 S、この電荷総量も考慮 して閾値電圧 Vthは適切に設定される。 As a result, the influence of the plumming phenomenon is suppressed, and an accurate incident light intensity is detected. Note that the charge-voltage conversion circuit 1 1 O period the switch element 1 1 3 open the m (Tokii U tl later), N number of switch elements of the m rows SW ^ SW ^ photodiode PD that put each All of the charges generated by du y (the second term on the right side of the above equation (1)) also take into account the force S accumulated in the capacitor 1 1 2 of the charge-voltage conversion circuit 1 1 O m and the total amount of this charge. The threshold voltage Vth is set appropriately.
また、 本実施形態では、 M個のュニット 1 0 (^〜丄 0 0 Mおよびタイミング検 知回路 3 0 0が 1つの半導体基板上に設けられているので、 各電荷電圧変換回路 1 1 O mおよび電荷電圧変換回路 3 1 0それぞれの設計を同一のものとすれば、製 造プロセスが安定していなくても、各電荷電圧変換回路 1 1 omおよび電荷電圧変 換回路 3 1 0それぞれの動作特性も同一のものとなる。 Further, in this embodiment, since the M units 10 (^ to 丄 00 M and the timing detection circuit 300 are provided on one semiconductor substrate, each charge-voltage conversion circuit 11 O m and if the charge-voltage converting circuit 3 1 0 each design and the same thing, manufacturing process is stabilized even if no, the charge-voltage conversion circuit 1 1 o m and charge voltage conversion circuitry 3 1 0, respectively The operating characteristics are also the same.
本発明は、上記実施形態に限定されるものではなく、種々の変形が可能である。 例えば、 タイミング検知回路 3 0 0を設けることなく、 スィッチ素子 S Wmnの開 閉タイミングを制御する制御信号を外部より光検出装置 1に与えてもよい。 この 場合、 強度が強い光を光検出装置 1に入射させたときにブルーミング現象の影響 が抑制される期間だけスィッチ素子 s wmnを閉じる。 The present invention is not limited to the above embodiment, and various modifications are possible. For example, without providing the timing detection circuit 300 , a control signal for controlling the opening / closing timing of the switch element SWmn may be externally provided to the photodetector 1. In this case, the switch element sw mn is closed only during the period in which the effect of the blooming phenomenon is suppressed when the light with high intensity is incident on the photodetector 1.
また、 電荷電圧変換回路 1 1 O mは、 図 6に示すような構成であってもよい。 この図に示す電荷電圧変換回路 1 1 0 raは、 アンプ 1 1 1、 容量素子 1 1 2 i l 1 24およびスィッチ素子 1 1 3 1 1 34を含む。 アンプ 1 1 1の反転入力端子 と出力端子との間に、 容量素子 1 1 2 互いに直列接続された容量素子 1 1 22 およびスィッチ素子 1 1 32、 互いに直列接続された容量素子 1 1 23およびスィ ツチ素子 1 1 33、 互いに直列接続された容量素子 1 1 24およびスィッチ素子 1 1 34、 ならびに、 スィッチ素子 1 1 3 iが並列的に設けられている。 この電荷電 圧変換回路 1 1 0mの積分容量部の容量値は、 スィッチ素子 1 1 32〜1 1 34それ ぞれの開閉状態に応じて決定される。 このようにすることで、 積分容量部の容量 値は、 入射光強度に応じて適切に設定され得る。 The charge-voltage conversion circuit 1 1 O m may be configured as shown in FIG. The charge voltage shown in FIG conversion circuit 1 1 0 ra comprises an amplifier 1 1 1, capacitor element 1 1 2 il 1 2 4 and switch element 1 1 3 1 1 3 4. Amplifier 1 1 between the first inverting input terminal and the output terminal, the capacitive element 1 1 2 serially connected capacitance element 1 1 2 2 mutually And switch element 1 1 3 2, capacitor element 1 1 2 3 and sweep rate Tutsi element 1 1 3 3 connected in series with each other, the capacitive element 1 1 2 4 and switch element 1 1 3 4 connected in series with each other, as well as switch Elements 113 i are provided in parallel. The capacitance value of the integral capacitance part of the charge-voltage conversion circuit 1 1 0 m is determined according to the switch device 1 1 3 2-1 1 3 4 closed state of their respective. By doing so, the capacitance value of the integration capacitance section can be appropriately set according to the incident light intensity.
産業上の利用可能性 Industrial applicability
本発明は、 入射した光の強度を検出する装置および方法に利用することができ る。  INDUSTRIAL APPLICABILITY The present invention can be used for an apparatus and a method for detecting the intensity of incident light.

Claims

請求の範面 Claim aspects
1 . 入射した光の強度に応じた量の電荷を発生する光検出素子と、 前記光検出素子で発生した電荷の出力を制御するスィッチ素子と、  1. A photodetector that generates an amount of electric charge according to the intensity of incident light, and a switch element that controls the output of the electric charge generated by the photodetector,
前記光検出素子で発生し前記スィツチ素子を経て到達した電荷を積分容量部に 蓄積して、 前記積分容量部に蓄積した電荷の量に応じた電圧出力を出力する電荷 電圧変換回路と、  A charge-to-voltage conversion circuit that accumulates charge generated by the light detection element and arrives via the switch element in the integration capacitance unit, and outputs a voltage output according to the amount of charge accumulated in the integration capacitance unit;
前記光検出素子で発生する電荷が仮に飽和した場合に当該飽和電荷が前記電荷 電圧変換回路の前記積分容量部に蓄積される時刻より前に、 前記積分容量部にお ける電荷蓄積を終了させる制御手段と、  A control for ending the charge accumulation in the integration capacitance section before the time when the charge generated in the photodetector is temporarily saturated and before the saturation charge is accumulated in the integration capacitance section of the charge-voltage conversion circuit. Means,
を備えることを特徴とする光検出装置。  A light detection device comprising:
2 . 前記スィツチ素子が閉じる時刻に前記飽和電荷を発生させる飽和 電荷発生手段と、  2. Saturated charge generation means for generating the saturated charge at a time when the switch element closes;
前記電荷電圧変換回路と同等の動作特性であって、 前記飽和電荷努生手段によ り発生させられた電荷を蓄積して、 この蓄積した電荷の量に応じた電圧出力を出 力するダミ一電荷電圧変換回路と、  A dummy circuit that has an operating characteristic equivalent to that of the charge-to-voltage conversion circuit, stores the charge generated by the saturation charge storage unit, and outputs a voltage output corresponding to the amount of the stored charge. A charge-voltage conversion circuit,
前記ダミ一電荷電圧変換回路から出力される電圧出力の値と閾値とを比較して、 前記電圧出力の値が前記閾値に達したときに、 その旨を示す飽和信号を出力する 比較回路と、  A comparison circuit that compares a value of a voltage output output from the dummy charge-voltage converter with a threshold value, and outputs a saturation signal indicating that when the value of the voltage output reaches the threshold value;
を更に備え、  Further comprising
前記制御手段は、 前記比較回路から出力される飽和信号に基づいて、 前記電荷 電圧変換回路の前記積分容量部における電荷蓄積を終了させることを特徴とする 請求の範囲第 1項に記載の光検出装置。  The light detection device according to claim 1, wherein the control unit terminates charge accumulation in the integration capacitance unit of the charge-voltage conversion circuit based on a saturation signal output from the comparison circuit. apparatus.
3 . 入射した光の強度に応じた量の電荷を発生し出力する光検出素子 と、 前記光検出素子で発生した電荷の出力を制御するスィッチ素子と、 前記光検 出素子で発生し前記スィツチ素子を経て到達した電荷を積分容量部に蓄積して前 記積分容量部に蓄積した電荷の量に応じた電圧出力を出力する電荷電圧変換回路 と、 を備える光検出装置を用いて、 入射した光の強度を検出する方法であって、 前記光検出素子で発生する電荷が仮に飽和した場合に当該飽和電荷量が前記電 荷電圧変換回路の前記積分容量部に蓄積される時刻より前に、 前記積分容量部に おける電荷蓄積を終了させることを特徴とする光検出方法。 3. A photodetector that generates and outputs an amount of electric charge according to the intensity of the incident light, a switch element that controls the output of the electric charge generated by the photodetector, and the switch that is generated by the photodetector. The charge arriving through the element is stored in the integrating capacitance A charge-to-voltage conversion circuit that outputs a voltage output according to the amount of charge accumulated in the integration capacitance unit.A method for detecting the intensity of incident light, comprising: In the case where the charge generated in step (a) is temporarily saturated, the charge accumulation in the integration capacitance unit is terminated before the time when the saturation charge amount is accumulated in the integration capacitance unit of the charge-voltage conversion circuit. Light detection method.
PCT/JP2001/010737 2000-12-07 2001-12-07 Photosensor and photosensing method WO2002047377A1 (en)

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CN115392174A (en) * 2022-08-26 2022-11-25 苏州英嘉通半导体有限公司 Capacitance fitting method of field plate type semiconductor device
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CN115392174A (en) * 2022-08-26 2022-11-25 苏州英嘉通半导体有限公司 Capacitance fitting method of field plate type semiconductor device

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