ES2328779A1 - Digital read-out integrated circuit for the digital reading of high-speed image sensors - Google Patents

Abstract

The invention relates to read-out integrated circuits (ROIC) for reading image sensor arrays. The invention comprises a novel pulse modulator topology as part of the analog-digital converter for active digital pixels, which attenuates signal losses caused by the initialisation times of the analog integrator. The invention also comprises the use of the function enabling cancellation of the low-frequency noise of the analog integrator using correlated double sampling. The invention is advantageous over current technology in that it increases the image capture speed or alternatively reduces the power consumption in active pixels without a loss of resolution.

Description

Integrated circuit for digital reading of high speed image sensors.

Technical sector

The present invention relates to the sectors of information and communications technologies, and describes a specific microelectronic device for capture digital static or dynamic images. These images are decompose in pixels, whose individual value is obtained from the reading of a monolithic or hybrid optical sensor. The grouping in matrix of these sensors constitutes the focal plane of the image at capture. Taking into account the current state of the art, the The present invention has the advantage of maintaining the resolution versus faster image capture speed or alternatively decrease power consumption in pixels assets.

Current state of the art

The semiconductor market is currently experiencing a growing demand for portable devices capable of capturing images at very high speed, for applications such as automotive night navigation, medical diagnosis or strategic equipment. In general, these imaging devices are based on focal plane arrays ( Focal Plane Array , FPA) formed by active pixel sensors ( Active Pixel Sensor , APS), each containing both the optical sensor element and its individual pre-processed circuit .

Modern design techniques for APS cells partially include [US5461425, 1995-10-24, Standford University (US); US6707410, 2004-03-16, Micron Technology Inc. (US); US7023369, 2006-04-04, University of Rochester (US)] or completely [US6741198, 2004-03-25, R3 Logic Inc (US)] the analog -to-digital converter (ADC) within the APS itself, giving rise to active digital pixels ( Digital Pixel Sensor , DPS). Given the constraints of physical space within the active pixel, the most commonly adopted ADC architectures for DPS cells are predictive, compared to direct alternatives (eg parallel) and algorithmic (eg successive approximations), since they allow simplifying the parts ADC analog. In that sense, the complete or partially included processing chain within each DPS is shown in Figure 1. Its basic principle of operation is as follows: the optical sensor (1) generates an I_ {sens} current (2) proportional to the power of the incident lighting (3) and its response function; the current level (2) is converted to discrete digital output b_ {out} (4), in amplitude and time, by the predictive ADC block (5). Said ADC (5) consists of two stages in cascade: a PDM modulator, Pulse Density Modulation , (6) and a digital filter (11). The first stage (6) is responsible for discretizing the amplitude to the bit in the form of a pulse train V_ {pdm} (7); The main parts of this modulator (6) are a low frequency gain block (8), a quantizer (9) and a digital -to-analog converter (DAC) (10) that provides the necessary feedback For prediction. The power of the quantization error resulting from said modulation is mainly concentrated in the high frequency components of V_ {pdm}, so that a low-pass digital filtering is then applied in the second stage (11), which also Complete the discretization in time. As a result, the digital output word b_ {out} (4) is obtained.

In order to reduce the power consumption per pixel, the modulator (6) is usually implemented by asynchronous design techniques, whether they are of the " time to first spike" type [US5565915, 1996-10-15, Matsushita Electric Industrial Co; US6271785, 2001-09-07, Texas Instruments Inc; US6377303, 2002-04-23, Intel Corp; US6525304, 2003-02-25, Foveon Inc; US6559788, 2003-05-06; US6969879, 2005-11-29, STMicroelectronics Ltd; US7071982, 2006-07-04, Texas Instruments Inc; US7164114, 2007-01-16, Via Technologies Inc], or of type "event counting" ( spike counting ) [US7095439, 2006-09-22, Motorola Inc]. The advantage of the second strategy is the low digital switching activity during analog-digital conversion, with the consequent reduction of electronic noise.

In the case of high-speed DPS acquisition cells, the circuit topology commonly used for PDM modulators (6) for event counting and also for digital filtering (11) is shown in Figure 2. In order to minimize the DPS cell size, the compact PDM event count modulator (200) is reduced to: an integrator implemented by means of a capacitive transimpedance amplifier ( Capacitive Translmpedance Amplifier , CTIA) (201) with C_ {int} integration capability (202 ), which functions as a low frequency gain block (8) and polarizes the optical sensor (1) to a reference V_ {ref} (203); a comparator (204), which functions as a quantifier (9) with respect to a threshold V_ {th} (205); and a feedback of the pulse train V_ {pdm} (7) towards the initialization (206) of the CTIA (201), which performs the functions of DAC (10). Apart from this initialization on each pulse of V_ {pdm} (7), the CTIA (201) is also initialized before the analog-to-digital conversion phase by means of the V_ {init} signal (207) and by the same mechanism (206 ). The use of CTIA (201) is especially indicated for high-speed DPS cells that require low C_ {int} values (202), since it allows compensating high values of parasitic input capacity C_ {par} (208), either due to the optical sensor itself (1), CTIA (201), or the monolithic or hybrid interconnection between the two. Optionally, the PDM modulator (200) can also incorporate a second capacity C_ {cds} (209) controlled by the same signal V_ {pdm} (7) through the [key (210), and intended to cancel by CDS ( Correlated Double Sampling ) the low frequency noise of the CTIA (201) in the integrated signal V_ {int} (211). Regarding digital filtering (11), its realization is reduced to a first-order low-pass filter implemented by means of a digital counter (212), which functions as an integrator, and an initialization input (213) controlled by V_ {init } (207), which implements the losses in said integrator.

The ADC operating principle Predictive (5) based on the PDM modulator (200) and the counter Digital (212) is illustrated in Figure 3, taking into account that Figure 2 keys perform the operation indicated in each case for high logic levels of its control signals. One time Started the analog-digital conversion phase (300) by V_ {init} (207), the evolution of the integrated signal V_ {int} (211) describes a ramp (302), positive or negative according to the sign of I_ {sens} (2), until the comparator trip (204) to a distance V_ {th} (205), positive or negative according to the sign of I_ {sens} (2), with respect to the resting level V_ {ref} (203). How as a result of the said shot, a pulse (303) occurs in the signal V_ {pdm} (7) that causes the initialization of the CTIA (201) and the return of the integrated signal V_ {int} (211) to the standby level V_ {ref} (203) to start the cycle again. In conditions ideals (301), the duration of said pulse (303) is negligible compared to its periodicity T_ {pdmideal} (304), and in consequently the frequency of the signal V_ {pdm} (7) is 1 / T_ {pdmideal} = I_ {sens} / C_ {int} V_ {th}. Taking into account that the counter (212) integrates the number of pulses in V_ {pdm} (7) within the acquisition window T_ {frame} (305), the reading digital output b_ {out} (4) under ideal conditions (301) is proportional to the current I_ {sens} (2) of the optical sensor (1) a measure according b_ {out} = T_ {frame} / T_ {pdmideal} = I_ {sens} (T_ {frame} / C_ {int} V_ {th}).

In practice (306), the limitations of power in the different blocks of the PDM modulator (200) cause a duration T_ {res} (307), not zero, of the pulses (308) in V_ {pdm} (7). Bearing in mind that CTIA (201) cannot integrate the sensor current I_ {sens} (2) into the capacity C_ {int} (202) during the time T_ {res} (307), the evolution real (305) of the integrated signal V_ {int} (211) presents a periodicity T_ {pdmreal} (309) higher than the ideal T_ {pdmideal} (304), causing a loss of pulses in the V_ {pdm} signal (7) (e.g. 1 pulse in Figure 3) at the output of the PDM modulator (200). This loss is especially evident in high DPS cells speed, in which the ideal periodicity of the pulses T_ {pdmideal} (304) is short and comparable at the same time T_ {res} (307).

An example of the effects caused in the predictive ADC (5) by the loss of pulses in the V_ {pdm} signal (7) is presented in Figure 4. In this case an electric model of the PDM modulator (200) has been simulated for a complementary metal-oxide-semiconductor technology ( Complementary Metal-Oxide-Semiconductor , CMOS) of 0.18 µm, powered at 1.8V, with C_ {int} = C_ {cds} = 100fF, V_ {ref} = 1V and V_ {th} = 100 mV. The graph shows the value of the digital output word b_ {out} (4), in terms of the least significant bit ( Least Significant Bit , LSB), for T_ {frame} = 2 ms depending on the current I_ {sens} (2) generated in the optical sensor (1). Said analog-digital conversion curve (401) is calculated for different current consumption values I_ {bias} (400) in each block of the PDM modulator (200), equivalent to setting different values of T_ {res} (307). As the available power in the DPS cell circuits is limited by lowering I_ {bias} (400), the consequent increase in T_ {res} (307) rapidly accentuates the loss of pulses in the V_ {pdm} signal (7 ). Since this loss is dependent on the signal to be measured I_ {sens} (2), its effect is translated into a non-linearity of the digital output reading b_ {out} (4). In particular, a saturation of the upper part of the prediction ADC conversion curve (5) is observed, as can be seen in Figure 4.

The integrated circuit presented in this report of invention tries to solve this unwanted effect of non-linearity and saturation of the output signal  by means of a compact PDM modulator topology of events that do not require high power consumption in their circuits, especially for high-speed DPS cells data acquisition (images). The present invention addresses, also, to overcome the limitations presented by the circuits currently on the market and for this a new one is introduced PDM modulator topology especially indicated to avoid pulse losses due to block initialization time CTIA. This topology facilitates the reduction of dissipated power in each active pixel or alternatively it allows to increase the Image capture speed.

Description of the invention Brief Description of the Invention

The Integrated Circuit for Digital Reading of High Speed Image Sensors object of the present invention is characterized by comprising an optical sensor (1), and a Predictive ADC (5) completely or partially within the DPS cell. Said ADC (5) is composed, according to Figure 5, by a new PDM event count modulator (500), which performs the initialization of CTIA (501) and reduction of its noise by CDS by controlled injection of load in the ability to C_ {int} integration (502); as well as by a digital counter (212), for low-pass filtering of noise from PDM modulator quantification (500).

The new PDM modulator block for counting events (500) use a specific capacity C_ {reset / cds} (503) that allows the integration of the sensor current I_ {sens} (2) during the initialization of CTIA itself (501). Also, the capacity C_ {reset / cds} (503) is also used to sample the low frequency output noise of the CTIA (501) and perform your pre-compensation during the generation of each pulse in V_ {pdm} (7).

In comparison with the references of the state of The technique already mentioned above, the invention allows maintain the linearity of the ADC (5) even for time values of initialization of the CTIA (501) next to the pulse period V_ {pdm} (7). Consequently, the speed of image acquisition for the same power dissipated or, alternatively, reduce the power consumption in the circuits of the PDM modulator (500) maintaining the speed of acquisition.

       \ newpage
    

Detailed description of the invention

The Integrated Circuit for Digital Reading of High Speed Image Sensors object of the present invention is characterized by comprising an optical sensor (1), and a Predictive ADC (5), completely or partially within the DPS cell, composed according to Figure 5 by a new PDM modulator counting events (500) and by a digital counter (212).

The new compact PDM modulator counting events (500) incorporates: a CTIA (501) with integration capability C_ {int} (502), initializable by switch (504), which performs the functions of low frequency gain block (8); a comparator (204), which functions as a quantifier (9) with respect to a threshold V_ {th} (205); a capacity C_ {reset / cds} (503), identical to that of integration C_ {int} (502), which does the DAC functions (10) and is connected at one of its ends to the resting level V_ {ref} (203) of the integrated signal V_ {int} (505), while the other end of it C_ {reset / cds} (503) can be connected alternately to the output or to the input no CTIA inverter (501) using switches (506) and (507), respectively, according to the output V_ {pdm} (7) of the modulator itself PDM (500).

The operating principle of the new PDM modulator (500) is illustrated in Figure 6, taking into account that the switches in Figure 5 perform the indicated operation in each case for high logic levels of its control signals. The analog-digital conversion phase starts with the opening of the [wash (504) by V_ {init} (207). During the conversion window (300), the current is allowed I_ {sens} (2) generated by the incident lighting (3) in the sensor (1) can be integrated into C_ {int} (502) through CTIA (501), while the capacity C_ {reset / cds} (503) remains connected to the output of CTIA itself (501) through the switch (506) sampling the value of the integrated signal V_ {int} (505). The same CTIA (501) is also responsible for polarizing the sensor (1) at the resting voltage level V_ {ref} (203) and of compensate for the effect of the parasitic input capacity C_ {par} (208). The evolution of the integrated signal V_ {int} (505) to the CTIA exit (501) describes a ramp (601), positive or negative according to the sign of I_ {sens} (2), up to the trigger level of the comparator (204) located at a distance V_ {th} (205), positive or negative according to the sign of I_ {sens} (2), with respect to the level of rest V_ {ref} (203). As a result of this shot, produces a pulse (602) on the signal V_ {pdm} (7), causing the opening of the key (506) and closing of the key (507). The consequent switching of C_ {reset / cds} (503) injects the level load required in capacity C_ {int} (502) to cause the return of signal V_ {int} (505) to its idle value V_ {ref} (203), thus completing the initialization of CTIA (501).

However, and unlike the PDM topology (200) already commented in the State of the Art, during the duration T_ {res} (603) of the pulse V_ {pdm} (7) also allows integration of I_ {sens} (2) in C_ {int} (502), combined with the load injected through C_ {reset / cds} (503). This effect can be observed in the actual evolution (600) of the integrated signal V_ {int} (505), where the ramp (601) does not return to the level of standby V_ {ref} (203) after comparator trip (204) due precisely to the effect of the current I_ {sens} (2). From In fact, CTIA (501) operates as a continuous time integrator throughout the conversion window T_ {frame} (305), blocking only C_ {int} (502) during the pre-window phase in order to initialize the polarization of the optical sensor (1). In consequently, the actual period T_ {pdmreal} (604) of the signal V_ {pdm} (7) coincides with the theoretical period T_ {pdmideal} (304) in ideal conditions (301), even for times of initialization T_ {res} (603) comparable to the nominal period T_ {pdmideal} (304). Therefore, the signal frequency V_ {pdm} (7) is proportional to the sensor current to be measured according to 1 / T_ {pdmreal} = I_ {sens} / C_ {int} V_ {th}. Having in note that the counter (212) integrates the number of pulses in V_ {pdm} (7) within the acquisition window T_ {frame} (305), digital output reading b_ {out} (4) in conditions real (600) matches the ideal case (301) and is proportional to the  current I_ {sens} (2) of the optical sensor (1) to be measured according to the expression b_ {out} = T_ {frame} / T_ {pdmreal} = I_ {sens} (T_ {frame} / C_ {int} V_ {th}).

Apart from the initialization function of C_ {int} (502), the capacity C_ {reset / cds} (503) is also used for low frequency electronic noise attenuation of CTIA (501) through CDS. Before the shot of the comparator (204), C_ {reset / cds} (503) keeps sampled the electronic noise in V_ {int} (505) generated by the CTIA (501). During the initialization time T_ {res} (603), said noise is pre-substrat of C_ {int} (502) for the following integration cycle, thus implementing the CDS mechanism. In consequently, the noise components of the CTIA (501) are seen attenuated in a manner inversely proportional to its frequency.

Example of embodiment of the invention

Below is an example of compact embodiment of the invention, in which a detailed possible circuit implementation for each of the blocks of the new event counting PDM modulator (500) defined in the section of the Detailed Description of the Invention. The example a Detailed continuation has been electrically designed and simulated to a real 0.18 µm CMOS technology powered at 1.8V, although the same invention has already been successfully integrated for a 0.35 µm technology powered at 1.25V.

As shown in Figure 7, the CTIA integrator block (501) is implemented in this case by a single stage inverting amplifier composed of the N-type MOS Field Effect Transistor , NMOSFET M1 ( 700) and the current source I_ {bias} (701), together with the integration capacity C_ {int} (502). The resting level V_ {ref} (203) is generated locally within the modulator itself through the NMOSFET M2 (702), identical to MI (700), and the current source I_ {bias} (703), also identical to I_ {bias} (701). Both the pre-initialization key (504) and the switching keys (506) and (507) of C_ {reset / cds} (503) are implemented by means of NMOSFETs of minimum dimensions. For the realization of the comparator (204), another single stage inverting amplifier is used, composed of the NMOSFET M3 (704), with aspect ratio 1 / K with respect to Ml (700), and the current source I_ {bias } (705), identical to I_ {bias} (701), cascaded with a digital inverter (706) composed of complementary MOSFETs of minimum dimensions. Consequently, and assuming that Ml (700) and M3 (704) are operating in the sub-threshold region and in saturation, the equivalent threshold expression (205) is V_ {th} = nU_ {t} In (K), where n U_ {t} are the subthreshold slope of the transistor and the thermal operation potential, respectively.

Based on the circuit described in Figure 7, the results of the electrical simulation for the design case C_ {int} = C_ {cds} = 100fF, V_ {ref} = 1V and V_ {th} = 100 mV (for K = 20 and T = 27ºC) are presented in Figure 8. The graph shows the value of the digital output word b_ {out} (4), in terms of LSB ( Least Significant Bit ) for T_ {frame} = 2 ms depending on the current I_ {sens} (2) generated in the optical sensor (1). Said analog-digital conversion curves (801) are calculated for different current consumption values I_ {bias} (800) at the sources (701), (703) and (705) of the PDM modulator (500), equivalent to setting different values of T_ {res} (603).

From the direct comparison between Figures 2 (Current State of the Art) and 8 (results obtained in this example) it is clear that through the device presented herein, the saturation of the curve analog-to-digital conversion has been reduced by 75% factor with respect to the initial value, even in configurations that have drastic power limitations in the circuits of the DPS cell. This practical result constitutes (represents) a important advance in technology.

Detailed description of the figures

Fig. 1: The figure shows a general scheme of digital pixel reading, partially or completely included in each DPS cell, as it is currently manufactured (see Status of the Technique). It shows the existence of: an optical sensor (1), and a predictive ADC (5), consisting of a PDM modulator (6) and a Low pass digital output filter (11). Saying PDM modulator (6) consists of: a low gain block frequency (8), a quantifier (9), and a DAC (10) that supplies Feedback needed for prediction.

Fig. 2: The figure shows a compact topology of predictive ADC (5), partially or completely included in each DPS cell, as it is currently manufactured (see Status of the Technique). It shows the existence of: a PDM modulator High speed event count (200), and a digital counter (212). Said PDM modulator (200) is composed of: a CTIA integrator (201) with C_ {int} integration capability (202), a second C_ {cds} capacity (209) for noise cancellation by CDS, a comparator (204) and a feedback of the pulse train V_ {pdm} (7) towards the initialization (206) of the CTIA (201).

Fig. 3: The figure shows the operation of the PDM topology (200) presented in Figure 2, as it is currently manufactures (see State of the Art). In it appreciate the temporal evolution of window signals from acquisition V_ {init} (207), integration V_ {int} (211), and output V_ {pdm} (7), both for the ideal case (301) and for real implementations (306).

Fig. 4: The figure shows an example of Electrical simulation results for the PDM topology (200) presented in Figure 2. It shows the curve of transfer (401) of the predictive ADC (5) in word terms digital output b_ {out} (4) depending on the current I_ {sens} (2), generated in the optical sensor (1), for different current consumption values I_ {bias} (400) in each block of the PDM modulator (200).

Fig. 5: The figure shows the new topology of PDM high speed event counting modulator (500) proposed in the invention. It shows that said PDM modulator (500) consists of: a CTIA (501) with the ability to C_ {int} (502) and pre-initializable integration by means of the key (504), a comparator (204), and a capacity C_ {reset / cds} (503) connected at one of its ends at the level of idle V_ {ref} (203) of the integrated signal V_ {int} (505), while the other end of it C_ {reset / cds} (503) can alternatively connect to the output or to the non-inverting input of the CTIA (501) using the keys (506) and (507), respectively, according to the output V_ {pdm} (7) of the PDM modulator (500) itself.

Fig. 6: The figure shows the operation of the new PDM topology (500) proposed in the invention. In it appreciate the temporal evolution of window signals from acquisition V_ {init} (207), integration V_ {int} (211) and output V_ {pdm} (7), both for the ideal case (301) and for real implementations (600).

Fig. 7: The figure shows an example of compact realization of the new PDM topology (500) proposed in the invention. It shows the implementation of the blocks of Figure 5 using MOSFETs (700, 702 and 704), sources of current (701, 703 and 705), keys (504, 506 and 507) and doors Logic (706).

Fig. 8: The figure shows an example of electrical simulation results for the practical realization of the new PDM topology (500) proposed in the invention. In the same the transfer curve (801) of the predictive ADC (5) is appreciated in terms of digital output word b_ {out} (4) based on the current I_ {sens} (2), generated in the optical sensor (1), for different values of current consumption I_ {bias} (800) in each current source (701, 703 and 705).

Claims (6)

1. Integrated circuit for digital reading of high-speed image sensors characterized in that it comprises (see Figure 5):

a new PDM event count modulator (500) that incorporates: a CTIA (501) with C_ {int} integration capability (502) and pre-initializable using the key (504), which makes Low frequency gain block functions (8), polarize the optical sensor (1) to a reference V_ {ref} (203) and compensates for the effects of the parasitic input capacity C_ {par} (208); a comparator (204), which functions as a quantifier (9) with respect to a threshold V_ (205); a capacity C_ {reset / cds} (503), identical to that of integration C_ {int} (502), which performs the functions of DAC (10) and is connected in one from its ends to the resting level V_ {ref} (203) of the signal integrated V_ {int} (505), while the other end of it C_ {reset / cds} (503) can alternatively be connected to the output or to the non-inverting input of the CTIA (501) using the keys (506) and (507), respectively, according to the V_ {pdm} (7) output of the PDM modulator itself (500).

2. Integrated circuit for digital reading of high-speed image sensors, according to claim 1 and characterized by understanding (see Figure 5):

an optical sensor (one);

a PDM modulator according to claim 1;

3. Integrated circuit for digital reading of high-speed image sensors, according to claims 1 and 2, characterized by understanding (see Figure 5):

a PDM modulator according to claim 1;

an accountant digital (212) with initialization (213), which performs the functions of digital low-pass filter (11).

4. Integrated circuit for digital reading of high-speed image sensors, according to claims 1, 2 and 3, characterized by understanding (see Figure 5):

an optical sensor (one);

a PDM modulator according to claim 1;

an accountant digital (212) with initialization (213), which performs the functions of digital low-pass filter (11).

5. Integrated circuit according to claim 1, characterized (see Figure 6) for initializing the integration capacity C_ {int} (502) of the CTIA integrator (501) in each output pulse of the PDM modulator (500) by opening the key (506) and the closing of the key (507), injecting through C_ {reset / cds} (503) the level of charge necessary to cause the return of the V_ {int} signal (505) to its value standby V_ {ref} (203), without interrupting the integration of the current I_ {sens} (2) of the optical sensor (1) into the integration capacity C_ {int} (502) at any time during the entire window of T_ {frame} conversion (305). 6. Integrated circuit according to claim 1, characterized (see Figure 5) for using the same C_ {reset / cds} capacity (503) as in claim 2 to attenuate by CDS the effect of CTIA low frequency noise (501 ) by means of its pre-compensation in C_ {int} (502) in each output pulse generation of the PDM modulator (500).