WO2002011254A2

WO2002011254A2 - Widely tunable laser structure

Info

Publication number: WO2002011254A2
Application number: PCT/US2001/023649
Authority: WO
Inventors: Chan-Long Shieh; Barbara M. Foley
Original assignee: Motorola, Inc.
Priority date: 2000-07-31
Filing date: 2001-07-27
Publication date: 2002-02-07
Also published as: TW508882B; AU2001279044A1; WO2002011254A3

Abstract

High quality epitaxial layers of compound semiconductor materials (26, 1008) can be grown overlying large silicon wafers (22, 1002) by first growing an accommodating buffer layer (24, 1004) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Widely tunable lasers (92) can be created by growing lasers on the high quality compound semiconductor material and using an electro-optical crystalline oxide to tune wavelengths by forming electro-optical wave guide phase matching sections and electro-optical wave guide grating sections which lie adjacent to facets of the lasers which are preferably edge emitting lasers. In addition, widely tunable lasers can also be created by growing lasers on a silicon substrate and forming wave guide phase matching sections (94) and wave guide grating sections (96, 98) from an electro-optical crystalline oxide (24, 1004).

Description

WIDELYTUNABLELASERSTRUCTURE

Field of the Invention

This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to a widely tunable laser structure having a phase matching section and a wave guide section formed by growing a crystalline oxide on at least one facet of the laser.

Background of the Invention

The vast majority of semiconductor discrete devices and integrated circuits are fabricated from silicon, at least in part because of the availability of inexpensive, high quality monocrystalline silicon substrates. Other semiconductor materials, such as the so called compound semiconductor materials, have physical attributes, including wider bandgap and/or higher mobility than silicon, or direct bandgaps that make these materials advantageous for certain types of semiconductor devices. Unfortunately, compound semiconductor materials are generally much more expensive than silicon and are not available in large wafers as is silicon. Gallium arsenide (GaAs), the most readily available compound semiconductor material, is available in wafers only up to about 150 millimeters (mm) in diameter. In contrast, silicon wafers are available up to about 300 mm and are widely available at 200 mm. The 150 mm GaAs wafers are many times more expensive than are their silicon counterparts. Wafers of other compound semiconductor materials are even less available and are more expensive than GaAs.

Because of the desirable characteristics of compound semiconductor materials, and because of their present generally high cost and low. availability in bulk form, for many years attempts have been made to grow thin films of the compound semiconductor materials on a foreign substrate. To achieve optimal characteristics of the compound semiconductor material, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow layers of a monocrystalline compound semiconductor material on germanium, silicon, and various insulators. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting thin film of compound semiconductor material to be of low crystalline quality. If a large area thin film of high quality monocrystalline compound semiconductor material was available at low cost, a variety of semiconductor devices could advantageously be fabricated in that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of compound semiconductor material or in an epitaxial film of such material on a bulk wafer of compound semiconductor material. In addition, if a thin film of high quality monocrystalline compound semiconductor material could be realized on a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the compound semiconductor material. Accordingly, a need exists for a semiconductor structure that provides a high quality monocrystalline compound semiconductor film over another monocrystalline material and for a process for making such a structure.

This structure and process have extensive applications. One such application of this structure and process involves the formation of devices for use in optical communications. Semiconductor lasers are important components for many optical communication applications. At present, the change in refractive index along the cavity of most laser diodes is small thereby resulting in a small tuning range. However, a larger range for tuning lasing wavelength is desirable. For example, a wide tuning range for lasers used in dense wave length division multiplexer (DWDM) systems require lasers to be tuned within a wide range in order to overcome the limitations relating to available bandwidth in fiber optic systems. Accordingly, there is also a need for widely tunable lasers which are capable of tuning over a range of wavelengths that is broader than that which is capable of being tuned by lasers in the cunent art. Brief Description of the Drawings

The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:

FIGS. 1-3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention;

FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer;

FIG. 5 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer; FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer;

FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer;

FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer;

FIG. 9 illustrates a top plan view of an exemplary embodiment of a widely tunable laser system in accordance with the present invention;

FIG. 10 illustrates in cross section the exemplary embodiment of the widely tunable laser system of the present invention shown in FIG. 9; FIG. 11 illustrates an enlarged view of the area within the tunable laser system of FIG. 10 in which the lasing and tuning of wavelengths takes place; and

FIG. 12 illustrates a schematic view of another exemplary embodiment of the present invention directed to a widely tunable laser system having multiple lasers. Detailed Description of the Drawings

FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 in accordance with an embodiment of the invention. Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material. In this context, the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and gennanium and epitaxial layers of such materials commonly found in the semiconductor industry.

In accordance with one embodiment of the invention, structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24. Structure 20 may also include a template layer 30 between the accommodating buffer layer and compound semiconductor layer 26. As will be explained more fully below, the template layer helps to initiate the growth of the compound semiconductor layer on the accommodating buffer layer. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer. Substrate 22, in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter. The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group rVA. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate. In accordance with one embodiment of the invention, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline compound semiconductor layer 26.

Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material. For example, the material could be an oxide or nitride having a lattice structure matched to the substrate and to the subsequently applied semiconductor material. Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafniates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements. Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24. Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.

The compound semiconductor material of layer 26 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III- V semiconductor compounds), mixed III-V compounds, Group II(A or B) and VIA elements (II- VI semiconductor compounds), and mixed II- VI compounds. Examples include gallium arsenide (GaAs), gallium indium arsenide (GalnAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP), cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide (ZnSe), zinc sulfur selenide (ZnSSe), and the like. Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent compound semiconductor layer 26. Appropriate materials for template 30 are discussed below.

FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment of the invention. Structure 40 is similar to the previously described semiconductor structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26. Specifically, the additional buffer layer is positioned between template layer 30 and the overlying layer of compound semiconductor material. The additional buffer layer, formed of a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying monocrystalline compound semiconductor material layer.

FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention. Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38.

As explained in greater detail below, amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline semiconductor layer 26 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing--e.g., compound semiconductor layer 26 formation. The processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline compound semiconductor layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline compound semiconductor layers because it allows any strain in layer 26 to relax.

Semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32. For example, layer 38 may include monocrystalline Group rv or monocrystalline compound semiconductor materials. In accordance with one embodiment of the present invention, semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound. In accordance with another embodiment of the invention, semiconductor layer 38 comprises compound semiconductor material (e.g., a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38. In this case, a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26. In other words, the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36.

The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.

Example 1

In accordance with one embodiment of the invention, monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm. In accordance with this embodiment of the invention, accommodating buffer layer 24 is a monocrystalline layer of Sr_zBa_1-zTiO₃ where z ranges from 0 to 1 and the amorphous interme diate layer is a layer of silicon oxide (SiO_x) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to conesponding lattice constants of the subsequently formed layer 26. The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the compound semiconductor layer from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.

In accordance with this embodiment of the invention, compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers (μm) and preferably a thickness of about 0.5 μm to 10 μm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the gallium arsenide or aluminum gallium arsenide on the monocrystalline oxide, a template layer is formed by capping the oxide layer. The template layer is preferably 1 - 10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O. By way of a prefened example, 1-2 monolayers of Ti-As or Sr-Ga-O have been shown to successfully grow GaAs layers.

Example 2

In accordance with a further embodiment of the invention, monocrystalline substrate 22 is a silicon substrate as described above. The accommodating buffer layer is a monocrystalline oxide of strontium or barium zirconate or hafniate in a cubic or orthorhombic phase with an amorphous intennediate layer of silicon oxide formed at the interface between the silicon substrate and the accommodating buffer layer. The accommodating buffer layer can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is fonned of a monocrystalline SrZrO₃, BaZrO₃, SrHfO₃, BaSnO₃ or BaHfO₃. For example, a monocrystalline oxide layer of BaZrO₃ can grow at a temperature of about 700 degrees C. The lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate silicon lattice structure. An accommodating buffer layer formed of these zirconate or hafniate materials is suitable for the growth of compound semiconductor materials in the indium phosphide (InP) system. The compound semiconductor material can be, for example, indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide, (AlInAs), or aluminum gallium indium arsenic phosphide (AlGalnAsP), having a thickness of about 1.0 nm to 10 μm. A suitable template for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As), zirconium-phosphorus (Zr-P), hafnium- arsenic (Hf-As), hafnium-phosphorus (Hf-P), strontium-oxygen-arsenic (Sr-O-As), strontium-oxygen-phosphorus (Sr-O-P), barium-oxygen-arsenic (Ba-O-As), indium- strontium-oxygen (In-Sr-O), or barium-oxygen-phosphorus (Ba-O-P), and preferably 1- 2 monolayers of one of these materials. By way of an example, for a barium zirconate accommodating buffer layer, the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1 -2 monolayers of arsenic to fonn a Zr-As template. A monocrystalline layer of the compound semiconductor material from the indium phosphide system is then grown on the template layer. The resulting lattice structure of the compound semiconductor material exhibits a 45 degree rotation with respect to the accommodating buffer layer lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.

Example 3

In accordance with a further embodiment of the invention, a structure is provided that is suitable for the growth of an epitaxial film of a II- VI material overlying a silicon substrate. The substrate is preferably a silicon wafer as described above. A suitable accommodating buffer layer material is Sr_xBa_1-xTiO₃, where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. The II- VI compound semiconductor material can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe). A suitable template for this material system includes 1- 10 monolayers of zinc-oxygen (Zn-O) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface. Alternatively, a template can be, for example, 1-10 monolayers of strontium-sulfur (Sr-S) followed by the ZnSeS.

Example 4 This embodiment of the invention is an example of structure 40 illustrated in FIG. 2. Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1. In addition, an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material. Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP), an indium gallium arsenide (InGaAs), an aluminum indium phosphide (AllnP), a gallium arsenide phosphide (GaAsP), or an indium gallium phosphide (InGaP) strain compensated superlattice. In accordance with one aspect of this embodiment, buffer layer 32 includes a GaAs_xP]_-x superlattice, wherein the value of x ranges from 0 to 1. In accordance with another aspect, buffer layer 32 includes an In_yGa_1-yP superlattice, wherein the value of y ranges from 0 to 1. By varying the value of x or y, as the case may be, the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying compound semiconductor material. The compositions of other materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner. The superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm. The template for this structure can be the same of that described in example 1. Alternatively, buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm. In using a germanium buffer layer, a template layer of either germanium-strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer. The formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium. The monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond. Example 5

This example also illustrates materials useful in a structure 40 as illustrated in FIG. 2. Substrate material 22, accommodating buffer layer 24, monocrystalline compound semiconductor material layer 26 and template layer 30 can be the same as those described above in example 2. In addition, a buffer layer 32 is inserted between the accommodating buffer layer and the overlying monocrystalline compound semiconductor material layer. The buffer layer, a further monocrystalline semiconductor material, can be, for example, a grated layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs). In accordance with one aspect of this embodiment, buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%. The buffer layer preferably has a thickness of about 10-30 nm. Varying the composition of the buffer layer from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material and the overlying layer of monocrystalline compound semiconductor material. Such a buffer layer is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.

Example 6

This example provides exemplary materials useful in structure 34, as illustrated in FIG. 3. Substrate material 22, template layer 30, and monocrystalline compound semiconductor material layer 26 may be the same as those described above in connection with example 1.

Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above). For example, amorphous layer 36 may include a combination of SiO_x and Sr_zBa_1-z TiO (where z ranges from 0 to l),which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36. The thickness of amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like, h accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2- 10 nm, and more preferably about 5-6 nm.

Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24. In accordance with one embodiment of the invention, layer 38 includes the same materials as those comprising layer 26. For example, if layer 26 includes GaAs, layer 38 also includes GaAs. However, in accordance with other embodiments of the present invention, layer 38 may include materials different from those used to fonn layer 26. In accordance with one exemplary embodiment of the invention, layer 38 is about 1 monolayer to about 100 nm thick.

Referring again to FIGS. 1-3, substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms "substantially equal" and "substantially matched" mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.

FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.

In accordance with one embodiment of the invention, substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable. Still referring to FIGS. 1-3, layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate 22. To achieve high crystalline quality in this epitaxially grown monocrystalline layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer 26, substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. If the grown crystal is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and the accommodating buffer layer is monocrystalline Sr_xBa_1-xTiO₃, substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide. Similarly, if the host material is a strontium or barium zirconate or a strontium or barium hafniate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide, substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal. In some instances, a crystalline semiconductor buffer layer between the host oxide and the grown compound semiconductor layer can be used to reduce strain in the grown monocrystalline compound semiconductor layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline compound semiconductor layer can thereby be achieved. The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1-3. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a prefened embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 0.5° off axis. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thennally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.

In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.

Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.

After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material. For the subsequent growth of a layer of gallium arsenide, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of this capping layer, arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As. Any of these form an appropriate template for deposition and formation of a gallium arsenide monocrystalline layer. Following the formation of the template, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide forms. Alternatively, gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.

FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention. Single crystal SrTiO accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch. GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.

FIG. 6 illustrates an x-ray diffraction spectrum taken on structure including GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 24. The peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.

The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step. The buffer layer is formed overlying the template layer before the deposition of the monocrystalline compound semiconductor layer. If the buffer layer is a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template described above. If instead the buffer layer is a layer of germanium, the process above is modified to cap the strontium titanate monocrystalline layer with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer can then be deposited directly on this template.

Structure 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36. Layer

26 is then subsequently grown over layer 38. Alternatively, the anneal process may be carried out subsequent to growth of layer 26.

In accordance with one aspect of this embodiment, layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 10 seconds to about 10 minutes. However, other suitable anneal processes maybe employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing or "conventional" thermal annealing processes (in the proper environment) may be used to fonn layer 36. When conventional thermal annealing is employed to form layer 36, an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process. For example, when layer 38 includes GaAs, the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38. As noted above, layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.

FIG. 7 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3. In Accordance with this embodiment, a single crystal SrTiO accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above. Next, GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.

FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22. The peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.

The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafniates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other III-V and II- VI monocrystalline compound semiconductor layers can be deposited overlying the monocrystalline oxide accommodating buffer layer. Each of the variations of compound semiconductor materials and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the compound semiconductor layer. For example, if the accommodating buffer layer is an alkaline earth metal zirconate, the oxide can be capped by a thin layer of zirconium. The deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively. Similarly, if the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafniate, the oxide layer can be capped by a thin layer of hafnium. The deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively. In a similar manner, strontium titanate can be capped with a layer of strontium or strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen. Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a compound semiconductor material layer comprising indium gallium arsenide, indium aluminum arsenide, or indium phosphide.

FIG. 9 shows a top plan view of an exemplary embodiment of a widely tunable laser system 90 in accordance with the present invention. Laser system 90 includes an edge emitting laser 92, an electro-optical waveguide phase matching section 94 in alignment with and contacting the edge of laser 92, an electro-optical wave guide grating section 96 in alignment with phase matching section 94, another electro-optical wave guide grating section 98 in alignment with and contacting the opposite edge of laser 92, a laser control circuit 100 operatively coupled to laser 92 to control the operation of laser 92, control circuits 102 and 104 to independently control the index of refraction of electro-optical wave guide grating sections 96 and 98, and control circuit 106 to control the phase angle of the beam coupled from electro-optical phase matching section 94 into grating section 96.

A cross section of the widely tunable laser system 90 shown in FIG. 9 is illustrated in FIG. 10. Laser 92, electro-optical wave guide grating sections 96 and 98, and electro-optical wave guide phase matching section 94 are all grown on a monocrystalline oxide such as the oxides described above with reference to layer 24 in FIGS. 1,2 and 5 and preferably include alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides. Laser 92 is preferably comprised of a monocrystalline compound semiconductor material such as those previously described with reference to layer 26 in FIGS. 1-3 but which preferably include GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS. Electro-optical wave guide grating sections 96 and 98, and phase matching section 94, are formed from monocrystalline oxide layers similar to the oxide layer that they are grown on. Prefened materials for these layers are STO and BST.

In order to fabricate tunable laser system 90, a monocrystalline semiconductor substrate 1002 such as silicon functions as the starting material. An oxide layer 1004 is then grown epitaxially over substrate 1002 and an amorphous intermediate layer 1006 may be formed between substrate 1002 and oxide layer 1004 by the oxidation of substrate 1002 during the growth of oxide layer 1004. As indicated above, oxide layer 1004 maybe comprised of a monocrystalline oxide material such as that comprising layer 24 with reference to FIGS. 1,2 and 5. In addition, oxide layer 1004 may comprise an amorphous oxide layer, which is fonned by annealing amorphous intermediate layer 1006 and a monocrystalline oxide layer, such as layer 36 described with reference to FIG. 3.

Next, a monocrystalline compound semiconductor layer 1008 is epitaxially deposited over oxide layer 1004 and then patterned to form a laser diode 1110 formed at least partially in the compound semiconductor layer 1008 in accordance with those methods of patterning known in the art. A layer of electro-optical material 1111 having a first index of refraction is epitaxially deposited over oxide layer 1004 such that layer 1111 contacts or is proximate an edge of laser 92. Another layer 1112 of electro-optical material having a second index of refraction is then epitaxially deposited over layer 1111 and layer 1112 is patterned to form a wave guide phase matching section 1114 in alignment with and contacting or proximate the edge of laser 92, and a wave guide grating section 1116 in alignment with phase matching section 1114. A wave guide may also be formed an opposite edge of laser 92 in a like manner. Another layer 1118 of electro-optical material having a third index of refraction is epitaxially deposited over wave guide phase matching section 1114 and wave guide grating section 1116. A periodic pattern is formed in layers 1111, 1112 or 1118 of wave guide 96 and/or 98 to form an optical grating 1120 at a position spaced apart from laser 92. The periodic spacing of the grating is such that it provides an effective minor at or near the wave length peak gain for the laser, as is known in the art. The periodic pattern formed in one of layers 1111, 1112, or 1118 of wave guide

96 and/or 98 may include ion implanting a pattern of impurity dopants in layer 1111, 1112, or 1118 to change the index of refraction of the implanted layer, or selectively etching the surface of layer 1111, 1112, or 1118 to form a spatial variation in the thickness of the etched layer. The ion implantation and etching may be carried out by suitable implantation and etching means known in the art.

An electrode layer 1122 may then be deposited over layer 1118 and patterned to form electrode(s) to operate laser 92, to tune the phase of the beam output from section 94, and to electro-optically tune the grating of sections 96, 98, as known in the art. For example, electrode(s) 1124 proximate to phase matching section 94 and an electrode(s) 1126 proximate to optical grating 1120 may suitably be formed. Integrated circuits 106 and 102 may also be formed partially or wholly within substrate 1002 and coupled via interconnect to electrode(s) 1124 and electrode(s) 1126 in order to electro-optically control the index of refraction of sections 94, 96. In addition, a laser control circuit 100 may be formed at least partially in substrate 1002 and coupled to laser 92 with an interconnect to control operation of the laser.

Layers 1111, 1112 and 1118 are deposited adjacent to laser 92 and are preferably comprised of an oxide material similar to layer 1004 which may include alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides. Furthermore, layers 1111, 1112 and 1118 may be doped with a dopant to change their respective index of refraction: at least one of layers 1111, 1112, and 1118 is electro-optic.

The step of annealing monocrystalline oxide layer 1004 and amorphous intermediate layer 1006 to form an amorphous oxide layer similar to layer 36 described in reference to FIG. 3 may be performed after depositing monocrystalline oxide layer 1004 by rapid thermal annealing. Moreover, like the epitaxial depositing steps described with reference to FIGS. 1-3, the steps of epitaxially depositing specific layers to form system 90 may be performed by MBE, MOCVD, MEE, CVD, PVD, PLD, CSD, and ALE. As previously stated, oxide layer 1004 and layers 1111, 1112, and 1118 which form wave guide 95 are comprised of an oxide material such as that comprising layer 24 previously described with reference to FIGS. 1,2, and 5. However, in one exemplary embodiment of system 90, oxide layer 1004 preferably comprises (Sr,Ba)TiO₃ or LiNbO₃ and wave guide 95 which includes layers 1111, 1112, and 1118 preferably comprises an oxide having an index of refraction value that is responsive to an electric field such as (Sr,Ba)TiO₃. With respect to wave guide 95, oxide layers 1111, 1112, and 1118 conespond to a bottom cladding layer, a core, and a top cladding layer, respectively.

Optical grating 1120 may be formed by etching a pattern in any one of layers 1111, 1112, and 1118 by way of photo-assisted etching or any other suitable etching means. Optical grating 1120 may also be formed by doping any of layers 1111, 1112, or 1118 with a periodic pattern of an impurity by ion implantation or other suitable means. Moreover, core layer 1112 of wave guide 95 may be formed by photolithographically patterning any of layers 1111, 1112, or 1118. Light is directed from laser 92 to wave guide phase matching section 94 to wave guide grating section 96. Light directed into wave guide grating section 96 is guided through core layer 1112. Preferably, wave guide grating section 96 is designed such that substantially all light received from phase matching section 94 is confined within core 1112 of wave guide grating section 96 during light transmission and optical grating 1120 is configured to provide a reflectivity centered about a wavelength centered about the operation wavelength of laser 92. Phase matching section 94 can be used to optimize phase angle for maximum reflectivities afforded by the gratings 1120.

To obtain total or at least substantial internal reflection, core layer 1112 is fonned of a material having a different index of refraction than the material used to form top and bottom cladding layers 1118 and 1111. More particularly, the index of refraction of core layer 1112 is greater than the index of refraction of top and bottom cladding layers 1118 and 1111, which may suitably be formed of the same material. In accordance with an exemplary embodiment, material selected for core layer 1112 has an index of refraction of n_l5 material selected for top and bottom cladding layers 1118 and 1111 has an index of refraction of n₂, and the difference between ni and n₂ is about

0.02. Accordingly, optical grating 1120 will comprise a periodic perturbation in wave guide grating section 96. The periodic perturbation may be in one of layers 1111, 1112 or 1118 and may comprise an etched surface or a periodic impurity doping.

As previously described, wave guide grating section 96 may be formed from monocrystalline oxide layers 1111, 1112 and 1118 etched with grating 1120.

Accordingly, suitable materials for core 1112 and top and bottom cladding layers 1118 and 1111 include oxides like those previously described for layers 1111, 1112 and 1118 which include alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, perovskite oxides, other suitable oxides, nitrides, and the like. In accordance with one particular example, core layer 1112 may include strontium titanate doped with a material (e.g., an impurity), and top and bottom cladding layers 1118 and 1111 may include undoped strontium titanate such that the refractive index of top and bottom cladding layers 1118 and 1111 is lower than the refractive index of core layer 1112.

FIG. 11 illustrates an enlarged view of the area 1150 within the tunable laser system of FIG. 10 in which the lasing and tuning of wavelengths takes place. Gain section 1152 of laser 92 has a first facet 1154. Layer 1156 which conesponds to layer 1118 in FIG. 10 includes wave guide phase matching section 1158 and wave guide grating section 1160. Layer 1154 is deposited such that phase matching section 1158 lies adjacent to first facet 1154 of laser 1152. Laser 1152 also includes a second facet 1162.

Conventional tunable distributed feedback (DFB) or distributed Bragg reflector (DBR) lasers have a tuning range of around 5 nanometers (nm) and cannot achieve a wide tuning range. This is due to the fact that the change in refractive index that can be achieved in conventional compound semiconductors such as InGaAsP material systems is limited. Moreover, an injection of cunent, which consumes a lot of power, is used to change the refractive index. As described above, the widely tunable laser of the present invention allows for making tunable DBR lasers on a silicon wafer where the interface between the silicon and the electro-optical crystalline oxide enables growth of lasers on the silicon. The widely tunable lasers of the present invention can also be grown on monocrystalline compound semiconductor materials such as on GaAs wafers. In either case, DBR optical gratings are made on an electro-optical crystalline oxide such as, for example, BTO. Since a large change in the index of refraction can be made in electro- optical crystalline oxides, a wide tuning range can be achieved. In addition, the power consumed in the widely tunable lasers of the present invention is much less than in conventional tunable lasers since tuning is achieved by applying voltage instead of cunent.

Referring again to FIG. 11 , gain section 1152 is made on a compound semiconductor material, for example InGaAsP and then defined by etching in accordance with suitable etching processes known in the art. Electro-optical crystalline oxide layer 1156 is then grown in the etched region to selectively create wave guide grating section 1160 and wave guide phase matching section 1158. Optical grating 1164 is made in wave guide grating section 1160 by etching and overgrowth. Electrodes (not shown) can be placed on gain section 1152, wave guide phase matching section 1158 and wave guide grating section 1160. The widely tunable laser of the present invention can be formed in parallel and used as multiple sources of different wavelengths in WDM systems. Optical grating 1164 may be formed on both facets 1154 and 1162 of gain section 1152 to provide greater tunability. Tuning is achieved by applying voltage to wave guide phase matching section 1158 and wave guide grating section 1160.

A schematic view of another exemplary embodiment of the present invention directed to a widely tunable laser system 1200 having multiple distributed bragg grating lasers (DBGL) 1202, 1204, and 1206 is illustrated in FIG. 12. DBGLs 1202, 1204, and 1206 include a laser 1208 , an electro-optical wave guide phase matching section 1210, a wave guide grating section 1212, and an associated integrated control circuit 1214. Each DBGL may be formed of materials described above in connection with system 90, illustrated in FIGS. 9 and 10. Control circuit 1214 may include a laser control circuit, a phase matching control circuit, and a grating control circuit as described above. Each or these circuits may be autonomous or integrated with one or more other circuits.

Further, although not illustrated, multiple control circuits 1214 maybe combined into a single integrated circuit configured to control multiple portions of system 1200 — e.g., one circuit could control multiple portions of multiple DBGLs. Each integrated control circuit 1214 is fonned at least partially in a substrate such as silicon or a suitable compound semiconductor material and is coupled via interconnects 1216 to electrodes that are positioned to create electric fields across lasers 1208, phase matching sections 1210, and/or wave guide sections 1212.

DBGLs 1202, 1204, and 1206 maybe configured such that light emitted from one laser of system 1200 may be of the same or different as a wavelength of light emitted from another laser of system 1200. For example, various lasers of system 1200 may have diffraction gratings and/or tuning circuits that allow the associated DBGL to emit light of various wavelengths, which wavelengths may differ by about 2 nm or more. System 1200 allows tight control of light emitted from each DBGL, which in turn, allows for a greater bandwidth of information to be transmitted from system 1200. Laser system 1200 may be formed according to the methods described above in connection with system 90, except system 1200 includes multiple lasers systems (DBGLs) in parallel. Forming multiple lasers in parallel allows formation of wavelength division multiplexers (WDM) or dense wavelength division multiplexers (DWDM) on a single substrate. Widely tunable lasers of the present invention can be used in telecommunications, data communications, data storage and optical networks and provide an improvement over existing tunable lasers in that they provide for tuning over a wider range of wavelengths. In addition, the lasers and laser systems of the present invention are advantageous because they may be monolithically formed over a substrate such as a silicon wafer and consequently may be monolithically integrated with circuits formed on or within such a substrate.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, solution to occur or become more pronounced are not to be constructed as critical, required, or essential features or elements of any or all of the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A tunable semiconductor laser comprising:

a monocrystalline semiconductor substrate;

a first oxide layer epitaxially grown overlying the substrate;

a monocrystalline compound semiconductor laser diode formed overlying the first oxide layer, the laser diode having an output intensity peaking at an operation wavelength;

an electro-optical wave guide formed overlying the first oxide layer and coupled to receive the output from a first facet of the laser diode, the wave guide comprising a first phase matching section and a second section comprising an optical grating.

2. The laser of claim 1 wherein the semiconductor substrate comprises silicon.

3. The laser of claim 2 wherein the first oxide layer comprises an oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

4. The laser of claim 3 further comprising an amorphous silicon oxide formed underlying the first oxide layer.

5. The laser of claim 3 wherein the first oxide layer comprises a monocrystalline oxide.

6. The laser of claim 3 wherein the first oxide layer comprises an amorphous oxide.

7. The laser of claim 3 wherein the first oxide layer comprises a material selected from the group consisting of (Sr,Ba)TiO and LiNbO₃.

8. The laser of claim 3 wherein the laser diode comprises a compound semiconductor material selected from the group consisting of GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS.

9. The laser of claim 1 further comprising a laser control circuit formed at least partially in the substrate and operatively coupled to the laser diode to control the operation wavelength thereof.

10. The laser of claim 1 wherein the electro-optical wave guide comprises an oxide having an index of refraction the value of which is responsive to an electric field.

11. The laser of claim 10 wherein the electro-optical wave guide comprises a material selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

12. The laser of claim 11 wherein the electro-optical wave guide comprises (Sr,Ba)TiO₃.

13. The laser of claim 10 further comprising electrodes configured to apply an electric field across the electro-optical wave guide to control the index of refraction thereof.

14. The laser of claim 1 wherein the electro-optical wave guide comprises a first cladding layer having a first index of refraction, a core layer overlying the first cladding layer and having a second index of refraction, and a second cladding layer overlying the core layer and having a third index of refraction where the second index of refraction is greater than the first index of refraction and greater than the third index of refraction.

15. The laser of claim 14 wherein the optical grating comprises a periodic perturbation in the wave guide.

16. The laser of claim 15 wherein the optical grating comprises a periodic perturbation in one of the first cladding layer, core layer, or second cladding layer.

17. The laser of claim 16 wherein the periodic perturbation comprises an etched surface.

18. The laser of claim 16 wherein the periodic perturbation comprises a periodically varying impurity doping profile.

19. The laser of claim 14 wherein the first oxide layer comprises the first cladding layer.

20. The laser of claim 1 wherein the optical grating is configured to provide a reflectivity centered about a wavelength centered about the operation wavelength.

21. The laser of claim 1 wherein the laser diode comprises a first facet and a second facet.

22. The laser of claim 21 further comprising a second electro-optical wave guide formed overlying the first oxide layer and coupled to receive the output from the second facet of the laser diode, the wave guide comprising a second optical grating.

23. The laser of claim 22 further comprising a laser control circuit formed at least partially in the substrate and operatively coupled to the laser diode to control the operation wavelength thereof.

24. The laser of claim 23 further comprising electrodes configured to apply an electric field across the electro-optical wave guide and across the second electro-optical wave guide to control the index of refraction of each.

25. The laser of claim 24 v. h .i in c optical grating is configured to provide a reflectivity centered about a first was a....^ • •• >u . >e ond optical grating is configured to provide a second reflectivity centered about a second wavelength.

26. The laser of claim 25 wherein the first wavelength is different than the second wavelength and the control circuit is set to maintain the operation wavelength at a value between the first wavelength and the second wavelength.

27. The laser of claim 25 further comprising a second controller circuit formed at least partially in the substrate, coupled to the electrodes, and configured to control the index of refraction of the electro-optical wave guide and the second electro-optical wave guide.

28. The laser of claim 1 wherein the first phase matching section is aligned with and coupled to the laser diode and to the second section.

29. A tunable semiconductor laser comprising:

a monocrystalline semiconductor substrate;

a first oxide layer epitaxially grown overlying the substrate; an amorphous oxide layer formed underlying the first oxide layer;

a monocrystalline compound semiconductor laser diode capable of emitting radiation, the laser diode formed overlying the first oxide layer;

an electro-optical phase matching section coupled to receive the radiation from a first facet of the laser diode; and

an electro-optical wave guide coupled to receive the radiation after the radiation passes through the phase matching section.

30. The laser of claim 29 wherein the phase matching section comprises an electro- optical material having an index of refraction, the material selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

31. The laser of claim 30 further comprising first and second electrodes configured to apply a voltage across the phase matching section in a manner to influence the refractive index of the electro-optical material.

32. The laser of claim 29 wherein the electro-optical wave guide comprises an electro-optical material having a second index of refraction, the material selected from the group consisting of alkali eartli metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

33. The laser of claim 32 wherein the optical wave guide further comprises an optical grating.

34. The laser of claim 33 wherein the optical grating comprises a periodic perturbation in the optical wave guide.

35. The laser of claim 34 wherein the periodic perturbations comprise spatial variations of the index of refraction.

36. The laser of claim 34 wherein the optical grating comprises a plurality of layers and the perturbations in the optical wave guide comprise spatial variations in the thickness of one of the layers.

37. The laser of claim 32 wherein the optical grating is configured to provide a reflectivity centered about a predetermined wavelength.

38. The laser of claim 37 further comprising first and second electrodes configured to apply a voltage across the optical grating in a manner to influence the refractive index of the electro-optical material and the predetermined wavelength.

39. The laser of claim 29 wherein the electo-optical phase matching section and the wave guide each comprises an electro-optical material having an index of refraction the value of which is responsive to an applied electric field.

40. The laser of claim 39 further comprising:

first and second electrodes configured to apply an electric field across the wave guide; and

third and fourth electrodes configured to apply an electric field across the phase matching section.

41. The laser of claim 40 further comprising an integrated control circuit formed at least partially in the substrate and coupled to the first and second electrodes and to the third and fourth electrodes.

42. The laser of claim 41 further comprising a laser diode control circuit formed at least partially in the substrate and coupled to the laser diode.

43. The laser of claim 42 wherein the semiconductor substrate comprises silicon.

44. The laser of claim 43 wherein the first oxide layer comprises an oxide selected from the group consisting of alkali earth metal titanates, zirconates, and hafnates.

45. The laser of claim 44 wherein the amorphous oxide layer comprises silicon oxide.

46. The laser of claim 45 wherein the laser diode comprises a compound semiconductor material selected from the group consisting of GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS.

47. The laser of claim 46 wherein the electro-optical phase matching section and the electro-optical wave guide each comprise an electro-optical material selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

48. The laser of claim 47 wherein the electro-optical phase matching section and the electro-optical wave guide each comprise an epitaxially deposited monocrystalline oxide.

49. The laser of claim 29 wherein the electro-optical phase matching section is aligned with and coupled to the laser diode and to the electro-optical wave guide.

50. A laser diode anay comprising:

a monocrystalline semiconductor substrate;

a first oxide layer epitaxially grown overlying the substrate;

an amorphous oxide layer formed underlying the first oxide layer;

a plurality of monocrystalline compound semiconductor laser diodes each capable of emitting radiation, the laser diodes epitaxially formed overlying the first oxide layer;

a plurality of electro-optical phase matching sections, one coupled to each of the plurality of laser diodes to receive the radiation from the coupled laser diode, the plurality of phase matching sections epitaxially formed overlying the first oxide layer and formed of electro-optical material having an index of refraction;

a plurality of electro-optical wave guides, each coupled to receive the radiation from one of the plurality of laser diodes after the radiation passes through the coupled phase matching section, the plurality of wave guides epitaxially formed overlying the first oxide layer and formed of electro-optical material having an index of refraction;

electrodes coupled to each of the plurality of phase matching sections and to each of the plurality of wave guides, the electrodes configured to individually change the refractive index of each of the plurality of phase matching sections and of each of the plurality of wave guides in a predetermined manner; and integrated control circuitry formed in the substrate and coupled to each of the electrodes.

51. A process for fabricating a tunable laser comprising the steps of:

providing a monocrystalline semiconductor substrate;

epitaxially depositing a first oxide layer overlying the substrate;

epitaxially depositing a monocrystalline compound semiconductor layer overlying the first oxide layer;

patterning the compound semiconductor layer to form a laser diode at least partially in the compound semiconductor layer;

epitaxially depositing a second layer of electro-optical material having a first index of refraction overlying the first oxide layer and contacting an edge of the laser diode;

epitaxially depositing a third layer of electro-optical material having a second index of refraction overlying the second layer, the third layer contacting the edge of the laser diode;

patterning the third layer to form a phase matching section in alignment with and contacting the edge of the laser diode and a wave guide section in alignment with the phase matching section;

epitaxially depositing a fourth layer of electro-optical material having a third index of refraction overlying the phase matching section and the wave guide section;

forming a periodic pattern in one of the second layer, third layer, or fourth layer in a portion of the wave guide section to form an optical grating in the wave guide section at a position spaced apart from the laser diode; depositing a layer of electrode material overlying the fourth layer; and

patterning the layer of electrode material to form first electrical field electrodes proximate the phase matching section and second electric field electrodes proximate the optical grating.

52. The process of claim 51 further comprising the steps of:

forming an integrated circuit at least partially in the substrate; and

coupling the integrated circuit to the first electric field electrodes and to the second electric field electrodes.

53. The process of claim 51 wherein each of the steps of epitaxially depositing comprises the step of epitaxially depositing by a process selected from the group consisting of MBE, MOCVD, MEE, CVD, PVD, PLD, CSD and ALE.

54. The process of claim 51 wherein the step of epitaxially depositing a first oxide comprises the step of epitaxially depositing a monocrystalline layer of oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

55. The process of claim 54 further comprising the step of annealing the monocrystalline layer of oxide to convert the layer of monocrystalline oxide to a layer of amorphous oxide.

56. The process of claim 55 wherein the step of annealing comprises annealing after at least the step of epitaxially depositing a monocrystalline compound semiconductor layer.

57. The process of claim 55 wherein the step of annealing comprises rapid thermal annealing.

58. The process of claim 51 wherein the step of providing a monocrystalline semiconductor substrate comprises the step of providing a substrate comprising silicon.

59. The process of claim 58 further comprising the step of forming an amorphous oxide layer underlying the first oxide layer during the step of epitaxially depositing a first oxide layer.

60. The process of claim 49 wherein the steps of epitaxially depositing a second layer and epitaxially depositing a third layer comprises the steps of selectively depositing the second layer adjacent the laser diode and selectively depositing the third layer adjacent the laser diode.

61. The process of claim 51 wherein the step of forming a periodic pattern comprises the step of ion implanting a pattern of impurity dopants into one of the second layer, the third layer or the fourth layer to change the index of refraction of the implanted layer.

62. The process of claim 51 wherein the step of forming a periodic pattern comprises the step of selectively etching the surface of one of the second layer, the third layer or the fourth layer to form a spatial variation in the thickness of the etched layer.

63. The process of claim 51 wherein the steps of epitaxially depositing a second layer, epitaxially depositing a third layer, and epitaxially depositing a fourth layer each comprise the step of depositing a layer of oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

64. The process of claim 63 wherein the steps of epitaxially depositing a second layer, epitaxially depositing a third layer, and epitaxially depositing a fourth layer each further comprise the step of impurity doping the deposited layer to determine the index of refraction thereof.

65. A

a monocrystalline semiconductor substrate;

a first oxide layer epitaxially grown overlying the substrate;

an electro-optical wave guide formed overlying the first oxide layer and coupled to receive the output from a first facet of the laser diode, the wave guide comprising an optical grating.

66. The laser of claim 65 wherein the semiconductor substrate comprises silicon.

67. The laser of claim 66 wherein the first oxide layer comprises an oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

68. The laser of claim 67 further comprising an amorphous silicon oxide formed underlying the first oxide layer.

69. The laser of claim 67 wherein the first oxide layer comprises a monocrystalline oxide.

70. The laser of claim 67 wherein the first oxide layer comprises an amorphous oxide.

71. The laser of claim 67 wherein the first oxide layer comprises a material selected from the group consisting of (Sr,Ba)TiO and LiNbO₃.

72. The laser of claim 67 wherein the laser diode comprises a compound semiconductor material selected from the group consisting of GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS.

73. The laser of claim 65 further comprising a laser control circuit formed at least partially in the substrate and operatively coupled to the laser diode to control the operation wavelength thereof.

74. The laser of claim 65 wherein the electro-optical wave guide comprises an oxide having an index of refraction the value of which is responsive to an electric field.

75. The laser of claim 74 wherein the electro-optical wave guide comprises a material selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

76. The laser of claim 75 wherein the electro-optical wave guide comprises (Sr,Ba)TiO₃.

77. The laser of claim 74 further comprising electrodes configured to apply an electric field across the electro-optical wave guide to control the index of refraction thereof.

78. The laser of claim 65 wherein the electro-optical wave guide comprises a first cladding layer having a first index of refraction, a core layer overlying the first cladding layer and having a second index of refraction, and a second cladding layer overlying the core layer and having a third index of refraction where the second index of refraction is greater than the first index of refraction and greater than the third index of refraction.

79. The laser of claim 78 wherein the optical grating comprises a periodic perturbation in the wave guide.

80. The laser of claim 79 wherein the optical grating comprises a periodic perturbation in one of the first cladding layer, core layer, or second cladding layer.

81. The laser of claim 80 wherein the periodic perturbation comprises an etched surface.

82. The laser of claim 80 wherein the periodic perturbation comprises a periodic variation in impurity doping profile.

83. The laser of claim 78 wherein the first oxide layer comprises the first cladding layer.

84. The laser of claim 65 wherein the optical grating is configured to provide a reflectivity centered about a wavelength centered about the operation wavelength.

85. The laser of claim 65 wherein the laser diode comprises a first facet and a second facet.

86. The laser of claim 85 further comprising a second electro-optical wave guide formed overlying the first oxide layer and coupled to receive the output from the second facet of the laser diode, the wave guide comprising a second optical grating.

87. The laser of claim 86 further comprising a laser control circuit formed at least partially in the substrate and operatively coupled to the laser diode to control the operation wavelength thereof.

88. The laser of claim 87 further comprising electrodes configured to apply an electric field across the electro-optical wave guide and across the second electro-optical wave guide to control the index of refraction of each.

89. The laser of claim 88 wherein the optical grating is configured to provide a reflectivity centered about a first wavelength and the second optical grating is configured to provide a second reflectivity centered about a second wavelength.

90. The laser of claim 89 wherein the first wavelength is different than the second wavelength and the control circuit is set to maintain the operation wavelength at a value between the first wavelength and the second wavelength.

91. The laser of claim 89 further comprising a second controller circuit formed at least partially in the substrate, coupled to the electrodes, and configured to control the index of refraction of the electro-optical wave guide and the second electro-optical wave guide.

92. A tunable semiconductor laser comprising: a monocrystalline semiconductor substrate;

a first oxide layer epitaxially grown overlying the substrate;

an amorphous oxide layer formed underlying the first oxide layer;

a monocrystalline compound semiconductor laser diode capable of emitting radiation, the laser diode formed overlying the first oxide layer; and

an electro-optical wave guide coupled to receive the radiation emitted from the laser diode.

93. The laser of claim 29 wherein the electro-optical wave guide comprises an electro-optical material having an index of refraction, the material selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

94. The laser of claim 93 wherein the electro-optical wave guide further comprises an optical grating.

95. The laser of claim 94 wherein the optical grating comprises a periodic perturbation in the electro-optical wave guide.

96. The laser of claim 34 wherein the periodic perturbations comprise spatial variations of the index of refraction.

97. The laser of claim 95 wherein the optical grating comprises a plurality of layers and the perturbations in the electro-optical wave guide comprise spatial variations in the thickness of one of the layers.

98. The laser of claim 94 wherein the optical grating is configured to provide a reflectivity centered about a predetermined wavelength.

99. The laser of claim 97 further comprising first and second electrodes configured to apply a voltage aero. - *tιe optical grating in a manner to influence the refractive index of the electro-opticai , • ' ' >.? the predetermined wavelength.

100. The laser of claim 92 wherein the electro-optical wave guide comprises an electro-optical material having an index of refraction the value of which is responsive to an applied electric field.

101. The laser of claim 99 further comprising:first and second electrodes configured to apply an electric field across the electro-optical wave guide.

102. The laser of claim 100 further comprising an integrated control circuit formed at least partially in the substrate and coupled to the first and second electrodes.

103. The laser of claim 101 further comprising a laser diode control circuit formed at least partially in the substrate and coupled to the laser diode.

104. The laser of claim 102 wherein the semiconductor substrate comprises silicon.

105. The laser of claim 103 wherein the first oxide layer comprises an oxide selected from the group consisting of alkali earth metal titanates, zirconates, and hafnates.

106. The laser of claim 104 wherein the amorphous oxide layer comprises silicon oxide.

107. The laser of claim 105 wherein the laser diode comprises a compound semiconductor material selected from the group consisting of GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS.

108. The laser of claim 106 wherein the electro-optical wave guide comprises an electro-optical material selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafnates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

109. The laser of claim 107 wherein the electro-optical wave guide comprises an epitaxially deposited monocrystalline oxide.