WO2002008806A2

WO2002008806A2 - Monolithic optical system

Info

Publication number: WO2002008806A2
Application number: PCT/US2001/022423
Authority: WO
Inventors: Barbara M. Foley; Jerald A. Hallmark; William Jay Ooms
Original assignee: Motorola, Inc.
Priority date: 2000-07-21
Filing date: 2001-07-17
Publication date: 2002-01-31
Also published as: TW523809B; AU2001282899A1; WO2002008806A3

Abstract

High quality epitaxial layers of compound semiconductor materials (111) can be grown overlying large silicon wafers by first growing an accommodating buffer layer (24) on a silicon wafer (92). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (98) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Optical structures, including optical sources (1112) such as light emitting diodes or lasers and photodetectors such as photodiodes (1114) may be formed in the high quality epitaxial compound semiconductor material while wave guides (1004) having refractive and reflective capabilities are formed in the oxide layers underlying the high quality epitaxial compound semiconductor material. These optical structures are monolithically coupled to one another to form monolithic optical systems.

Description

MONOLITHIC OPTICAL SYSTEM

Field of the Invention

This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to integrated, monolithic optical systems including a light source and a wave guide .

Background of the Invention

The vast majority of semiconductor discrete devices and integrated circuits are fabricated from silicon, at least in part because of the availability of inexpensive, high quality monocrystalline silicon substrates. Other semiconductor materials, such as the so called compound semiconductor materials, have physical attributes, including wider bandgap and/or higher mobility than silicon, or direct bandgaps that make these materials advantageous for certain types of semiconductor devices . Unfortunately, compound semiconductor materials are generally much more expensive than silicon and are not available in large wafers as is silicon. Gallium arsenide (GaAs) , the most readily available compound semiconductor material, is available in wafers only up to about 150 millimeters (mm) in diameter. In contrast, silicon wafers are available up to about 300 mm and are widely available at 200 mm. The 150 mm GaAs wafers are many times more expensive than are their silicon counterparts. Wafers of other compound semiconductor materials are even less available and are more expensive than GaAs . Because of the desirable characteristics of compound semiconductor materials, and. because of their present generally high cost and low availability in bulk form, for many years attempts have been made to grow thin films of the compound semiconductor materials on a foreign substrate. To achieve optimal characteristics of the compound semiconductor material, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow layers of a monocrystalline compound semiconductor material on germanium, silicon, and various insulators. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting thin film of compound semiconductor material to be of low crystalline quality. If a large area thin film of high quality monocrystalline compound semiconductor material was available at low cost, a variety of semiconductor devices could advantageously be fabricated in that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of compound semiconductor material or in an epitaxial film of such material on a bulk wafer of compound semiconductor material. In addition, if a thin film of high quality monocrystalline compound semiconductor material could be realized on a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the compound semiconductor material . Accordingly, a need exists for a semiconductor structure that provides a high quality monocrystalline compound semiconductor film over another monocrystalline material and for a process for making such a structure. This structure and process have extensive applications. One such application of this structure and process involves the formation of a monolithic optical system which includes a light source and a wave guide .

Use of this structure and process to connect a light source, such as a laser or light emitting diode (LED) , to a wave guide results in the monolithic coupling of these devices thereby enabling more devices to be formed on a single chip.

Brief Description of the Drawings

The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:

FIGS. 1-3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention;

FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer; FIG. 5 illustrates a high resolution Transmission

Electron Micrograph of a structure including a monocrystalline accommodating buffer layer;

FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer;

FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer;

FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer;

FIGS. 9-11 illustrate in cross section the formation of a monolithic optical system in accordance with one exemplary embodiment of the present invention; FIG. 12 illustrates a top view of a monolithic optical system in accordance with another exemplary embodiment of the present invention;

FIG. 13 illustrates a top view of a monolithic optical system in accordance with yet another embodiment of the present invention;

FIG. 14 illustrates a top view of a monolithic optical system in accordance with still another exemplary embodiment of the present invention; FIGS. 15-18 illustrate in cross section the formation of a monolithic system in accordance with the exemplary embodiment of the present invention shown in FIG. 14; and

FIGS. 19-23 illustrate in cross section the formation of yet another embodiment of a monolithic optical system in accordance with the present invention.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description of the Drawings

FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 in accordance with an embodiment of the invention. Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material. In this context, the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.

In accordance with one embodiment of the invention, structure 20 also includes an amorphous intermediate layer

28 positioned between substrate 22 and accommodating buffer layer 24. Structure 20 may also include a template layer 30 between the accommodating buffer layer and compound semiconductor layer 26. As will be explained more fully below, the template layer helps to initiate the growth of the compound semiconductor layer on the accommodating buffer layer. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.

Substrate 22, in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter. The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate . In accordance with one embodiment of the invention, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer

24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline compound semiconductor layer 26. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material . For example, the material could be an oxide or nitride having a lattice structure matched to the substrate and to the subsequently applied semiconductor material. Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafniates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements. Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24.

Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.

The compound semiconductor material of layer 26 can be selected, as needed for a particular semiςonductor structure, from any of the Group IIIA and VA elements

(III-V semiconductor compounds) , mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds. Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , indium phosphide

(InP) , cadmium sulfide (CdS) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe) , and the like. Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent compound semiconductor layer 26. Appropriate materials for template 30 are discussed below.

FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment of the invention. Structure 40 is similar to the previously described semiconductor structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26. Specifically, the additional buffer layer is positioned between template layer 30 and the overlying layer of compound semiconductor material. The additional buffer layer, formed of a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying monocrystalline compound semiconductor material layer.

FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention. Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38.

As explained in greater detail below, amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline semiconductor layer 26 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing--e.g. , compound semiconductor layer 26 formation.

The processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline compound semiconductor layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline compound semiconductor layers because it allows any strain in layer 26 to relax.

Semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32. For example, layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials.

In accordance with one embodiment of the present invention, semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound.

In accordance with another embodiment of the invention, semiconductor layer 38 comprises compound semiconductor material { e . g. , a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38. In this case, a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26. In other words, the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36.

The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.

Example 1

In accordance with one embodiment of the invention, monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200- 300 mm. In accordance with this embodiment of the invention, accommodating buffer layer 24 is a monocrystalline layer of Sr_zBa₁__zTi0₃ where z ranges from 0 to 1- and the amorphous interme diate layer is a layer of silicon oxide (SiO_x) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26. The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the compound semiconductor layer from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm. In accordance with this embodiment of the invention, compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide

(AlGaAs) having a thickness of about 1 nm to about 100 micrometers (μm) and preferably a thickness of about 0.5 μm to 10 μm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the gallium arsenide or aluminum gallium arsenide on the monocrystalline oxide, a template layer is formed by capping the oxide layer. The template layer is preferably 1-10 monolayers of Ti-As, Sr-

O-As, Sr-Ga-O, or Sr-Al-O. By way of a preferred example,

1-2 monolayers of Ti-As or Sr-Ga-O have been shown to successfully grow GaAs layers.

Example 2

In accordance with a further embodiment of the invention, monocrystalline substrate 22 is a silicon substrate as described above. The accommodating buffer layer is a monocrystalline oxide of strontium or barium zirconate or hafniate in a cubic or orthorhombic phase with an amorphous intermediate layer of silicon oxide formed at the interface between the silicon substrate and the accommodating buffer layer. The accommodating buffer layer can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZr0₃, BaZr0₃, SrHf0₃, BaSn0₃ or BaHf0₃. For example, a monocrystalline oxide layer of BaZr0₃ can grow at a temperature of about 700 degrees C. The lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate silicon lattice structure. An accommodating buffer layer formed of these zirconate or hafniate materials is suitable for the growth of compound semiconductor materials in the indium phosphide (InP) system. The compound semiconductor material can be, for example, indium phosphide (InP) , indium gallium arsenide (InGaAs) , aluminum indium arsenide, (AlInAs) , or aluminum gallium indium arsenic phosphide (AlGalnAsP) , having a thickness of about 1.0 nm to 10 μm. A suitable template for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As) , zirconium- phosphorus (Zr-P) , hafnium-arsenic (Hf-As) , hafnium- phosphorus (Hf-P) , strontium-oxygen-arsenic (Sr-O-As) , strontium-oxygen-phosphorus (Sr-O-P) , barium-oxygen- arsenic (Ba-O-As) , indium-strontium-oxygen (In-Sr-O) , or barium-oxygen-phosphorus (Ba-O-P) , and preferably 1-2 monolayers of one of these materials . By way of an example, for a barium zirconate accommodating buffer layer, the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template. A monocrystalline layer of the compound semiconductor material from the indium phosphide system is then grown on the template layer. The resulting lattice structure of the compound semiconductor material exhibits a 45 degree rotation with respect to the accommodating buffer layer lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.

Example 3

In accordance with a further embodiment of the invention, a structure is provided that is suitable for the growth of an epitaxial film of a II-VI material overlying a silicon substrate. The substrate is preferably a silicon wafer as described above. A suitable accommodating buffer layer material is Sr_xBa₁._xTi0₃ , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. The II-VI compound semiconductor material can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe) . A suitable template for this material system includes 1-10 monolayers of zinc-oxygen (Zn-O) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface. Alternatively, a template can be, for example, 1-10 monolayers of strontium-sulfur (Sr-S) followed by the ZnSeS .

Example 4

This embodiment of the invention is an example of structure 40 illustrated in FIG. 2. Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1. In addition, an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material. Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs) , an indium gallium phosphide (InGaP) , an indium gallium arsenide (InGaAs) , an aluminum indium phosphide (AllnP) , a gallium arsenide phosphide (GaAsP) , or an indium gallium phosphide (InGaP) strain compensated superlattice . In accordance with one aspect of this embodiment, buffer layer 32 includes a GaASP^ superlattice, wherein the value of x ranges from 0 to 1. In accordance with another aspect, buffer layer 32 includes an In_yGa^_yP superlattice, wherein the value of y ranges from 0 to 1. By varying the value of x or y, as the case may be, the lattice constant is varied from bottom to top across the superlattice. to create a match between lattice constants of the underlying oxide and the overlying compound semiconductor material . The compositions of other materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner. The superlattice can have a thickness of about 50-500 n and preferably has a thickness of about 100-200 nm. The template for this structure can be the same of that described in example 1. Alternatively, buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm. In using a germanium buffer layer, a template layer of either germanium-strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer. The formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium. The monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.

Example 5

This example also illustrates materials useful in a structure 40 as illustrated in FIG. 2. Substrate material 22, accommodating buffer layer 24, monocrystalline compound semiconductor material layer 26 and template layer 30 can be the same as those described above in example 2. In addition, a buffer layer 32 is inserted between the accommodating buffer layer and the overlying monocrystalline compound semiconductor material layer. The buffer layer, a further monocrystalline semiconductor material, can be, for example, a grated layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide

(InAlAs) . In accordance with one aspect of this embodiment, buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%. The buffer layer preferably has a thickness of about 10-30 nm.

Varying the composition of the buffer layer from GaAs to

InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material and the overlying layer of monocrystalline compound semiconductor material. Such a buffer layer is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.

Example 6

This example provides exemplary materials useful in structure 34, as illustrated in FIG. 3. Substrate material 22, template layer 30, and monocrystalline compound semiconductor material layer 26 may be the same as those described above in connection with example 1.

Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above) . For example, amorphous layer 36 may include a combination of SiO_x and Sr^a^ Ti0₃ (where z ranges from 0 to 1) , which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.

The thickness of amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like.

In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5- 6 nm.

Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24. In accordance with one embodiment of the invention, layer 38 includes the same materials as those comprising layer 26. For example, if layer 26 includes GaAs, layer 38 also includes GaAs. However, in accordance with other embodiments of the present invention, layer 38 may include materials different from those used to form layer 26. In accordance with one exemplary embodiment of the invention, layer 38 is about 1 monolayer to about 100 nm thick.

Referring again to FIGS. 1-3, substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms "substantially equal" and "substantially matched" mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.

FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that have a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved. In accordance with one embodiment of the invention, substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable. Still referring to FIGS. 1-3, layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate

22. To achieve high crystalline quality in this epitaxially grown monocrystalline layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer 26, substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. If the grown crystal is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and the accommodating buffer layer is monocrystalline Sr_xBa₁__xTi0₃ , substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide. Similarly, if the host material is a strontium or barium zirconate or a strontium or barium hafniate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide, substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal. In some instances, a crystalline semiconductor buffer layer between the host oxide and the grown compound semiconductor layer can be used to reduce strain in the grown monocrystalline compound semiconductor layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline compound semiconductor layer can thereby be achieved. The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1-3. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, up to about 6° off axis. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus . In the case where strontium is used, the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.

In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.

Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.

After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material. For the subsequent growth of a layer of gallium arsenide, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of this capping layer, arsenic is deposited to form a Ti- As bond, a Ti-O-As bond or a Sr-O-As. Any of these form an appropriate template for deposition and formation of a gallium arsenide monocrystalline layer. Following the formation of the template, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide forms. Alternatively, gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.

FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention. Single crystal SrTi0₃ accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch. GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.

FIG. 6 illustrates an x-ray diffraction spectrum taken on structure including GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 2 . The peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.

The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step. The buffer layer is formed overlying the template layer before the deposition of the monocrystalline compound semiconductor layer. If the buffer layer is a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template described above. If instead the buffer layer is a layer of germanium, the process above is modified to cap the strontium titanate monocrystalline layer with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer can then be deposited directly on this template .

Structure 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36. Layer 26 is then subsequently grown over layer 38. Alternatively, the anneal process may be carried out subsequent to growth of layer 26.

In accordance with one aspect of this embodiment, layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700 °C to about 1000°C and a process time of about 10 seconds to about 10 minutes. However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing or "conventional" thermal annealing processes (in the proper environment) may be used to form layer 36. When conventional thermal annealing is employed to form layer 36, an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process. For example, when layer 38 includes GaAs, the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38. As noted above, layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26.

Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.

FIG. 7 is a high resolution Transmission Electron

Micrograph (TEM) of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3. In Accordance with this embodiment, a single crystal SrTi0₃ accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above. Next, GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.

FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22. The peaks in the spectrum indicate that

GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.

The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafniates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other III-V and II-VI monocrystalline compound semiconductor layers can be deposited overlying the monocrystalline oxide accommodating buffer layer. Each of the variations of compound semiconductor materials and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the compound semiconductor layer. For example, if the accommodating buffer layer is an alkaline earth metal zirconate, the oxide can be capped by a thin layer of zirconium. The deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively. Similarly, if the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafniate, the oxide layer can be capped by a thin layer of hafnium. The deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively. In a similar manner, strontium titanate can be capped with a layer of strontium or strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen. Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a compound semiconductor material layer comprising indium gallium arsenide, indium aluminum arsenide, or indium phosphide. The formation of a monolithic optical system shown in cross section in accordance with one exemplary embodiment of the present invention is illustrated in FIGS. 9-11. As previously described with reference to FIGS. 1, 2, and 5, and as shown in FIG. 9, an accommodating buffer layer 94 comprising a monocrystalline oxide, like layer 24 discussed above in connection with FIGS. 1, 2, and 5, is grown epitaxially on a Group IV substrate 92. During this growth process, an amorphous interface layer 98 is formed which relieves strain due to lattice mismatch where amorphous interface layer 98 is like layer 28 discussed above. Alternatively, an amorphous oxide layer, such as layer 36 described in reference to FIG. 3, may be formed from monocrystalline oxide layer 94 and amorphous interface layer 98 by an annealing process as previously described above .

Next, as shown in FIG. 10, a wave guide 1004 is formed by etching an optical grating 1006 into a surface of monocrystalline oxide layer 94 to form a diffractive optical element (DOE) , such as a hologram, for example, at a desired location for the beam of a light source such as a light emitting diode (LED) or a laser such as a vertical cavity surface-emitting laser (VCSEL) . Grating 1006 can also be etched at the receiving end of wave guide 1004 where the light will be directed into a photodetector such as a photodiode. Wave guide 1004 includes a core 1008 surrounded by a top cladding layer 1010 and a bottom cladding layer 1012.

Optical grating 1006 may be formed by etching a pattern in top cladding layer 1010 by way of photo- assisted etching or any other suitable etching means. Optical grating 1006 may also be formed by doping a surface of oxide layer 94 , such as top cladding layer 1010, with a periodic pattern of an impurity by ion implantation or other suitable means. Moreover, core 1008 of wave guide 1004 may be formed by photolithographically patterning oxide layer 94. Oxide layer 94 which comprises oxide layers 1008, 1010, and 1012 preferably comprises

Sr_^Ba^_^ iO_;, where x ranges, from zero to one and wherein depositing layers 1008, 1010, and 1012 is performed by

MBE, CVD, PVD, PLD or CSD.

After forming wave guide 1004, a layer of monocrystalline compound semiconductor material 1111 is epitaxially deposited overlying optical grating (s) 1006 as shown in FIG. 11. A light source such as VCSEL 1112 and/or a photodetector such as photodiode 1114 are then at least partially formed within monocrystalline compound semiconductor layer 1111. Optical system 1100 shown in FIG. 11 includes light source, depicted as VCSEL 1112, wave guide 1004, and photodetector depicted as photodiode 1114, and is capable of transmitting light having a wavelength or wavelengths between the infrared and ultraviolet regions of light . Those skilled in the art will also appreciate that optical system 1100 may also include a light source control unit and an electrical connection between the light source control unit and photodetector to enable feedback control of the light source. These additional features of system 1100 are later explained in detail with reference to the exemplary embodiment of the present invention shown in FIG. 13.

Wave guide 1004 includes a core 1008 surrounded by a top cladding layer 1010 and a bottom cladding layer 1012. VCSEL 1112 emits most of its power into the bottom facet adjacent to layer 1111 containing wave guide 1004 and wave guide 1004 guides light through core 1008. Preferably, wave guide 1004 and grating 1006 are designed such that substantially all light received from VCSEL 1112 is confined within core 1008 of wave guide 1004 during light transmission toward photodiode 1114; i.e., the light is preferably transmitted through wave guide 1004 with total internal reflection.

To obtain total or at least substantial internal reflection, core 1008 is formed of a material having a different index of refraction than the material used to form top and bottom cladding layers 1010 and 1012. More particularly, the index of refraction of core 1008 is greater than the index of refraction of top and bottom cladding layers 1010 and 1012, which may suitably be formed of the same material. In accordance with an exemplary embodiment, material selected for core 1008 has an index of refraction of n_x, material selected for top and bottom cladding layers 1010 and 1012 has an index of refraction of n₂, and the difference between n_x and n₂ is about 0.02.

As previously described, wave guide 1004 may be formed from monocrystalline oxide layer 94 etched with grating 1006. Accordingly, suitable materials for core 1008 and top and bottom cladding layers 1010 and 1012 include oxides such as alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, perovskite oxides, other suitable oxides, nitrides, and the like. For example, one or more of core 1008, top cladding layer 1010, and bottom cladding layer 1012 may include a monocrystalline oxide such as that described above in connection with any of FIGS. 1-3. In accordance with one particular example, core 1008 may include strontium titanate doped with a material (e.g., an impurity), and top and bottom cladding layers 1010 and 1012 may include undoped strontium titanate such that the refractive index of top and bottom cladding layers 1010 and 1012 is lower than the refractive index of core 1008. Wave guide 1004 is formed on amorphous intermediate layer 98 by depositing a monocrystalline oxide material for bottom cladding layer 1012, depositing another monocrystalline layer for the core having a refractive index greater than the refractive index of the material used to form bottom cladding layer 1012, etching bottom cladding layer 1012 to pattern core 1008, depositing another monocrystalline oxide layer to form top cladding layer 1010 having a refractive index lower than the monocrystalline oxide material used to form core 1008, and then etching gratings 1006 into top cladding layer 1010 above core 1008 of wave guide 1004 to form a DOE which will diffract the light from VCSEL 1112 into an angle permitting the coupling of the light into wave guide 1004. Accordingly, the wave guide structure includes a periodic effective index difference. After formation of wave guide 1004, VCSEL 1112 and photodiode 1114 are built on a monocrystalline compound semiconductor material directly above gratings 1006. FIG. 12 illustrates a top view of a monolithic optical system 1200 in accordance with another exemplary embodiment of the present invention. Monolithic optical system 1200 includes a light source 1202 such a s a VCSEL or LED, optical wave guides 1204, and detectors 1206. However, as shown in this embodiment, gratings as previously described with reference to FIGS. 10 and 11, are designed to refract the light into multiple directions. In FIG. 12, the DOE under the VCSEL 1202 directs light into four different directions. Monolithic optical system 1100 may be formed on Group IV substrate 92, which may include various devices such as CMOS circuits formed therein. FIG. 13 illustrates a top view of a monolithic optical system in accordance with yet another embodiment of the present invention which includes a feedback control loop. Optical system 1300 includes a light source 1302, an optical detector 1304, a feedback control circuit 1306, a light source control unit 1308, and a wave guide 1310 coupled to both light source 1302 and optical detector 1304. In accordance with the present invention, each of light source 1302, optical detector

1304, circuit 1306, light source control circuit 1308, and wave guide 1310 are monolithically integrated on a Group

IV substrate .

In general, optical system 1300 is configured to control an output from light source 1302, for example, at a desired intensity level, using a feedback look 1312. In accordance with the illustrated example, detector 1304 (with appropriate receiver circuitry) converts light received from light source 1302 into an electrical signal. Feedback circuit 1306 manipulates the signal from detector 1304 with an appropriate gain, and light source control circuit 1308 sends a signal to light source 1302 in response to a signal received from feedback circuit 1306. Detector 1304 circuitry, feedback circuit 1306, and light source control circuit 1308 may be formed in any suitable semiconductor layer. For example, light source control circuit 1308 may be formed within the Group IV (e.g., silicon) substrate or within any semiconductor material deposited thereon. A top view of yet another embodiment of a monolithic optical system in accordance with another exemplary embodiment of the present invention is shown in FIG. 14. Optical system 1400 includes a light source 1402, a wave guide 1404, and a photo detector 1406. Light source 1402 is preferably a laser or light emitting diode and both light source 1402 and photo detector 1406 are formed within a compound semiconductor region of system 1400. Wave guide 1404 is formed from an oxide layer which may be a monocrystalline oxide layer or an amorphous oxide layer. FIGS. 15-17 illustrate in cross section the formation of the exemplary monolithic optical system shown in FIG.

14. As shown in FIG. 15, a wave guide 1404 is formed over a substrate 92 which is preferably a Group IV substrate as previously indicated with reference to FIGS. 9-11.

Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Substrate 92 is preferably a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer.

Wave guide 1404 includes a core 1408 which is surrounded by a top cladding layer 1410 and a bottom cladding layer 1412. Wave guide 1404 is formed from an oxide layer overlying substrate 92 wherein the oxide layer is preferably a perovskite oxide or a titanium rich oxide such as barium titanate or strontium titanate. However, this oxide layer may also comprise an oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates . Core 1408 of wave guide 1404 may be formed by doping or implanting the oxide layer with a material (e.g., an impurity) so that core 1408 has a higher refractive index than top and bottom cladding layers 1410 and 1412. For example, core 1408 may include a strontium titanate, doped with a specific material, and top and bottom cladding layers 1410 and 1412 may include undoped strontium titanate such that the refractive index of top and bottom cladding layers

1410 and 1412 is lower than the refractive index of core 1408.

Although top and bottom cladding layers may both have the same index of refraction, the index of refraction of core 1408 must be great than the index of refraction of top and bottom cladding layers 1410 and 1412. In addition, although core 1408 and top and bottom cladding layers 1410 and 1412 may each have a different index of refraction thereby creating three indexes of refraction within wave guide 1404, the index of refraction of core

1408 must be greater than the index of refraction of both top and bottom cladding layers 1410 and 1412.

In order to enable directing light from a light source, a light source 1425, shown as a VCSEL, for example, in FIG. 16, and/or a photo detector 1426, shown as a photodiode, for example, in FIG. 16, are both formed at least partially in a monocrystalline compound semiconductor layer 1424 grown epitaxially over the oxide layer. An optical mirror is then formed to reflect light output from VCSEL 1425 in a direction along wave guide 1404 by beveling the oxide layer which comprises wave guide 1404 such that the oxide layer forms an angle X with respect to substrate 92 where angle X is within the critical angle for total internal reflection. For the oxides described herein, n is approximately 2.5 so the critical angle is approximately 23 degrees.

For example, as shown in FIG. 17, the oxide layer which comprises wave guide 1404 is beveled such that it forms a 45 degree angle with respect to substrate 92 which is within the critical angle required to achieve total internal reflection of light from VCSEL 1425 as shown in FIG. 18. Furthermore, the beveled surface of wave guide 1404 may be coated with a metal to provide a mirror surface . Photo-assisted etch, which uses a wet etch in combination with collimated ultraviolet (UV) light, is used to fabricate the beveled surface of the oxide layer. For example, in this case, the wet etch may be sulfuric acid (or hydrochloric acid) with a small amount of hydrofluoric acid. The sulfuric acid acts as a slow etch while the hydrofluoric acid passivates the surface and reduces the etch rate to almost zero. An opaque mask, such as a photosresist , a polysilicon or a metal mask, for example, is used to pattern the wafer surface and the wafer surface is then exposed to a beam of collimated UV light . The etch rate in those areas exposed with UV light is high and the selectivity can be 100:1 depending on the intensity of the light and the amount of hydrofluoric acid. In typical photo assisted etching, the UV light is perpendicular to the wafer surface. However, with respect to the present invention, the wafer is tilted in order to create a beveled edge that is angled within the critical angle for total reflection. For example, as previously discussed in reference to FIG. 17, a metal mask (not shown) is applied to the wafer surface and photo assisted etching is performed such that UV light 1430 is directed to the wafer surface so that the oxide layer is beveled at an angle X in relation to substrate 92 where angle X is within the critical angle for total internal reflection. As shown in FIG. 18, light from VCSEL 1425, shown by arrows 1427, enters the oxide layer which comprises wave guide 1404 and is reflected off of the beveled edge 1428 of the oxide layer and into a direction along wave guide 1404. The same process can also be used to create a beveled edge in the oxide layer directly beneath photodiode 1426 at the receiving end of wave guide 1404 in order to direct light 1427 from wave guide 1404 into photodiode 1426. For example, as shown in FIG. 18, an optical mirror is configured under photodiode 1426 by performing photo-assisted etch and directing UV light 1430 against the wafer surface to form a beveled edge 1429 in the oxide layer beneath photodiode 1426 thereby creating angle Y between the oxide layer which comprises wave guide 1404 and substrate 92 where angle Y is within the critical angle for total internal reflection. In FIG. 18, angle Y is a 45 degree angle which causes light 1427 to hit beveled edge 1429 and direct light 1427 into photodiode

1426.

It will be appreciated by those skilled in the art that other methods may be used to bevel the oxide layer such as reactive ion etching, gas etching with appropriate buffers, and other suitable wet etches although these methods may not be as desirable due to other effects.

Moreover, the structure and process for fabricating the optical system shown in FIG. 18, may include epitaxially depositing a monocrystalline oxide layer over substrate 92, epitaxially depositing monocrystalline compound semiconductor material 1424 over the monocrystalline oxide layer, and annealing the monocrystalline oxide layer to convert it to an amorphous oxide layer. Further, the annealing step may include, for example, the rapid thermal annealing of the monocrystalline oxide layer at a temperature between about 700° C and about 1000° C. In addition, the step of epitaxially growing the monocrystalline oxide layer may include growing a layer of Sr_xBa₁__xTi0₃ where x ranges from 0 to 1. The steps of epitaxially growing the monocrystalline oxide layer which forms wave guide 1404 and epitaxially growing compound semiconductor layer 1424 may be carried out by molecular beam epitaxy, chemical vapor deposition, physical vapor deposition, pulsed laser deposition and chemical solution deposition.

The formation of yet another exemplary embodiment of a monolithic optical system in accordance with the present invention is shown in cross section in FIGS. 19-23. A semiconductor substrate 92, described previously with reference to FIGS. 9-11 and 15-18, and also described as layer to in reference to FIGS. 1-3, functions as the base substrate. As shown in FIG. 19, an oxide layer 1902 is grown over substrate 92 and a monocrystalline compound semiconductor material 1904 is grown over oxide layer

1902. An edge emitting laser 1906 having a top 1908 and an edge 1910 is then formed in at least a portion of oxide layer 1902. Another oxide layer 1912 is grown over laser 1906 including top 1908 and edge 1910 of laser 1906 as shown in

FIG. 20. Oxide layer 1912 is then planarized as shown in

FIG. 21 to remove oxide from top 1908 of laser 1906.

Oxide layer 1912 is then etched on edge 1910 of laser 1906 at an angle within the critical angle for reflecting light from laser 1906 in a direction substantially perpendicular to substrate 92 as shown in FIG. 22. The etching step may include photo assisted etching, undercut etching, or any other suitable etching means for creating critical angle Z. For example, photo assisted etching may be performed as previously described in reference to FIGS. 17 and 18 using a wet etch such as sulfuric acid with a small amount of hydrofluoric acid in the presence of a collimated beam of UV light. As shown in FIG. 22, UV light 1925 is directed into oxide layer 1912 at a top edge of laser 1906 at a 45 degree angle in order to create critical angle Z, which is also a forty five degree angle, to direct light from laser 1906.

After etching oxide layer 1912, the resulting optical system 2300 is shown in FIG. 23. Optical system 23 includes substrate 92 underlying oxide layer 1902, edge emitting laser 1906 formed partially within monocrystalline compound semiconductor material 1904, and an optical mirror coupled to edge emitting laser 1906 in the form of an etched oxide layer 1912 to reflect light emitted from laser 1906, shown by arrow s 1927, in a direction substantially perpendicular to substrate 92. In addition, structure 2300 may include a photodetector 1929 in substrate 92 underlying the oxide layer 1912. As a result, light 1927 from laser 1906 contacts an edge 1930 of oxide layer 1912 which acts as a mirror. Light 1927 is then deflected down through oxide layer 1902 and into photodetector 1929 in substrate 92.

Oxide layers 1902 and 1912 may be monocrystalline oxide layers or amorphous oxide layers formed from a monocrystalline oxide layer. Oxide layers 1902 and 1912 , like the oxide layer forming wave guide 1404 previously discussed in reference to FIGS. 15-18, may include an oxide from the group including alkali earth metal • titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides. Preferably, oxide layers 1902 and 1912 include

where x ranges from 0 to 1. Further, optical structure 2300 may further include a laser control circuit and electrical feedback loop from the photodetector to the laser control circuit as described in reference to FIG. 13.

In the foregoing specification, the invention has been described with reference to specific embodiments.

However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense , and all such modifications are intended to be included within the scope of the present invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element (s) that may cause any benefit, advantage, solution to occur or become more pronounced are not to be constructed as critical, required, or essential features or elements of any or all of the claims. As used herein, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

CLAIMSWe claim:

1. An optical structure comprising;

a monocrystalline semiconductor substrate;

an oxide layer formed overlying the substrate;

a compound semiconductor light source formed in a monocrystalline compound semiconductor layer epitaxially grown overlying the oxide layer and capable of emitting a light output; and

a diffractive optical element configured to couple the light output from the light source into the oxide layer .

2. The structure of claim 1 wherein the monocrystalline semiconductor substrate comprises silicon.

3. The structure of claim 1 wherein the oxide layer comprises an oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

4. The structure of claim 3 wherein the oxide layer comprises Sr_xBa₁._xTi0₃ where x ranges from 0 to 1.

5. The structure of claim 1 wherein the light source comprises a device selected from the group consisting of lasers and light emitting diodes.

6. The structure of claim 5 wherein the light source comprises a vertical cavity surface emitting laser.

7. The structure of claim 6 wherein the vertical cavity surface emitting laser is configured to emit most of the light output in a direction toward the diffractive optical element .

8. The structure of claim 1 wherein the diffractive optical element comprises an optical grating etched in a surface of the oxide layer.

9. The structure of claim 8 wherein the optical grating is configured to diffract a portion of the light output having a specific wavelength in a predetermined direction.

10. The structure of claim 1 further comprising a photo detector formed in the monocrystalline compound semiconductor layer overlying the oxide layer.

11. The structure of claim 10 wherein the oxide layer is etched to form an optical wave guide in alignment with the light source and the photo detector and configured to conduct the light output from the light source to the photo detector.

12. The structure of claim 11 further comprising a second diffractive optical element configured to couple the light output from the optical wave guide to the photo detector.

13. The structure of claim 12 wherein the diffractive optical element and the second diffractive optical element each comprise an optical grating.

14. The structure of claim 11 wherein the optical wave guide is etched to form a plurality of optical wave guides emanating from and in alignment with the light source .

15. The structure of claim 14 wherein the diffractive optical element comprises an optical grating configured to diffract the light output into each of the plurality of optical wave guides.

16. The structure of claim 15 further comprising a light source control circuit formed in the substrate and coupled to the light source to control the light output .

17. The structure of claim 16 further comprising a photo detector aligned with one of the plurality of optical wave guides to receive a portion of the light output from the light source, the photo detector capable of producing an electrical signal in response to the portion of the light output received.

18. The structure of claim 17 further comprising an electrical connection from the photo detector to the light source control circuit capable of feeding back the electrical signal to the light source control circuit to control the light output .

19. The structure of claim 14 wherein the light source comprises a light source capable of emitting light comprising a plurality of wavelengths and the diffractive optical element comprises a plurality of diffraction gratings, each configured to diffract one of the plurality of wavelengths into one of the plurality of optical wave guides .

20. An optical structure comprising:

a monocrystalline semiconductor substrate;

an oxide layer formed overlying the substrate;

a light source formed at least partially in a monocrystalline compound semiconductor layer grown epitaxially overlying the oxide layer and capable of emitting a light output;

an optical wave guide formed overlying the substrate; and

an optical mirror configured to reflect the light output in a direction along the wave guide.

21. The optical structure of claim 20 wherein the oxide layer comprises a monocrystalline oxide layer.

22. The optical structure of claim 20 wherein the oxide layer comprises an amorphous oxide layer.

23. The optical structure of claim 20 wherein the optical mirror comprises a beveled edge formed on the oxide layer in alignment with the light source.

24. The optical structure of claim 23 wherein the light source comprises a vertical cavity surface emitting laser configured to emit the light output downwardly toward the oxide layer .

25. The optical structure of claim 23 wherein the beveled edge is angled at an angle within the critical angle for total internal reflection.

26. The optical structure of claim 20 wherein the oxide layer comprises an alkali earth metal oxide.

27. The optical structure of claim 20 wherein the oxide layer comprises an oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

28. The optical structure of claim 20 wherein the optical wave guide comprises an oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides .

29. The optical structure of claim 20 wherein the oxide layer comprises an oxide from the group consisting of the alkali-earth-metal zirconates and the alkali-earth- metal hafnates .

30. The optical structure of claim 29 wherein the compound semiconductor layer comprises a monocrystalline compound semiconductor material selected from the group consisting of InP and InGaAs.

31. The optical structure of claim 20 wherein the oxide layer comprises an. alkali earth metal titanate.

32. The optical structure of claim 31 wherein the compound semiconductor layer comprises a monocrystalline compound semiconductor material selected from the group consisting of GaAs, AlGaAs, ZnSe, and ZnSSe .

33. The optical structure of claim 20 further comprising:

a photo detector formed in the monocrystalline compound semiconductor layer overlying the oxide layer; and

a second optical mirror configured to reflect the light output from the wave guide to the photo detector.

34. The optical structure of claim 33 wherein the second optical mirror comprises a second beveled edge formed on the oxide layer in alignment with the photo detector.

35. The optical structure of claim 20 wherein the compound semiconductor light source comprises a device selected from the group consisting of lasers and light emitting diodes.

36. The optical structure of claim 20 further comprising

a photo detector formed in the monocrystalline semiconductor substrate;

37. The optical structure of claim 36 wherein the second optical mirror comprises a second beveled edge formed on the wave guide in alignment with the photo detector.

38. The optical structure of claim 20 wherein the optical wave guide comprises a first cladding layer having a first index of refraction, a core layer having a second index of refraction, and a second cladding layer having a third index of refraction.

39 . An optical structure comprising :

a monocrystalline semiconductor substrate having a surface ;

an oxide layer formed overlying the substrate surface;

an edge emitting laser formed at least partially in a monocrystalline compound semiconductor layer formed overlying the oxide layer; and

an optical mirror coupled to an emitting edge of the laser, the optical mirror configured to reflect light emitted from the laser in a direction substantially perpendicular to the surface of the substrate.

40. The optical structure of claim 39 wherein the oxide layer comprises an oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides.

41. The optical structure of claim 39 wherein the oxide layer comprises a monocrystalline oxide layer.

42. The optical structure of claim 39 wherein the oxide layer comprises an amorphous oxide layer formed from a monocrystalline oxide layer.

43. The optical structure of claim 39 wherein the oxide layer comprises Sr^a^JTiO., where x ranges from 0 to 1.

44. The optical structure of claim 39 wherein the optical mirror comprises a perovskite oxide deposited on the edge of the laser and etched to have a beveled edge angled at an angle of less than the critical angle.

45. The optical structure of claim 39 further comprising a photo detector formed in the substrate.

46. The optical structure of claim 45 wherein the optical mirror is configured to reflect light emitted from the laser in a direction to impinge upon the photo detector.

47. The optical structure of claim 45 further comprising:

a laser control circuit formed in the substrate; and

an electrical feedback loop from the photo detector to the laser control circuit.

48. A process for fabricating an optical structure comprising the steps of :

providing a monocrystalline semiconductor substrate;

forming an oxide layer having a surface overlying the substrate;

forming an optical grating in the surface of the oxide layer;

epitaxially depositing a layer of monocrystalline compound semiconductor material overlying the optical grating; and

forming a light source at least partially within the layer of monocrystalline compound semiconductor material.

49. The process of claim 48 wherein the step of forming a light source comprises photolithographically patterning the layer of monocrystalline compound semiconductor material in alignment with the optical grating.

50. • The process of claim 48 wherein the step of forming an optical grating comprises the step of etching a pattern in the surface of the oxide layer.

51. The process of claim 48 wherein the step of forming an optical grating comprises the step of forming a pattern of periodic impurity doping in the surface of the oxide layer.

52. The process of claim 51 wherein the step of forming a pattern comprises the step of ion implanting.

53. The process of claim 48 wherein the step of forming an oxide layer comprises the steps of :

depositing a first layer of monocrystalline oxide having a first index of refraction;

depositing a second layer of monocrystalline oxide overlying the first layer, the second layer characterized by a second index of refraction greater than the first index of refraction; and

depositing a third layer of monocrystalline oxide overlying the second layer, the third layer characterized by a third index of refraction less than the second index of refraction.

54. The process of claim 53 further comprising the step of photolithographically patterning the second layer to form a wave guide core having a predetermined pattern.

55. The process of claim 54 wherein the step of photolithographically patterning comprises photolithographically patterning the second layer to form a plurality of wave guide cores each having an end, and the step of forming an optical grating comprises forming a plurality of optical gratings, each of the plurality of optical gratings formed in alignment with a section of one of the plurality of wave guides .

56. The process of claim 55 wherein the step of forming a light source comprises photolithographically patterning the fourth layer aligned with and overlying the plurality of optical gratings .

57. The process of claim 53 wherein each of the steps of depositing a first layer, depositing a second layer and depositing a third layer comprise depositing a layer comprising Sr_xBa₁__xTi0₃ where x ranges from 0 to 1 by a process selected from the group consisting of molecular beam epitaxy, chemical vapor deposition, physical vapor deposition, pulsed laser deposition and chemical solution deposition.

58. The process of claim 57 wherein each of the steps of depositing a first layer, depositing a second layer and depositing a third layer further comprise doping the layer comprising Sr_xBa₁._xTi0₃ with an impurity to determine the refractive index.

59. The process of claim 53 wherein the step of forming an optical grating comprises forming an optical grating in the third layer.

60. The process of claim 59 wherein the step of forming an optical grating comprises the step of etching the surface of the oxide layer by a process of photo assisted etching.

61. The process of claim 48 further comprising the step of forming a photo detector device at least partially within the layer of monocrystalline compound semiconductor material .

62. The process of claim of claim 48 further comprising the step of forming a light source control circuit in the substrate.

63. The process of claim 62 further comprising the steps of:

forming a photo detector device at least partially within the layer of monocrystalline compound semiconductor material; and

forming an electrical interconnection between the photo detector device and the light source control circuit .

64. The process of claim 48 wherein the step of epitaxially depositing comprises the step of depositing a monocrystalline layer by a process selected from the group consisting of molecular beam epitaxy, chemical vapor deposition, physical vapor deposition, pulsed laser deposition and chemical solution deposition.

65. The process of claim 48 wherein the step of forming a light source comprises forming a vertical cavity surface emitting laser.

66 . The process of claim 48 wherein the step of forming a light source comprises forming a light emitting diode .

67. The process of claim 48 wherein the step of forming an oxide layer comprises the steps of:

epitaxially depositing a monocrystalline oxide layer; and

after the step of epitaxially depositing a layer of monocrystalline compound semiconductor material, annealing the monocrystalline oxide layer to convert the monocrystalline oxide layer to an amorphous oxide layer.

68. The process of claim 67 wherein the step of annealing comprises the step of rapid thermal annealing.

69. The process of claim 67 wherein the step of annealing comprises thermal annealing at a temperature between about 700° C and about 1000° C.

70. A process for fabricating an optical device comprising the steps of:

providing a monocrystalline substrate having a surface ;

epitaxially growing a first layer of monocrystalline oxide overlying the surface;

epitaxially growing a second layer of monocrystalline compound semiconductor material overlying the first layer;

forming a light emitting device at least partially in the second layer; and

etching the first layer at an angle to undercut the light emitting device.

71. The process of claim 70 wherein the step of providing a monocrystalline substrate comprises providing a monocrystalline semiconductor substrate comprising silicon.

72. The process of claim 71 wherein the step of epitaxially growing a first layer comprises growing an oxide selected from the group consisting of alkali earth metal titanates, alkali earth metal zirconates, alkali earth metal hafniates, alkali earth metal tantalates, alkali earth metal ruthenates, alkali earth metal niobates, and perovskite oxides by a process selected from the group consisting of molecular beam epitaxy, chemical vapor deposition, physical vapor deposition, pulsed laser deposition and chemical solution deposition.

73. The process of claim 71 wherein the step of epitaxially growing a first layer comprises growing a layer comprising SrBa^ iO_j where x ranges from 0 to 1.

74. The process of claim 70 wherein the step of epitaxially growing a second layer comprises growing a compound semiconductor layer by a process selected from the group consisting of molecular beam epitaxy, chemical vapor deposition, physical vapor deposition, pulsed laser deposition and chemical solution deposition.

75. The process of claim 70 wherein the step of etching comprises etching the first layer by the process of photo assisted etching.

76. The process of claim 75 wherein the step of etching comprises the steps of:

providing an opaque mask overlying the first layer; and

exposing the first layer to an etchant in the presence of a collimated light beam.

77. The process of claim 76 wherein the step of providing an opaque mask comprises providing a metal mask and the step of exposing the first layer to an etchant comprises exposing the first layer to an etchant comprising sulfuric acid and hydrofluoric acid.

78. The process of claim 76 wherein the step of exposing comprises exposing the first layer to an etchant in the presence of a collimated ultra violet light beam striking the first layer at an angle of about 45°.

79. The process of claim 70 further comprising the step of forming a photo detector device at least partially in the second layer .

80. The process of claim 79 further comprising the step of etching the first layer at an angle to undercut the photo detector device.

81. The process of claim 79 further comprising the step of etching the first layer to form a wave guide aligned with and extending from the light emitting device to the photo detector device.

82. The process of claim 70 further comprising the step of annealing the first layer after the step of epitaxially growing a second layer to convert the first layer of monocrystalline oxide to a layer of amorphous oxide .

83. A process for fabricating an optical device comprising the steps of :

providing a semiconductor substrate;

growing a first layer of perovskite oxide overlying the substrate;

growing a second layer of monocrystalline compound semiconductor material overlying the first layer;

forming an edge emitting laser at least partially in the second layer, the laser having a top and an edge;

growing a third layer of perovskite oxide overlying the laser including the top and the edge;

planarizing the third layer to remove the perovskite oxide from the top of the laser; and

etching the perovskite oxide on the edge of the laser at an angle within the critical angle.

84. The process of claim 83 wherein the step of etching comprises photo assisted etching.

85. The process of claim 83 wherein the step of etching comprises undercut etching.

86. The process of claim 83 wherein the step of etching comprises etching an upper surface of the perovskite oxide.

87. The process of claim 86 further comprising the step of forming a photo detector device in the substrate underlying the etched perovskite oxide .

88. The process of claim 83 wherein the step of growing a first layer comprises the step of growing a first monocrystalline layer.

89. The process of claim 88 further comprising the step of annealing the first monocrystalline layer to convert the first monocrystalline layer to an amorphous layer .