WO2002010914A1 - Procede de traitement de donnees - Google Patents

Procede de traitement de donnees Download PDF

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Publication number
WO2002010914A1
WO2002010914A1 PCT/IE2001/000089 IE0100089W WO0210914A1 WO 2002010914 A1 WO2002010914 A1 WO 2002010914A1 IE 0100089 W IE0100089 W IE 0100089W WO 0210914 A1 WO0210914 A1 WO 0210914A1
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WO
WIPO (PCT)
Prior art keywords
data word
data
bit
alu
processor
Prior art date
Application number
PCT/IE2001/000089
Other languages
English (en)
Inventor
Thomas Moore
Michael Byrne
Original Assignee
Delvalley Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/IE2001/000002 external-priority patent/WO2002010994A1/fr
Application filed by Delvalley Limited filed Critical Delvalley Limited
Priority to AU2001269394A priority Critical patent/AU2001269394A1/en
Publication of WO2002010914A1 publication Critical patent/WO2002010914A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE

Definitions

  • This invention relates to data processors and to a method of improving the processing speed of data processors and in particular to a method of processing two data words to provide a new data word in a processor comprising an arithmetic logic unit (ALU), a plurality of registers and access to memory.
  • ALU arithmetic logic unit
  • data processors contain an arithmetic logic unit (ALU), a plurality of registers having data words stored therein and access to memory.
  • ALU arithmetic logic unit
  • the ALU performs a variety of different arithmetic or logical operations on pairs of data words. These operations may include addition, subtraction, logical AND, OR, XOR, NAND, NOR and XNOR instructions. Quite often, several of these instructions will have to be completed in succession. Therefore, the time spent completing an operation of this type can be critical to overall processing speed.
  • certain applications do not require the use of an entire data word, but only the top or bottom half of such a data word. Often, it may be the case that the top half of one data word is to be computed with the bottom half of another data word.
  • the processor may be in an application processing packets of data received from an Ethernet local area network (LAN).
  • LAN Ethernet local area network
  • These packets of data contain addresses and further data and are often larger than the registers into which they are being placed. If, for instance, the length of an address is one and a half times the register width and there are contiguous registers with all bits used, then three registers would be required to store two addresses. The first address received would be put into a first register with the remainder placed in the top half of a second register and a second address received would be put into the bottom half of the second register and the remainder of the second address would fill a third register. It is clear then that to complete any calculations on either of the addresses, only half of the second register is required. The rest of the data in that register is surplus to requirements.
  • Another known way of achieving the correct alignment of the bit positions in the data words is to perform a series of rotational shift operations.
  • a bit is taken from one end of the data word, the remainder of the bits are shifted in the direction of the now empty bit position and the original bit is appended to the opposite end of the word from which it came.
  • MSB most significant bit
  • LSB now vacant least significant bit
  • the present invention is directed towards providing a processor which would be able to execute a single instruction that would complete all the necessary shift operations and any arithmetic or logic operations in a single clock cycle. This would result in a more efficient method of processing data as well as creating a more efficient data processor.
  • a method for processing two data words to provide a new data word in a processor comprising an arithmetic logic unit (ALU), a plurality of registers and access to memory characterised in that the method comprises, not necessarily in this order, the steps of:-
  • ALU arithmetic logic unit
  • the switching operation further comp rises the steps of:-
  • the upper and lower bit portions may be formed to be as close to equal if not equal in size as is possible. Alternatively, if a specific number of bits is required, then this also may be defined. The number of bits to be repositioned could depend largely on the field of application of the data processor and the various types of operations that must be performed by it. It can be seen that the above method, by simultaneously writing all the bits in both portions of the data words to the relevant portions of the mirror data word and performing an operation on the data word at the same time, significantly reduces the time taken to execute an instruction.
  • the data word's upper portion comprises bit (n-1) to bit (n/2) and it's lower portion comprises bit [(n/2)- 1] to bit 0 and the mirror data word's upper portion comprises bit (p-1) to bit (p/2) and it's lower portion comprises bit [(p/2)-1] to bit 0.
  • the data word will have an even number of bits.
  • one half of the data in a particular data word will be required. The above method enables operations to be carried out on both halves of the data word in an efficient manner with a minimum of difficulty.
  • the data word's upper portion comprises bit (n-1) to bit [(n-1)/2] and it's lower portion comprises bit ⁇ [(n-1)/2]-1 ⁇ to bit 0 and the mirror data word's upper portion comprises bit (p-1) to bit [(p+1)/2] and it's lower portion comprises bit [(p-1)/2] to bit 0.
  • the processor designates the upper portion of the data word as the larger of the two portions.
  • the lower portion of the mirror data word is designated as the larger portion for reception of this data word upper portion.
  • the lower portion of the data word and the upper portion of the mirror data word are assigned the same number of bits.
  • the lower portion of the data word and the upper portion of the mirror data word may be designated as the larger portion while the upper portion of the data word and the lower portion of the mirror data word are designated as the smaller portions. This choice will be entirely up to the designer and may be determined by the type of calculations that will be performed.
  • This static bit may preferably be the MSB, LSB or the central bit [(n-1)/2]. It may, in fact, be any chosen bit of the data word.
  • the switching operatio n performed on one of the data words is performed by using cross wiring techniques. This is seen as a most advantageous method of performing the invention.
  • the bits are switched automatically and practically instantaneously which negates the need for several instructions to be carried out and also reduces the processing time used to carry out that portion of the instruction. There is no extra logic required to perform the switching of the portions of the data word.
  • the data flows along a wiring path that has been cross-wired and is switched as it flows along that path.
  • the switching operation is performed on one of the data words using logic circuitry.
  • the logic circuitry in effect will perform the identical operation of the switching of the bits in the data word but will do so by performing a rotational shift operation on the data.
  • the result will be either the final result of the instruction or may be used for further processing but again it may all be achieved by a single instruction.
  • the switching operation is performed on one of the data words before an ALU operation is performed on that data word and another data word.
  • This type of instruction is called an X-type instruction. For instance, if the data required is in the top half of the operand that is to be operated on with a piece of data in the lower half of another operand, then we would perform a switching operation on the first operand to swap the upper and lower portions so that an operation could then be performed on the correctly aligned data words. Alternatively, it may be desirable to perform an operation on two data words and then perform a switching operation on the result.
  • This type of instruction is called an S-type instruction. This may be to correctly align the data for further processing or for presentation of the data in a particular manner.
  • the bitwise operations that these type of operations involve are AND, NAND, OR, NOR, XOR, XNOR, ADD and SUB resulting in ANDX, NANDX, ORX, NORX, XORX, XNORX, ADDX, SUBX, ANDS, NANDS, ORS, NORS, XORS, XNORS, ADDS and SUBS instructions.
  • an ANDS instruction would entail bitwise AND-ing two data words together followed by switching the upper and lower portions of the resulting data word.
  • a method of processing two data words to provide a new data word in a processor comprising an ALU, a plurality of registers and access to memory characterised in that the method comprises, not necessarily in this order, the steps of:-
  • the advantage of this above method is that the individual bits of the data word are switched as they are in transit to their destination and are not stored in any intermediate storage medium. By doing so, the switching operation is performed practically instantaneously and a logical operation or arithmetic operation may be performed in the same clock cycle.
  • the ALU operation may be performed after the switching operation in which case the end location of the data word is the ALU. Alternatively, the ALU operation may be performed before the switching operation in which case the start location of the data word is the result of the ALU operation.
  • a method of processing two data words, each having a plurality of bits, to provide a new data word in a processor comprising an ALU, a plurality of registers and access to memory characterised in that the method comprises the steps of:-
  • the data word is transmitted along a cross-wired pathway and is switched practically instantaneously before having an ALU operation performed on it. Uneven bit numbers as well as even may be handled in this way.
  • a method of processing two data words to provide a new data word in a processor comprising an ALU, a plurality of registers and access to memory characterised in that the method comprises the steps of:-
  • a data processor comprising an ALU, a plurality of registers and access to memory characterised in that the data processor comprises means to execute an instruction on two data words to provide a new data word, the means to execute an instruction comprising: -
  • (b) means to perform a switching operation on one of the data words.
  • the means to perform the switc hing operation further comprises :-
  • (c) means to separate the data word into an upper portion and a lower portion
  • (e) means to separate the mirror data word into an upper portion and a lower portion where the upper portion of the mirror data word is equal in size to the lower portion of the data word and the lower portion of the mirror data word is equal in size to the upper portion of the data word;
  • (f) means to copy the data in the upper portion of the data word into the lower portion of the mirror data word and write the data in the lower portion of the data word into the upper portion of the mirror data word;
  • the upper and lower bit portions may be formed to be as close to equal to, if not equal, as possible. If a particular number of bits is required to be switched, this may also be achieved. By switching the bits and performing an operation in this way, the processor can significantly decrease the time taken to run through a particular program.
  • a data processor in which when n is an even number, the data word's upper portion comprises bit (n-1) to bit (n/2) and it's lower portion comprises bit [(n/2)-1] to bit 0 and the mirror data word's upper portion comprises bit (p-1) to bit (p/2) and it's lower portion comprises bit [(p/2)- 1] to bit 0.
  • a data processor in which when n is an uneven number, the data word's upper portion comprises bit (n -1) to bit [(n-1)/2] and it's lower portion comprises bit ⁇ [(n-1)/2]-1 ⁇ to bit 0 and the mirror data word's upper portion comprises bit (p-1) to bit [(p+1)/2] and it's lower portion comprises bit [(p-1)/2] to bit 0.
  • the processor may be processing words of uneven bit number. If this is the case, then the processor may designate the upper portion of the data word and the lower portion of the mirror data word as the larger portions and the lower portion of the data word and the upper portion of the mirror data word as the smaller portions before any switching is carried out.
  • the larger portions will be 1 bit larger in size than the smaller portions, although this may be chosen, depending on the number of bits required by that particular operation.
  • the lower portion of the data word and the upper portion of the mirror data word may be designated as the larger portions, with the upper portion of the data word and the lower portion of the mirror data word as the smaller portions. This again will largely depend on the data required by a particular operation.
  • (h) means to designate a particular bit of the data word to act as a static bit and to write the static bit to the corresponding position in the mirror data word; and thereafter performing the separation and copying steps on the remainder of the bits of the data word and the mirror data word.
  • This static bit is written directly and then essentially is ignored for the rest of the switching process. The remaining bits are switched as if they were an even bit data word.
  • This static bit may be the MSB, LSB or the ce ntral bit [(n-1)/2]> In fact, it may be any chosen bit.
  • a data processor in which the means to perform the switching operation on one of the data words comprises cross-wiring techniques.
  • the word may be switched almost instantaneously allowing for further operations to be carried out within the same clock cycle and by using a single instruction, it reduces the number of instructions necessary as well as significantly speeding up the operation. There is no extra logic required to perform the switching of the portions of the data word.
  • a data processor in which the means to perform the switching operation on one of the data words comprises logic circuitry.
  • the switching operation may be performed by a rotational shift operation. This may require more circuitry than in the hardwiring case and essentially the same operation of switching around the bits of the data word is performed. Again, it has the advantage of being executable by a single instruction.
  • a processor in which the switching operation is performed on one of the data words before an ALU operation is performed on that data word and another data word. It may be necessary for the processor to perform the switching operation on one of the data words prior to carrying out an ALU operation on the data words.
  • This type of instruction is called an X-type instruction.
  • the processor may be required to perform an ALU operation on the two data words before a switching operation is performed on the result of the ALU operation. This type of operation is called an S-type instruction.
  • bitwise operations that these type of operations involve are AND, NAND, OR, NOR, XOR, XNOR, ADD and SUB resulting in ANDX, NANDX, ORX, NORX, XORX, XNORX, ADDX, SUBX, ANDS, NANDS, ORS, NORS, XORS, XNORS, ADDS and SUBS instructions.
  • ANDS instruction would entail logical AND-ing two data words together followed by switching the upper and lower portions of the resulting data word.
  • a data processor comprising an ALU, a plurality of registers and access to memory characterised in that the data processor comprises means to execute an instruction on two data words to provide a new data word, the means to execute an instruction comprising: -
  • cross-wiring means means to perform a switching operation on one of the data words in which the data word is separated into discrete portions and the order of the portions is rearranged by cross-wiring means, the cross-wiring means comprising:
  • a process of this type has the ability to perform the switching operation and the ALU operation in the same clock cycle.
  • a data word travelling down the cross-wired pathway will be automatically rearranged into the desired configuration when it arrives at its destination. This negates the need for two separate instructions.
  • the end location of the wiring pathway may be at the input of the means to perform an ALU operation in which case the data word is switched before the ALU operation or alternatively the start location of the wiring pathway may be at the end location of the means to perform an ALU operation in which case the ALU operation is carried out before a switching operation. It is seen as preferred to cross-wire the pathway in this manner.
  • a data processor comprising an ALU, a plurality of registers and access to memory characterised in that the data processor comprises means to execute an instruction on two data words to provide a new data word, the means to execute an instruction comprising: -
  • (c) means to deliver the other data word to the ALU along a cross-wired pathway in which the individual bits of the data word may be rearranged into a desired configuration before arriving at the ALU;
  • (d) means to perform an ALU operation on the two data words.
  • a data processor comprising an ALU, a plurality of registers and access to memory characterised in that the data processor comprises means to execute an instruction on two data words to provide a new data word, the means to execute an instruction comprising: -
  • (b) means to perform an ALU operation on the data words to produce a result data word
  • (c) means to deliver the result data word to a desired location along a cross-wired path in which the individual bits of the result data word may be rearranged into a desired configuration before reaching the desired location.
  • This processor will enable us to perform a switching operation subsequent to an ALU operation, both of which may be completed in the same clock cycle. Again, the cross- wiring of the pathway between the output of the ALU and the end destination is seen as a beneficial way of carrying out the invention.
  • the processor essentially comprises a design of a processor that is embodied in a computer program.
  • This program may be stored on a computer readable medium. This may include a floppy disk, CD-ROM or other similar record medium.
  • the computer program may be stored on a carrier signal. This may be either an electrical or an optical or a radio frequency carrier signal.
  • a computer program comprising program instructions for causing a computer to perform the method of the invention.
  • program instructions for causing a computer to perform the method of the invention.
  • a program code from which a processor will run.
  • These programs may be stored on a record medium such as computer readable medium.
  • This computer readable medium may be any of CD, floppy disk, DVD or the like.
  • the computer program may be embodied in ROM or embedded on an integrated circuit.
  • a computer program stored on a carrier signal.
  • This carrier signal may be an electrical carrier signal or an optical carrier signal or other type for transmitting signals across the internet.
  • a computer programmed to carry out the method of processing two data words to provide a new data word.
  • the computer itself may have software loaded thereon which will enable it to carry out the method as outlined above.
  • Fig. 1 is a block diagram of the processor according to the invention.
  • Fig. 2 is a flow diagram illustrating a method according to the invention
  • Fig. 3 is a block diagram of part of the method outlined in Fig. 2 showing an X instruction
  • Fig. 4 is a block diagram of part of the method outlined in Fig. 2 showing an S instruction
  • Fig. 5 is a flow diagram illustrating an alternative method according to the invention.
  • Fig. 6 is a block diagram illustrating the method of Fig. 5;
  • Fig. 7 is a block diagram illustrating switching using hardwiring
  • Fig. 8 is a block diagram illustrating a rotational shift operation; and Referring to the drawings and in particular to Fig. 1 , there is illustrated a block diagram of a processor according to the invention.
  • the processor indicated generally by the reference numeral 1 , comprises an ALU 2, a plurality of registers 3 and access to memory 4.
  • the processor is arranged to execute an instruction on two data words to provide a new data word according to the methods hereinafter described.
  • the switching circuitry 5 This is to provide the separation and the copying of one of the data words to a mirror data word which will be discussed in detail below.
  • a pair of data words of size n - bits are retrieved. These may have been retrieved from memory or from the registers or indeed from both the memory and the registers.
  • the processor determines the type of instruction to be executed, namely, whether it has received an X instruction or an S instruction. If an X instruction has been given, the method will proceed to step 13 where a mirror data word is generated.
  • the wires of the data word are cross-wired and connected directly to the ALU and the data word is switched as it passes along the wiring.
  • the mirror data word would in fact be a virtual data word and is created by the data flowing along the wiring.
  • th e mirror data word is separated into an upper portion and a lower portion.
  • one of the data words is separated into an upper portion and a lower portion.
  • the two portions are always separated in such a way that the upper portion of the data word is equal in size to the lower portion of the mirror data word and the lower portion of the data word is equal in size to the upper portion of the mi rror data word.
  • the write stage the upper portion of the data word is written to the lower portion of the mirror data word and the lower portion of the data word is written to the upper portion of the mirror data word.
  • the mirror data word is substituted for the data word. Of course, by substitution, it does not necessarily mean that the entire data word is overwritten by the mirror data word. It may be that the mirror data word will replace the data word or be used instead of it in a further calculation.
  • an ALU operation is performed on the other original data word and the switched data word to form a new data word. By using this method, both the switching operation and the ALU operation are completed in the same clock cycle by one instruction.
  • step 12 the processor determines that an S instruction is to be carried out, then the method will proceed to step 21 where an ALU operation is performed on the data words to produce another data word.
  • this ALU operation may comprise an AND, NAND, OR, NOR, XOR, XNOR, ADD or SUB instruction.
  • step 22 a mirror data word is generated and in step 23, the mirror data word is separated into an upper portion and a lower portion.
  • step 24 the data word created as a result of the ALU operation, the outcome data word, is separated into an upper portion and a lower portion.
  • step 25 the upper portion of the outcome data word is written to the lower portion of the mirror data word and the lower portion of the outcome data word is written to the upper portion of the mirror data word.
  • step 26 the mirror data word is substituted for the outcome data word.
  • substitution we do not necessarily mean the entire re-writing of the word but we can simply mean that the now switched form of the outcome data word rather than the outcome data word, will be the result of the instruction and will be used in any future stored memories or further calculations. This is achieved by cross-wiring the result of the ALU to the end destination of the data word.
  • FIG. 3 there are shown in block diagram form an X instruction and an S instruction respectively.
  • two data words 30 and 31 are to be operated on.
  • a mirror data word 32 is generated, the upper portion of the data word 30 is written to the lower portion of the mirror data word 32 and the lower portion of the data word 30 is written to the upper portion of the mirror data word 32.
  • the mirror data word is substituted for the data word and an ALU operation is carried out on the mirror data word 32 and the data word 31 producing a result data word 33.
  • the data word 30 may be cross-wired directly to the ALU so that the mirror data word is seen as a virtual data word on the hardwiring.
  • the data word is automatically switched as it travels along the wiring to the ALU.
  • an ALU operation is performed on two data words 35, 36 producing an outcome data word 37.
  • a mirror data word 38 of this outcome data word 37 is then generated and the relevant separation and writing stages are carried out on the outcome data word 37 and the mirror data word 38.
  • the mirror data word 38 is substituted for the outcome data word 37 as the result of the instruction.
  • the mirror data word may be the end location of the switched result of the ALU and the data word is switched by passing along a cross-wired pathway en route to the end destination of the data.
  • the upper and lower portions of both the data word and mirror data word may be equal in size if the number of bits n of the data word is an even number. If n is an uneven number, then one portion will be larger than the other portion in a data word.
  • the choice of which is the larger portion is up to the programmer and will be dictated largely by the data that is required for a particular operation. The important thing is that if the upper portion of the data word is chosen to be the larger portion, then the lower portion of the mirror data word must also be chosen as the larger portion and vice versa.
  • step 40 the data words are retrieved in the usual manner.
  • step 41 the processor determines whether an X or S instruction is to be carried out. If an X instruction is to be carried out, the method proceeds to step 42 where a mirror data word is generated.
  • step 43 a bit that has been preselected as a static bit is written from the data word to the corresponding bit position in the mirror data word.
  • the static bit may be any chosen bit but preferably one of either the MSB, LSB or central bit will be chosen.
  • the remainder of the mirror data word, excluding the static bit is separated into an upper portion and a lower portion.
  • the remainder of the data word, excluding the static bit is separated into an upper portion and a lower portion.
  • both the upper and lower portions are the same size but this need not be the case, as described above.
  • the upper portion of the data word must be the same size as the lower portion of the mirror data word and the lower portion of the data word must be the same size as the upper portion of the mirror data word.
  • step 46 the upper portion of the data word is written to the lower portion of the mirror data word and the lower portion of the data word is written to the upper portion of the mirror data word.
  • step 47 the mirror data word is substituted for the data word for the reasons already described and in step 48, an ALU operation is performed on the original data word and the other now switched data word to form a new data word. Again, with this method, both the switching and ALU operations can be performed using a single instruction which is of great benefit.
  • step 41 the processor is to perform an S instruction
  • the method will proceed to step 50 in which an ALU operation will be carried out on the two data words to produce an outcome data word.
  • step 51 a mirror data word is generated.
  • step 52 the predetermined static bit of the outcome data word is written to the corresponding bit position in the mirror data words.
  • step 53 the remainder of the mirror data words, excluding the static bit, is separated into an upper portion and a lower portion.
  • the outcome data word excluding the static bit, is separated into an upper portion and a lower portion.
  • step 55 the outcome data word's upper portion is written to the mirror data word's lower portion and the outcome data word's lower portion is written to the mirror data word's upper portion.
  • step 56 the mirror data word is substituted for the outcome data word as the result data word.
  • FIG. 6 there is shown a block diagram of an X instruction carried out according to the method outlined in Fig. 4.
  • two operands 60, 61 are retrieved in the normal manner.
  • a mirror data word 62 is generated.
  • the predetermined static bit 63 of the data word 60 is written directly to the corresponding bit position 65 in the mirror data word 62.
  • the MSB is shown as the static bit but equally well, it could be any chosen bit.
  • the remainder of the mirror data word 62, excluding the static bit 65 is separated into an upper portion and a lower portion.
  • the remainder of the data word 60, excluding the static bit 63 is separated into an upper portion and a lower portion.
  • the upper portion of the data word 60 is written to the lower portion of the mirror data word 62 and the lower portion of the data word 60 is written to the upper portion of the mirror data word 62.
  • the mirror data word 62 is substituted for the data word 60 for the purpose of further calculations and the ALU operation is then carried out on the data word 61 and the now switched original data word to produce a result data word 64.
  • the S instruction is carried out in a manner as previously described and it is not deemed necessary to show an S instruction for the current method.
  • Fig. 7 shows an example of cross-wiring techniques.
  • a data word indicated by the reference numeral 66 This data word contains a total of four bits and is separated into an upper portion and a lower portion, the upper portion containing bit 3 and bit 2 and the lower portion containing bit 1 and bit 0.
  • a mirror data word 67 also having a total of four bits separated into an upper portion [bit 3 and bit 2] and a lower portion [ bit 1 and bit 0].
  • the upper portion of the data word 66 is directly wired to the lower portion of the mirror data word 67, i.e.
  • bit 3 and bit 2 of the data word to bit 1 and bit 0 respectively of the mirror data word 67 and the lower portion of the data word 66 is directly wired to the upper portion of the mirror data word 67, i.e. bit 1 and bit 0 of the data word 66 to bit 3 and bit 2 respectively of the mirror data word 67.
  • bit 1 and bit 0 of the data word 66 to bit 3 and bit 2 respectively of the mirror data word 67 When a data word is loaded into the data word position 66, it will be automatically and practically instantaneously be written to the mirror data word 67 in a rearranged format. For example, if the bit sequence 1001 was written to data word position 66, the sequence '0110' would appear on the mirror data word. Due to the fact that this may be done in hardware, it is practically instantaneous and it enables us to speed up the processing speed and reduce the time it takes to execute an operation requiring such swapping.
  • Fig. 8 shows an example of a single rotational shift left operation.
  • a data word indicated generally by the reference numeral 70, having an MSB 71 and an LSB 72.
  • the processor When the processor is to perform a single rotational shift left operation, it takes the MSB from the end of the data word 70 and shifts the entire data up one position to the left. Once the shift operation has been completed, the MSB is placed in the now vacant LSB position.
  • a rotational shift operation may involve shifting several bit positions at the same time. This is achieved by using extensive logic gate circuitry (not shown) and a person well versed in the art would be able to reproduce such logic circuitry.
  • the designer does not have to produce a separate mirror word as such.
  • the logic circuitry and the data word work in conjunction with each other to perform the duties of a mirror data word.
  • the logic circuitry temporarily holds the data of one half of the word while the appropriate shift operations are carried out until it can be placed back into the data word.
  • the data word will then be ready for further calculations or operations as desired.
  • This logic circuitry may be combined with additional circuitry to perform the ALU operation of the data word thereby using only one instruction. This, as explained, is of substantial benefit to the designer and the ultimate user of such a method.
  • the processor described may not have been realised in silicon yet and may be in its design layout form in which case it may be embodied in a computer program.
  • This program may be stored on a carrier, for example, a computer readable medium or a carrier signal.
  • the MSB has been taken to mean the leftmost bit
  • the LSB has been taken to mean the rightmost bit in a piece of data.
  • the data adjacent the MSB has been named a s the upper portion
  • the data adjacent the LSB has been named the lower portion, it is understood that the data may be arranged having the MSB on the right-hand side of a piece of data and the LSB on the left-hand side and references to the upper and lower portions should be construed accordingly.
  • the invention also extends to computer programs, particularly computer programs on or in a carrier adapted for putting the invention into practice.
  • the code may be in source code, object code, or a code intermediate source and object code or any other form suitable for use in the implementation of the methods according to the invention.
  • the carrier may comprise a storage medium, for example, a ROM, CD or semiconductor, floppy disk or any other recording medium.
  • the carrier may be a transmissible carrier such as an electrical or an optical or radio signal which may be conveyed by an electrical or optical cable or any other means.
  • the carrier may be constituted by such means.
  • the carrier may also be an integrated circuit in which the program is embedded, the integrated circuit being adapted for performing or for use in the performance of relevant methods.

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Abstract

L'invention concerne un procédé qui permet de traiter deux mots de donnée afin de produire un nouveau mot de donnée dans un processeur. Elle concerne également un processeur servant à mettre en oeuvre ledit procédé, qui comprend une unité arithmétique logique, plusieurs registres et accès mémoire. Le procédé se caractérise en ce qu'il se met en oeuvre selon des étapes qui consistent, pas nécessairement dans l'ordre indiqué, à utiliser l'unité arithmétique logique pour effectuer une opération sur les mots de donnée afin de former un autre mot de donnée, puis à effectuer une opération de commutation sur un desdits mots de donnée. Ces deux étapes sont complétées par l'exécution d'une instruction simple, laquelle peut être réalisée en un cycle d'horloge, ce qui améliore la performance du processeur. Lesdites opérations de commutation peuvent être effectuées soit par des techniques de câblage, soit par un circuit de porte logique.
PCT/IE2001/000089 2000-07-28 2001-07-09 Procede de traitement de donnees WO2002010914A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001269394A AU2001269394A1 (en) 2000-07-28 2001-07-09 A method of processing data

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IE20000603 2000-07-28
IES2000/0603 2000-07-28
PCT/IE2001/000002 WO2002010994A1 (fr) 2000-07-28 2001-01-08 Processeur de donnees
IEPCT/IE01/00002 2001-01-08

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WO2002010914A1 true WO2002010914A1 (fr) 2002-02-07

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AU (1) AU2001269394A1 (fr)
WO (1) WO2002010914A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1866744A2 (fr) * 2005-04-08 2007-12-19 Icera Inc. Acces a des donnees et unite de permutation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171190A2 (fr) * 1984-07-09 1986-02-12 Advanced Micro Devices, Inc. Unité arithmétique et logique à fonction étendue
EP0718757A2 (fr) * 1994-12-22 1996-06-26 Motorola, Inc. Appareil et procédé pour effectuer l'arithmétique à 24 ainsi qu'à 16 bit
US5606677A (en) * 1992-11-30 1997-02-25 Texas Instruments Incorporated Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
GB2317467A (en) * 1996-09-23 1998-03-25 Advanced Risc Mach Ltd Input operand control in data processing systems
US5893145A (en) * 1996-12-02 1999-04-06 Compaq Computer Corp. System and method for routing operands within partitions of a source register to partitions within a destination register
WO2000068783A2 (fr) * 1999-05-12 2000-11-16 Analog Devices, Inc. Noyau de calcul de processeur de signaux numeriques

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171190A2 (fr) * 1984-07-09 1986-02-12 Advanced Micro Devices, Inc. Unité arithmétique et logique à fonction étendue
US5606677A (en) * 1992-11-30 1997-02-25 Texas Instruments Incorporated Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
EP0718757A2 (fr) * 1994-12-22 1996-06-26 Motorola, Inc. Appareil et procédé pour effectuer l'arithmétique à 24 ainsi qu'à 16 bit
GB2317467A (en) * 1996-09-23 1998-03-25 Advanced Risc Mach Ltd Input operand control in data processing systems
US5893145A (en) * 1996-12-02 1999-04-06 Compaq Computer Corp. System and method for routing operands within partitions of a source register to partitions within a destination register
WO2000068783A2 (fr) * 1999-05-12 2000-11-16 Analog Devices, Inc. Noyau de calcul de processeur de signaux numeriques

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1866744A2 (fr) * 2005-04-08 2007-12-19 Icera Inc. Acces a des donnees et unite de permutation

Also Published As

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