WO2002004968A3 - Support de vieillissement universel d'essai de puces de circuit integre - Google Patents

Support de vieillissement universel d'essai de puces de circuit integre Download PDF

Info

Publication number
WO2002004968A3
WO2002004968A3 PCT/US2001/020924 US0120924W WO0204968A3 WO 2002004968 A3 WO2002004968 A3 WO 2002004968A3 US 0120924 W US0120924 W US 0120924W WO 0204968 A3 WO0204968 A3 WO 0204968A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
socket
burn
circuit chip
different
Prior art date
Application number
PCT/US2001/020924
Other languages
English (en)
Other versions
WO2002004968A2 (fr
Inventor
Rafiqul Hussain
Phuc Dinh Do
Benjamin G Tubera
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2001271717A priority Critical patent/AU2001271717A1/en
Publication of WO2002004968A2 publication Critical patent/WO2002004968A2/fr
Publication of WO2002004968A3 publication Critical patent/WO2002004968A3/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G01R1/0483—Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

L'invention concerne un appareil et un procédé d'essai de différents modèles de puces de circuit intégré de différentes dimensions sur le même support de vieillissement. L'ouverture d'un support de vieillissement est modifiée par des structures de différente forme pouvant être fixées au support de vieillissement puis retirées de celui-ci. Les différentes structures permettent d'adapter le support de vieillissement pour l'essai de différents modèles de puces de circuit intégré, chaque structure différente étant associée à un modèle de puce de circuit intégré spécifique. Une structure fixée, spécifique à un modèle de circuit intégré, guide et aligne une puce de circuit intégré sur le support de vieillissement de façon que les contacts électriques de la puce du circuit intégré soient connectés à un sous-ensemble sélectionné de fiches de contact du substrat (12) de vieillissement.
PCT/US2001/020924 2000-07-12 2001-06-29 Support de vieillissement universel d'essai de puces de circuit integre WO2002004968A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001271717A AU2001271717A1 (en) 2000-07-12 2001-06-29 Universal burn-in socket for testing integrated circuit chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61472900A 2000-07-12 2000-07-12
US09/614,729 2000-07-12

Publications (2)

Publication Number Publication Date
WO2002004968A2 WO2002004968A2 (fr) 2002-01-17
WO2002004968A3 true WO2002004968A3 (fr) 2003-11-06

Family

ID=24462474

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/020924 WO2002004968A2 (fr) 2000-07-12 2001-06-29 Support de vieillissement universel d'essai de puces de circuit integre

Country Status (2)

Country Link
AU (1) AU2001271717A1 (fr)
WO (1) WO2002004968A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011015815B4 (de) * 2011-04-01 2014-02-13 Yamaichi Electronics Deutschland Gmbh Testkontaktor mit veränderlicher Bauteilaufnahme, Verwendung und Verfahren
US8535956B2 (en) 2012-02-14 2013-09-17 International Business Machines Corporation Chip attach frame
CN109471017A (zh) * 2018-11-23 2019-03-15 昆明理工大学 一种基于单片机控制的78xx系列芯片型号检测电路及方法
CN112269123B (zh) * 2020-10-16 2023-03-14 天津津航计算技术研究所 通用可配置的芯片测试电路
CN116224039B (zh) * 2023-01-06 2023-10-27 法特迪精密科技（苏州）有限公司 一种芯片温度循环老化测试台的降温插座

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5745346A (en) * 1995-06-08 1998-04-28 Shin-Etsu Polymer Co., Ltd. Connecting socket for a semiconductor package
US5989039A (en) * 1997-06-25 1999-11-23 Lg Semicon Co., Ltd. Socket apparatus for testing package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5745346A (en) * 1995-06-08 1998-04-28 Shin-Etsu Polymer Co., Ltd. Connecting socket for a semiconductor package
US5989039A (en) * 1997-06-25 1999-11-23 Lg Semicon Co., Ltd. Socket apparatus for testing package

Also Published As

Publication number Publication date
WO2002004968A2 (fr) 2002-01-17
AU2001271717A1 (en) 2002-01-21

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