WO2002003448A1 - Procede pour determiner la profondeur d'une jonction p-n au silicium - Google Patents

Procede pour determiner la profondeur d'une jonction p-n au silicium Download PDF

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Publication number
WO2002003448A1
WO2002003448A1 PCT/AM2001/000001 AM0100001W WO0203448A1 WO 2002003448 A1 WO2002003448 A1 WO 2002003448A1 AM 0100001 W AM0100001 W AM 0100001W WO 0203448 A1 WO0203448 A1 WO 0203448A1
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WO
WIPO (PCT)
Prior art keywords
silicon
anodic
junction
determination
junction depth
Prior art date
Application number
PCT/AM2001/000001
Other languages
English (en)
Inventor
Gagik Ayvazyan
Aram Vardanyan
Gagik Makaryan
Original Assignee
Gagik Ayvazyan
Aram Vardanyan
Gagik Makaryan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gagik Ayvazyan, Aram Vardanyan, Gagik Makaryan filed Critical Gagik Ayvazyan
Priority to AU2001228167A priority Critical patent/AU2001228167A1/en
Publication of WO2002003448A1 publication Critical patent/WO2002003448A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Definitions

  • the present invention relates to semiconductor technology and may be used for determination of silicon P-N junction depth, in particular, for epitaxial and diffusion structures.
  • the object of this invention is to increase precision and productivity of the method of determining the silicon P-N junction depth.
  • anodic treatment is carried out in volt-static regime of porous silicon formation in P-type silicon before the mechanical opening of P-N junction, and is stopped when anodic current reduces to zero.
  • PS Porous silicon
  • Y.S. Tsou Y. Xiao
  • P-type silicon has enough quantity of holes, therefore PS formation takes place at the low anodic voltage ( ⁇ 5 V).
  • anodic current with density of order 10 mA/cm 2 flow through system silicon - electrolyte.
  • N-type silicon has tiny quantity of holes, therefore PS formation takes place at higher anodic voltage (over 10 V) and in conditions of additional external influences (light, mechanical stress).
  • the layer of PS has obvious dark-brown color that's why we can easily distinguish it from crystalline silicon. It gives opportunity to distinguish precisely the porous P-region from the N-region after mechanical opening of P-N junction with the help of microscope.
  • FIGS. 1-3 are schematic sectional view for explaining the steps of a method determination of P-N junction depth in accordance with our invention. Best Mode for Carrying out the Invention
  • FIG. 1 the N- type silicon wafer 1 1 with a P- type epitaxial or diffusion layer 12 on one surface, is presented.
  • the structure wafer-layer is provided with flat, smooth opposing top and back surfaces.
  • epitaxial silicon structures were used.
  • epitaxial layers with different thickness 2.5-60.0 ⁇ m and resistivity 1.5-7.5 Om-cm were grown on silicon wafers with resistivity 0.01 Om.cm.
  • the P- type layer 12 is changed to PS layer 21 by an anodic treatment using an electrolyte containing hydrofluoric acid.
  • an electrolyte containing hydrofluoric acid typically the wafer is first inserted within a suitable holding device and then immersed within the electrolyte. During immersion the wafer acts as an anode and a conductive member which is likewise inserted within the electrolyte but is not readily dissoluble therein acts as a cathode.
  • anodic voltage is applied there between a reaction takes place causing gradual deep pore formation on the side wafer exposed to the electrolyte.
  • anodic treatment was carried out from the P- type layer side in a volt-static regime on the anodic treatment holding device, with the help of potentiostat.
  • an electrolyte a solution of hydrofluoric acid (48%) and ethyl eneglycol, taken in proportion of 1 :3, was used.
  • Anodic voltage was 2.5 V, and anodic current - 20-30 mA/cm 2 .
  • the treatment was stopped as anodic current reduced to zero (it was controlled by the amperemeter of the potentiostat). Duration of anodic treatment was ranging between a few seconds up to 45 sec, depending on thickness of epitaxial layer. The above-mentioned conditions are typical for formation of only PS P-type silicon.
  • FIG. 3 The next operation, FIG. 3, was mechanical opening.
  • Mechanical opening of the P-N junction 31 was carried out on the dimpling apparatus for forming a sloping section.
  • As an abrasive material the paste of 1-2 ⁇ m granulation was used. Duration of mechanical opening did not exceed 4 min.
  • Topographic contrast of interface epitaxial layer (PS) - wafer 32 was evaluated with optic microscope.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

L'invention a trait à la technologie des semi-conducteurs. Le procédé comporte les étapes consistant à : mettre en oeuvre un traitement anodique de surface de silicium sous un régime de tension statique de formation de silicium poreux dans du silicium de type P, avant l'ouverture mécanique de la jonction P-N ; et interrompre le traitement anodique quand le courant anodique atteint zéro.
PCT/AM2001/000001 2000-07-04 2001-01-10 Procede pour determiner la profondeur d'une jonction p-n au silicium WO2002003448A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001228167A AU2001228167A1 (en) 2000-07-04 2001-01-10 Method of determination of silicon p-n junction depth

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AM20000060 2000-07-04
AMP20000060 2000-07-04

Publications (1)

Publication Number Publication Date
WO2002003448A1 true WO2002003448A1 (fr) 2002-01-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AM2001/000001 WO2002003448A1 (fr) 2000-07-04 2001-01-10 Procede pour determiner la profondeur d'une jonction p-n au silicium

Country Status (2)

Country Link
AU (1) AU2001228167A1 (fr)
WO (1) WO2002003448A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2599756A1 (fr) 2011-12-01 2013-06-05 W. R. Grace & Co.-Conn Composition et procédé permettant d'obtenir des agrégats exposés dans les surfaces en béton moulé et autres matériaux cimentaires

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU522462A1 (ru) * 1974-12-20 1976-07-25 Московский Институт Электронной Техники Миэт Способ измерени глубины слоев монокристаллического полупроводника
SU658626A1 (ru) * 1976-07-02 1979-04-25 Минский радиотехнический институт Способ электролитического анодировани
DD285436A5 (de) * 1989-06-28 1990-12-12 Veb Halbleiterwerk Kombinat Mikroelektronik,Dd Verfahren und vorrichtung zur lateralen und vertikalen schichtdickenkontrolle

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU522462A1 (ru) * 1974-12-20 1976-07-25 Московский Институт Электронной Техники Миэт Способ измерени глубины слоев монокристаллического полупроводника
SU658626A1 (ru) * 1976-07-02 1979-04-25 Минский радиотехнический институт Способ электролитического анодировани
DD285436A5 (de) * 1989-06-28 1990-12-12 Veb Halbleiterwerk Kombinat Mikroelektronik,Dd Verfahren und vorrichtung zur lateralen und vertikalen schichtdickenkontrolle

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2599756A1 (fr) 2011-12-01 2013-06-05 W. R. Grace & Co.-Conn Composition et procédé permettant d'obtenir des agrégats exposés dans les surfaces en béton moulé et autres matériaux cimentaires
WO2013079969A1 (fr) 2011-12-01 2013-06-06 W.R. Grace & Co.-Conn Composition et procédé pour obtenir des agrégats exposés dans des surfaces de béton moulé et d'autres matériaux cimentaires

Also Published As

Publication number Publication date
AU2001228167A1 (en) 2002-01-14

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