Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/64—Hybrid switching systems
  • H04L12/6418—Hybrid transport

Definitions

• This invention relates to a method for transferring data between a circuit switched environment wherein data is transmitted in recurrent frames, each frame comprising a plurality of time slots, each time slot defining at least a part of a channel, and a packet switched environment, wherein data is transmitted in packets.
• the invention also relates to a corresponding apparatus.
• the communication system comprises a plurality of nodes interconnected by communication media, such as optical fibers or other appropriate media, in one or more communication networks.
• One and the same node may be connected to transfer data between the circuit switched environment and the packet switched environment, wherein the data has to be rearranged within the node.
• the said environments may have different extension.
• the packet switched environment can be substantially external to the node, such as an Ethernet to which the node is connected, or substantially internal, such as where the node has a kernel operating according to a protocol for packet switching.
• data is transmitted in recurrent frames comprising a plurality of time slots, each time slot within a frame generally being associated with a specific channel.
• Each time slot typically comprises eight or sixty-four bits.
• the data can be transmitted in accordance with the DTM protocol (DTM - Dynamic Synchronous Transfer Mode, see e.g.
• data is rather transmitted in packets or packet fragments, each thereof generally comprising a plurality of bytes of data.
• the data may be transmitted in accordance to the TCP/IP protocol or any other appropriate protocol.
• An apparatus which is provided in a node or embodies a node, and wherein data is rearranged for transfer between the packet switched and the circuit switched environments, comprises a first interface providing access to the circuit switched environment and a second interface providing access to the packet switched environment. What is of particular interest is to study the transfer of incoming data to the circuit switched environment .
• a prior art apparatus containing a plurality of ports, data received at the apparatus via the first interface and via the second interface to be transmitted in the circuit switched environment are received at input ports and buffered in input buffers. The input ports obtain information regarding which ports the data are to be forwarded to for transmission and put them on an internal bus.
• the data arrive over the bus in an arbitrary order and are written slot by slot into a frame memory in correct order.
• a frame has been completed in the frame memory, it is transmitted.
• This prior art apparatus works well, however delays the data while transferring it. It would be desirable to decrease that delay.
• the object of this invention is to provide a method and an apparatus for transferring data between a circuit switched environment and a packet switched environment, which method and apparatus decreases the above-described data delay introduced when data are transferred for transmission in the circuit switched environment.
• a method for transferring data between a circuit switched environment wherein data is transmitted in recurrent frames, each frame comprising a plurality of time slots, each time slot defining at least a part of a channel, and a packet switched environment, wherein data is transmitted in packets said method comprising the steps of:
• an apparatus in a communication system comprising: - a first interface connecting to a circuit switched environment, wherein data is transmitted in recurrent frames, each frame comprising a plurality of time slots, each time slot defining at least a part of a channel; - a second interface connecting to a packet switched environment, wherein data is transmitted in packets;
• the sequential fetching is enabled by creating the bypass queue and the channel queues.
• the bypass queue slots received from the circuit switched environment are temporarily queued in the received order, which is the same as the order in which they are to be transmitted.
• the channel queues the data packets received from the packet switched environment are queued channel by channel, where each channel typically is defined by a different set of one or more time slots of a frame, the queued data then being ready to be fetched for direct transmission.
• Fig. 1 is a schematic block diagram of an apparatus according to an embodiment of the present invention.
• Fig. 2 and 3 respectively shows different mapping tables employed in the embodiment of Fig. 1.
• the apparatus logically comprises a first interface 3 and a second interface 5.
• the first interface 3 interfaces the apparatus to a circuit switched environment and the second interface 5 interfaces the apparatus to a packet switched environment, such as an Ethernet, wherein said environments have been described above.
• the first interface 3 has an input 7 and an output 9 connected to the circuit switched environment via an electro-optical transducer 11, and the second interface 5 has an input 13 and an output 15 connected to the packet switched environment, possibly via an electro-optical transducer 17.
• the packet switched environment may be external to a node as well as internal to a node, as will be further described below.
• the apparatus further comprises a packet retriever 19 connected between the first interface 3 and the second interface 5 for packeting input data before forwarding it to a packet transmitter means 21 of the second interface 5. Since the present invention is not particularly focused on the processing of input data to be transmitted in the packet switched environment, the packet retriever and the packet transmitter means will not be further described. They could be implemented by means of any conventional technology which is useable, as known by the skilled man.
• the first interface 3 comprises a receiver means 23 to which the input 7 is connected, a transmitter means 25 to which the output 9 is connected, a bypass queue 27 and a synchronisation unit 29, below referred to as the sync unit .
• the receiver means 23 comprises a decoder 31 connected to the input 7 and a slot-to-channel mapping means 33, having an input connected to a first output of the decoder 31, a first output connected to the packet retriever 19, and a second output connected to the bypass queue 27.
• a second output of the decoder is connected to the sync unit 29.
• the transmitter means 25 comprises an encoder 35 having an output connected to the output 9 of the first interface 3, and a channel-to-slot mapping means 37, having an output connected to the encoder 35, having a first input connected to the bypass queue 27 and having a second input connected to the sync unit 29.
• the sync unit 29 is further connected to the slot-to-channel mapping means 33.
• the data path from the packet switched environment to the circuit switched environment is ended with the channel-to-slot mapping means 37 and the encoder 35.
• Said data path further comprises a packet receiver means 39, comprised in the second interface 5, a plurality of channel queues 41, connected to the packet receiver means 39, and a fetching means 43, interconnecting the plurality of channel queues 41 and the channel-to-slot mapping means 37.
• data is transferred through the apparatus described above as follows. The operation of data transfer will be exemplified for a circuit switched environment where data is transmitted in accordance to a DTM protocol and where 64 bit time slots are transmitted encoded into 80 bits using 8bl0b encoding.
• the packet receiver 39 When data is received in packets from the packet switched environment it is received at the packet receiver 39.
• the packet receiver 39 separates the packet data into channels and queues the data in the respective channel queues 41.
• queue is meant any appropriate means for queuing data, such as for example a stack, a memory or a table.
• Data which is received from the circuit switched environment is received at the receiver means 23, which determines, on basis of control information whether said data is to be forwarded to the packet retriever 19 or to the bypass queue 27, and forwards the slot accordingly.
• the control information is held within the apparatus in connection with the receiver means 23 and, for each slot position of the recurrent frame, indicates whether the slot is to be transmitted on the packet switched environment or the circuit switched environment .
• the incoming bitstream is received at the decoder 23.
• the decoder is an 8bl0b-decoder, i.e. data, which is received in the expanded coding of 80 bits per slot, is decoded on a per block basis. That is, blocks of 10 bits are decoded into blocks of 8 bits so as to process the slots within the apparatus in the standard 64 bit format.
• the decoder 23 Prior to the very decoding operation the decoder 23 has demultiplexed the data into a parallel format. Further, in the decoder 23 a sync signal is detected and forwarded to the sync unit 29, which in turn provides sync signals to the slot-to-channel mapping means 33 and to the channel-to-slot mapping means 37 respectively.
• Data is then output, in a slot delimited sense, from the decoder 23 to the slot-to-channel mapping means 33, which maps the data of each slot to a respective channel queue based on the position thereof in the incoming DTM frame.
• Each channel is defined by an individual channel number (LCI) .
• An example of a slot-LCI mapping table is shown in Fig. 2. As illustrated in Fig. 2, the table has a respective entry for each slot in the DTM frame . Each entry holds the LCI that the slot belongs to.
• the slot-to-channel mapping means 33 then provides each slot in conjunction with information of the channel number to the packet retriever 19 for further processing.
• the slot-to-channel mapping means 33 In the case that an entry holds a particular predetermined bypass value, which does not correspond to any channel, the slot-to-channel mapping means 33, rather than forwarding the slot to the packet retriever 19, writes that slot into the bypass queue 27. Consequently, the bypass queue 27 is arranged for queuing those data received in a particular slot at the input 7 of the first interface 3 that are to be transmitted in the same particular slot at the output 9 of the first interface 3. In other words, data received from the circuit switched environment to be retransmitted in the same circuit switched environment is temporarily held in the bypass queue 27.
• This bypassing of data from the input 7 to the output 9 of the first interface is particularly used when the input 7 and the output 9 are connected to one and the same multi-access link, such as a ring or a bus, which typically connects to upstream as well as downstream nodes.
• a multi-access link such as a ring or a bus
• the transmitter means 25 sequentially fetches, slot by slot, the queued data in the same order as said slots are to be arranged in the frame. For each slot the transmitter means 25 determines, on basis of control information to fetch the slot from the bypass queue 27, or from one of the channel queues 41, or, in case said queues are empty, determines to transmit an idle marked slot.
• the control information is held in connection with the transmitter means 25 and, for each slot position of the recurrent frame, indicates from where the slot is to be fetched.
• the output frame can be regarded as being built and forwarded for transmission from start of frame to end of frame u on the fly", in contrast to the prior art, where an entire frame has to be assembled within the apparatus before the transmission thereof is begun.
• the channel-to-slot mapping means 37 looks up the slot number of the slot, which is to be transmitted, in a slot-LCI table.
• This slot-LCI table is of the same type as the one shown in Fig. 2 , but valid for the outgoing bitstream rather than for the incoming bitstream.
• Each entry of the table holds an identifier, which identifies one out of a group of sources of slot contents comprising at least said channel queues and said bypass queue.
• the data for that slot will be read by the channel-to- slot mapping means 37 from the bypass queue. If not, the channel number obtained from the slot-LCI table is input to the fetching means 43.
• the fetching means 43 enters the received LCI into a LCI-channel queue table, as is illustrated in Fig. 3.
• the LCI-channel queue table has a respective entry for each LCI. Each entry holds inter alia a channel queue address of a channel queue associated with the LCI in question. At the channel queue address of the entered LCI the slot data for the above mentioned slot, which is to be transmitted, is stored.
• the current slot data is then passed to the channel-to- slot mapping means 37, which in turn forwards the slot data to the encoder 35.
• the encoder 8bl0b encodes the slot, serialises the encoded bits and transmits the resulting bitstream by the output 9 and via the electro- optical transducer 11 in the circuit switched environment .

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Data Exchanges In Wide-Area Networks (AREA)

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Cited By (2)

Citations (5)

• 2000
  • 2000-04-13 SE SE0001386A patent/SE0001386L/sv not_active Application Discontinuation
• 2001
  • 2001-03-30 WO PCT/SE2001/000695 patent/WO2001080503A1/en active Application Filing
  • 2001-03-30 AU AU2001244969A patent/AU2001244969A1/en not_active Abandoned

Patent Citations (5)

Non-Patent Citations (1)

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