WO2001070517A1 - Decapage ultra-rapide pour resine photosensible endommagee - Google Patents

Decapage ultra-rapide pour resine photosensible endommagee Download PDF

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Publication number
WO2001070517A1
WO2001070517A1 PCT/US2001/005822 US0105822W WO0170517A1 WO 2001070517 A1 WO2001070517 A1 WO 2001070517A1 US 0105822 W US0105822 W US 0105822W WO 0170517 A1 WO0170517 A1 WO 0170517A1
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WO
WIPO (PCT)
Prior art keywords
wafer
plasma
stripping
sub
photoresist
Prior art date
Application number
PCT/US2001/005822
Other languages
English (en)
Inventor
Wayne L. Johnson
Original Assignee
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Priority to AU2001247226A priority Critical patent/AU2001247226A1/en
Priority to US10/204,263 priority patent/US6767698B2/en
Publication of WO2001070517A1 publication Critical patent/WO2001070517A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
    • C23C14/564—Means for minimising impurities in the coating chamber such as dust, moisture, residual gases
    • C23C14/566—Means for minimising impurities in the coating chamber such as dust, moisture, residual gases using a load-lock chamber
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/427—Stripping or agents therefor using plasma means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67751—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber vertical transfer of a single workpiece
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H01J2237/3342—Resist stripping

Definitions

  • the present invention is directed to a method and system for removing ion implanted photoresist, and more particularly to a method and system for effectively stripping a photoresist layer damaged by high dose ion implantation.
  • Photoresist has been used in the fabrication of very large-scale integrated (VLSI) circuits for years. It works as a masking material for shielding ion implantation in selected areas, and transferring patterns into various layers (e.g., oxide, nitride, polysilicon and metals). After ion implantation or pattern transfer is carried out, the photoresist layer needs to be removed completely. Generally, the removal of photoresist, also called stripping or ashing, is performed in a plasma containing (high amounts of) oxygen. The oxygen atoms react with the C (carbon) and H (hydrogen) in the photoresist, forming volatile products that are then exhausted from the system.
  • VLSI very large-scale integrated
  • polymers or other materials generated in the process can deposit onto the sidewalls of the photoresist pattern or etched features and form "veils" along the pattern edges that generally require both dry stripping and wet processing to remove.
  • those crust layers or "veils " will be left on the wafer surface as residues after ashing.
  • US Patent No. 5.478.403 (Shinagawa et al.. 1995) introduces an apparatus for resist ashing applications.
  • the apparatus uses a microwave source to generate the oxygen- containing plasma.
  • the microwave-generated plasma is introduced to a downstream process chamber, through a plasma-transmitting plate, to where the resist coated wafer is to be treated.
  • the microwave is efficient in generating oxygen radicals
  • the ions in the plasma may have high ion energy and cause charge damage and contamination if in direct contact with the wafer surface. Those ions must be eliminated from the flux on their way from the plasma source to the wafer substrate.
  • the transmitting plate captures charged particles in the plasma while allowing the transmission of neutral active species to thereby ash the photoresist coating without accumulating charges on the wafer surface.
  • the wafer is placed on a chuck that is capable of adjusting its position to vary the distance between the wafer and the plasma transmitting plate.
  • the problem of stripping high-dose ion-implanted photoresist when the above mentioned microwave source and charge-trapping plate are used, is that the oxygen radicals arriving at the wafer surface are not very effective in removing the carbonized crusted skin of the resist coating.
  • the skin layer tends to crack due to stress and softening of the underlying uncarbonized resist, and the oxygen radicals penetrating through those cracks can react with the underlying "soft" resist at a very high rate.
  • the volatile products generated from ashing the underlying "soft" resist layer will cause the hardened skin layer to crack even further and eventually break into many small pieces. This is generally referred to as "resist popping." Those small pieces of hardened resist skin will stick on the substrate surface and become very difficult to be removed completely by oxygen radicals, even with long overetching time.
  • the first step is performed in a parallel plate RIE (reactive ion etching) mode reactor and second step in a microwave downstream asher, as shown in Figure 2.
  • RIE reactive ion etching
  • the problem with this approach is that a parallel plate RIE mode reactor has a high electron temperature and high ion energies which may cause charge and lattice damage as well as contamination to the substrate.
  • US Patent No. 5,773,201, (Fujimura et al.) describes a process that adds water vapor into oxygen to create the ashing gases. The addition of water vapor lowers the activation energy of the ashing reaction and increases the reaction species, thus increasing the ashing rate and decreasing the process temperature.
  • the ashing rate in the disclosure is only about 3000 A min.
  • Savas describes a resist stripping system that utilizes an inductively coupled plasma source with a Faraday shield to reduce RF capacitive coupling to the plasma.
  • the nearly pure inductive coupling nature reduces the plasma potential.
  • the use of high pressure ( ⁇ 1 Torr) and low RF power level ( ⁇ 1 W/cc) produces a plasma with high dissociation and low ionization.
  • this source provides high resist stripping rate but very low charge damage.
  • the wafer temperature is kept high (e.g., between 200°C - 250°C).
  • the system has a potential resist popping problem when used for stripping ion implanted photoresist because of the high wafer temperature.
  • a low processing temperature is used to prevent resist popping, the ashing rate is compromised, resulting in lower throughput.
  • the first stripping step uses a combination of radical and controllable low energy ion-assisted etching of the carbonized layer using low processing temperature.
  • the second stripping step uses high concentration oxygen radical ashing to strip the soft resist at a high processing temperature.
  • the ESRF source is able to produce a plasma with adjustable dissociation and ionization rates. When operating at relatively high pressure (e.g., 1 Torr) and low power (e.g.. 1 W/cc), it produces high dissociation rate and low ionization rate. The ionization rate increases as the power increases and the pressure decreases.
  • the degree of capacitive coupling of the RF power to the plasma, and thus the plasma potential can be adjusted.
  • the plasma potential is raised higher, the ion bombardment of the chamber wall and the wafer substrate increases.
  • the bias level is high, the plasma potential becomes high and ion bombardment to the chamber wall increases. This can be used as a method to clean the chamber inside surface periodically without opening the chamber, resulting in prolonged time between chamber wet clean and higher overall system uptime.
  • the plasma potential is increased slightly and a small amount of ions, along with radicals, can be introduced to the wafer surface. This phenomenon can be utilized in the first processing step to assist in the removal of the hardened skin layer.
  • Figure 1 is a cross-section of a microwave system from U.S. Patent Number 5.478.403:
  • Figure 2 is schematic illustration of a two-chamber system disclosed in U.S. Patent Number 4.861.424.
  • FIG. 3 is a top view of a processing system according to one embodiment of the present invention:
  • Figure 4 is a cross-section of one embodiment of an ESFR process chamber of the present invention:
  • Figure 5 is a component-view of one embodiment of a chuck for use in the processing system of Figure 4.
  • Figure 6 is a cross-sectional view of a processing system utilizing exchangeable chucks
  • Figure 7 is a top view of a processing system according to a second embodiment of the present invention utilizing two exchangeable chucks.
  • Figure 8 is a top view of a processing system according to a third embodiment of the present invention utilizing three exchangeable chucks.
  • FIG. 3 is a schematic drawing of one embodiment of a plasma processing system 100.
  • the illustrated system includes a loading cassette 105a. an unloading cassette 105b, a load lock chamber 1 10. at least one processing chamber 120. and a cassette chamber 130.
  • a robotic arm 140 located in the load lock chamber 1 10 transfers the wafer (not shown) to/from the cassettes 105 and chambers ( 1 10. 120 and 130) during the processing cycles.
  • Vacuum pumps (not shown) are installed for each chamber in order to achieve the required vacuum conditions.
  • Nitrogen gas lines (not shown) are connected to the load lock chamber 1 10 and the cooling chamber 130 for purging and venting purposes. Gas lines for delivering processing gases or liquid vapors are connected to the process chamber(s) 120.
  • Heating or cooling mechanisms can also be installed in any of the processing, cooling and load lock chambers.
  • the load lock chamber 110 of the present invention shown in Figure 3.
  • an optional preheating chuck 150 is included.
  • multiple pre-heating chucks are included within the load lock chamber 1 10.
  • Pumping systems are installed for the load lock chamber and each of the processing chambers.
  • the pumping system for the processing chambers is capable of reaching a pumping speed of > 1000 liter/sec.
  • the high pumping speed increases the exchange rate of the reactive species and exhaust of the reaction products, enhancing the ashing process and improving the chamber cleanliness.
  • a silicon wafer with damaged resist (e.g.. resulting from patterning and ion implantation among other semiconductor device fabrication processes) is first transferred into the load-lock chamber 110.
  • the load-lock chamber 1 10 is then pumped down to a base pressure in the range of 0-10 mTorr. followed by purging the chamber 110 with an inert gas (e.g., nitrogen) while pumping to maintain the pressure at 200-500 mTorr.
  • the wafer is then transferred to the ESRF process chamber 120 where the two-step resist stripping will take place.
  • the wafer is pre-heated to a temperature between 100-150°C before being transferred into the ESRF process chamber 120. This further shortens the time necessary for the wafer to reach the first process step temperature, therefore increasing the system throughput.
  • the substrate holder inside the process chamber is normally maintained at an idle temperature of 100-150°C.
  • pre-heat and idle temperatures have been described herein as within the same range, it would be evident to one of ordinary skill in the art that those temperature ranges can be different in an alternate embodiment.
  • inert gases e.g.. nitrogen
  • the chamber is pumped down to base pressure of 0-2 mTorr.
  • Figure 4 is a schematic drawing of one embodiment of an ESRF processing chamber 120 according to the invention. ESRF sources are described in US Patent Nos. 4.938.031 and No.5.234.529.
  • a processing chamber 120 acts as a source plasma generating apparatus and includes a longitudinally slotted .
  • a ceramic, insulating wall 230 separates the plasma in the plasma processing region 220 and the coil 210.
  • the bias shield 202 is disposed between the E-shield 200 and the insulating wall 230. wherein the bias shield slots are aligned with the E-shield slots, however, the bias shield slots are typically wider.
  • the E-shield 200 minimizes the capacitive coupling of the coil 210 to the plasma in region 220 . while coupling the RF power to the plasma inductively (through a match network 262) from an RF power source 260.
  • the vertical slits or slots in the E-shield 200 are designed to optimize the relative percentage of capacitively and inductively coupled RF power.
  • the width, length and relative position of the E-shield and its slits (or slots) to the coil are particularly important as they directly affect the plasma property and process performance. To avoid difficulty in initiating plasma, but at the same time keep the plasma potential low.
  • the total area of the slit should be above 0.1%, but less than 10% or tunable in-situ to minimize ions with excess energy. In the preferred embodiment, the area of the slits is between 0.2% and 5%.
  • the E-shield 200 is electrically grounded.
  • the bias shield 202 is connected to an external biasing circuit 250. comprising an RF generator 252 and match network 254. wherein the electrical biasing of the bias shield 202 is realized. Additional details of utilizing a bias shield 202. can be found in the PCT patent application entitled "All-Surface Biasable and/or Surface Temperature Controlled Electrostatically- Shielded RF Plasma Source.” filed November 13. 1998 (PCT US98/23248).
  • the wafer holder 270. where the wafer is to be placed, is located at a lower portion of the chamber 120 and up to 50 mm below the lower end of the slots in the E-shield 200.
  • Figure 5 illustrates an embodiment of the wafer holder 270. and a detailed description of that design can be found in provisional application 60/156.595. filed September 29. 1999. entitled '"" Multi-Zone Resistance Heater".
  • the wafer holder 270 includes a focus ring 305. an electrostatic clamping section 310. a He gas distribution system 315. a multizone resistance heater section 320. a multizone cooling system 330. and a base 340.
  • the wafer 300 can be electrostatically clamped onto the holder 270 during processing.
  • He gas is supplied in between the wafer 300 and the holder 270 to provide good thermal conduction.
  • the multizone resistance heater section 320 is used for rapidly heating up the wafer 300 to a desired temperature
  • the cooling section 330 is used for rapidly cooling down the wafer to a desired temperature.
  • holder 270 is capable of changing temperatures in a very short time (a few seconds)
  • different temperature settings can be used when stripping ion implanted photoresist within one process.
  • a low temperature setting can be used for stripping the carbonized surface layer to eliminate the resist popping problem
  • a high temperature setting can be used to strip the underlying soft resist to increase the stripping rate and overall throughput.
  • the first process step strips the carbonized skin layer using a process gas or gases (e.g., (1 ) oxygen. (2) hydrogen. (3) water vapor, (4) mixture of oxygen and nitrogen, (5) mixture of hydrogen and nitrogen, (6) mixture of oxygen and water vapor, and (7) mixture of oxygen, water vapor and nitrogen).
  • the processing gas(es) is/ are introduced into the process chamber 120 through the gas delivery system 160 while maintaining the process chamber at between 0.6 -1.2 torr.
  • a RF power level of 1-1.5 W/cc is applied on the inductive coil 210 by the RF source 260 to generate the plasma.
  • the bias shield 202 is biased by the bias shield biasing circuitry 250 to generate a negative DC bias level (e.g..
  • the wafer is processed under this condition for a time period of the first process step (e.g.. seconds to minutes).
  • the wafer is separately negatively biased (due to DC self-bias when biasing with RF) using a biasing voltage source attached to or integrated with the substrate holder 270.
  • the bias shield 202 biases an edge of the wafer (or other substrate), and the biasing voltage source biases a center of the wafer.
  • the wafer temperature is raised to between 200-250°C.
  • the process chamber is pumped down to a low level, and then suitable gases (e.g., ( 1) oxygen. (2) a mixture of oxygen and nitrogen. (3) a mixture of oxygen and water vapor, and (4) a mixture of oxygen, water vapor and nitrogen) are introduced into the process chamber 120 while maintaining a pressure of 0.8-1.2 Torr.
  • suitable gases e.g., ( 1) oxygen. (2) a mixture of oxygen and nitrogen. (3) a mixture of oxygen and water vapor, and (4) a mixture of oxygen, water vapor and nitrogen
  • the RF power applied on the inductive coil 210 is reduced to a level between 0.8-1.2 W/cc to increase the generation of oxygen radicals and reduce the generation of ions.
  • the E-shield 200 is grounded in this step to minimize the plasma potential and number of ions arriving at the surface of the wafer 300.
  • an optional third step is added to strip the carbon residues, if any. on the wafer surface.
  • the conditions for this third step are similar to the first process step except that a higher wafer temperature (e.g.. 200-250°C ) is used.
  • the low energy ion flux and high wafer temperature help in removal of carbon residues from the wafer surface. Since the ion energy flux is low, minimal or no charge damage and contamination drive-in occurs.
  • the wafer 300 is transferred back to the load lock chamber.
  • the wafer 300 may then be moved to another process chamber 120 or through the loading door 185 to the unloading cassette 105b.
  • Cassettes 105 are inserted and removed through the front door 190.
  • high RF power >2 W/cc
  • a dummy wafer may be placed on the wafer holder 270 to protect the surface of the wafer holder 270.
  • Cleaning gases e.g.. (1) oxygen. (2) oxygen and nitrogen, (3) NF 3 , (4) oxygen and NF3, and (5) nitrogen and NF 3
  • the E-shield 200 should be biased to setup a negative bias on the chamber wall (e.g., greater than 100 volts).
  • the high shield bias increases the capacitive coupling of RF power to the plasma, resulting in higher plasma potential.
  • the high plasma potential increases the ion energy flux bombarding the surfaces inside the chamber and enhances the cleaning process.
  • the apparatuses and processes of the present invention are used to strip ion implantation damaged photoresist, wherein a carbonized skin layer is formed due to high dose ion bombardment.
  • the apparatus uses an electrostatically shielded source to generate the low potential source plasma.
  • the chuck design enables fast temperature change, thus multiple temperature settings are used in the same process.
  • a high speed pumping system is used for increasing the efficiency of exhausting the reaction products and exchange of fresh process gases.
  • the apparatuses and the processes have the advantages of stripping high dose implanted photoresist with (1) substantially complete cleanliness. (2) no or minimal charge damage, (3) no or minimal contamination drive in, and (4) high throughput.
  • the process uses multiple steps for stripping damaged resist.
  • oxygen radicals with small amount of ions are introduced to the wafer surface at a low wafer substrate temperature to strip the hardened skin layer using a biased E-shield.
  • oxygen radicals with almost no ions are introduced to the wafer surface at a high substrate temperature to strip the bulk underlying soft resist using a grounded E-shield.
  • conditions similar to the first step but with a high substrate temperature are used to strip the carbon residues, if any. on the wafer surface.
  • an exchangeable chuck arrangement is incorporated in place of the optional pre-heater 150 is incorporated in place of the optional pre-heater 150 as shown in Figure 6. and described in greater detail in attorney docket No. 2312-0836-6YA PROV entitled "Chuck Transport Method and System.” filed herewith.
  • Figure 7 shows a top view of the exchangeable chuck arrangement.
  • Two chucks. 270a and 270b which hold wafers 300a and 300b are situated in chamber 400. and equipped with facilities for both vertical motion 410 and rotary motion 420.
  • the wafer transfer arm 140 initially loads the wafer 300b onto chuck 270b where it is preheated.
  • the chuck assembly 280 lowers, utilizing vertical motion 410. and then rotates, utilizing rotary motion 420. so that chuck 270b together with wafer 300b are interchanged with chuck 270a and wafer 300a.
  • the chuck assembly 280 then raises 410 so that the chuck 270b and wafer 300b are located in ESRF process chamber 120.
  • the stripping of ion-implanted photoresist on wafer 300b then proceeds as described above.
  • the wafer 300b is unloaded by transfer arm 140 and returned to the wafer cassette 105b.
  • a grouping of three chucks 270a 270b and 270c, together with wafers 300a. 300b and 300c. on a triple chuck assembly 580 in chamber 500 is utilized.
  • triple chuck assembly 580 is equipped with vertical motion 410 and rotary motion 420.
  • Two ESRF reaction chambers 120a and 120b are provided. These two ESRF chambers are supplied with different chemistries.
  • ESRF chamber 120a could be supplied with the reducing chemistry for reducing the carbonized ion-implanted skin, and ESRF chamber 120b with the oxidizing chemistry for stripping the photoresist.
  • a wafer 300b would be loaded on chuck 270b by transfer arm 140 and preheated.
  • triple process chuck 580 lowers utilizing vertical motion 410. rotates 120 degree utilizing rotary motion 420. and then raises utilizing vertical motion 410 so that wafer 300b is now located in ESRF process chamber 120a. While in ESRF chamber 120a, the ion-implanted carbonized crust on the photoresist would be reduced.
  • the triple process chuck 580 again lowers, rotates 120 degrees and raises, so that wafer 300b is relocated into ESRF chamber 120b.
  • ESRF chamber 120b may be introduced the oxidizing chemistry for stripping of the photoresist.
  • the triple process chuck 580 again lowers, rotates 120 degrees and raises again. Wafer 300b. now stripped of ion-implanted photoresist, is ready to be returned to the wafer cassette 105b.

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  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

La présente invention concerne un procédé et un système (100) de décapage de couches de résine photosensible par plasma à fréquence radioélectrique et à blindage électrostatique (ESRF), consistant à réduire la croûte et à décaper ensuite la résine photosensible ramollie dans un plasma ESRF. En faisant varier la température au cours de ces deux opérations, ces système et procédé fournissent les paramètres de traitement pour les besoins de la réaction de décapage.
PCT/US2001/005822 1999-09-29 2001-03-20 Decapage ultra-rapide pour resine photosensible endommagee WO2001070517A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2001247226A AU2001247226A1 (en) 2000-03-20 2001-03-20 High speed stripping for damaged photoresist
US10/204,263 US6767698B2 (en) 1999-09-29 2001-03-20 High speed stripping for damaged photoresist

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19009800P 2000-03-20 2000-03-20
US60/190,098 2000-03-20

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WO2001070517A1 true WO2001070517A1 (fr) 2001-09-27

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004084280A3 (fr) * 2003-03-17 2005-03-24 Tokyo Electron Ltd Systeme et procede de traitement d'un substrat
US7605063B2 (en) 2006-05-10 2009-10-20 Lam Research Corporation Photoresist stripping chamber and methods of etching photoresist on substrates
US7718032B2 (en) 2006-06-22 2010-05-18 Tokyo Electron Limited Dry non-plasma treatment system and method of using
CN102522358A (zh) * 2011-12-30 2012-06-27 上海集成电路研发中心有限公司 半导体硅片的去胶工艺腔及去胶方法
US8343280B2 (en) 2006-03-28 2013-01-01 Tokyo Electron Limited Multi-zone substrate temperature control system and method of operating
CN114815532A (zh) * 2022-04-19 2022-07-29 度亘激光技术（苏州）有限公司 光刻胶去除方法及半导体器件制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5795831A (en) * 1996-10-16 1998-08-18 Ulvac Technologies, Inc. Cold processes for cleaning and stripping photoresist from surfaces of semiconductor wafers
US5811358A (en) * 1997-01-03 1998-09-22 Mosel Vitelic Inc. Low temperature dry process for stripping photoresist after high dose ion implantation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5795831A (en) * 1996-10-16 1998-08-18 Ulvac Technologies, Inc. Cold processes for cleaning and stripping photoresist from surfaces of semiconductor wafers
US5811358A (en) * 1997-01-03 1998-09-22 Mosel Vitelic Inc. Low temperature dry process for stripping photoresist after high dose ion implantation

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US7605063B2 (en) 2006-05-10 2009-10-20 Lam Research Corporation Photoresist stripping chamber and methods of etching photoresist on substrates
US7718032B2 (en) 2006-06-22 2010-05-18 Tokyo Electron Limited Dry non-plasma treatment system and method of using
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CN114815532B (zh) * 2022-04-19 2023-11-07 度亘激光技术（苏州）有限公司 光刻胶去除方法及半导体器件制造方法

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