WO2001037099A1 - Memoire destinee a l'unite centrale d'une unite de calcul - Google Patents

Memoire destinee a l'unite centrale d'une unite de calcul Download PDF

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Publication number
WO2001037099A1
WO2001037099A1 PCT/DE2000/004045 DE0004045W WO0137099A1 WO 2001037099 A1 WO2001037099 A1 WO 2001037099A1 DE 0004045 W DE0004045 W DE 0004045W WO 0137099 A1 WO0137099 A1 WO 0137099A1
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WO
WIPO (PCT)
Prior art keywords
memory
processor
main
memory cell
area
Prior art date
Application number
PCT/DE2000/004045
Other languages
German (de)
English (en)
Inventor
Gerd Dirscherl
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2001037099A1 publication Critical patent/WO2001037099A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Definitions

  • the invention relates to a memory for the central unit of a computer system according to the preamble of patent claim 1.
  • CMOS complementary metal-oxide-semiconductor
  • main memory main memory
  • CPU cache memories or often also briefly as CPU caches.
  • a CPU cache is significantly faster, but for reasons of cost it is also significantly smaller than the main memory.
  • execution speed of a central unit with a CPU cache - of course with the same main memories - is significantly higher.
  • level cache memories A distinction is made between level cache memories.
  • the first-level cache memory is located directly in the processor so that it can access it with the processor clock without waiting cycles. Its size is fixed.
  • the second-level cache memory on the other hand, is located on the main board and therefore works in the board clock, which is lower than the processor clock. Since it consists of memory chips, its memory capacity can be increased by adding more memory chips. As a result, the storage capacity of both the first-level cache memory and the second-level cache memory cannot be changed during the operation of the computing system.
  • This task is done by a memory for the
  • Each memory cell of the memory which is also referred to below as configurable memory, accordingly has four memory areas: the data area contains the actual data, that is to say program instructions or data to be processed, which have already been copied from the main memory by the cache logic of the processor or still have to be copied; the address range contains the associated address; the identifier area contains information generated by the cache logic, which is required for managing the reloading of new data from the main memory and the replacement of memory cells to be overwritten when the memory is full, and for example includes information about whether the corresponding memory cell is valid, when it was last and how often it has been used; and the area of use contains information as to whether the corresponding memory cell can be used as a cache memory or as main memory.
  • the area of use is large enough, a distinction can also be made between different memories or peripheral devices for which this memory cell is to serve as a cache memory.
  • the configurable memory is arranged on the processor chip. This has the advantage that the configurable memory can be accessed with the processor clock.
  • the main memory on the main platform can be dispensed with entirely if the configurable memory is large enough or the main memory requirement of the application program currently running in the computing system is low.
  • the configurable memory is therefore also suitable for very small computing systems, such as those provided on chip cards, because additional main memory is particularly expensive there.
  • the configurable memory is also suitable for computer systems with more than one processor. It can then serve as cache memory and / or main memory for each processor.
  • FIG. 1 schematically shows the structure of a central unit in a first embodiment
  • FIG. 2 schematically shows the structure of the configurable memory m of the central unit of FIG. 1;
  • FIG. 3 schematically shows the structure of a central unit in a second embodiment.
  • FIG. 1 schematically shows the structure of a central unit 10 m in a first embodiment.
  • This central unit 10 comprises a processor 12, a main memory 14, an input / output unit 16 and a configurable memory 18, which are arranged together with the bus 20 on a main platform.
  • the input / output unit 16 controls the transfer of data between the central unit 10 and the peripheral devices (not shown), such as, for example, keyboard, monitor, printer, magnetic disk memory, floppy disk drive, CD-ROM drive, modem, etc.
  • the configurable memory 18 is arranged here like the main memory 14 outside of the processor 12 on the main platform.
  • the CPU 10 shown in FIG. 1 has only one processor 12 which accesses the configurable memory 18, at least one further processor (not shown) can also be provided which, like the processor 12 shown, accesses the configurable memory 18.
  • FIG. 2 is a preferred embodiment of the configurable memory 18 for the central processing unit one
  • the configurable memory 18 is here divided into n n memory cells 22.
  • Each memory cell 22 is in turn divided into a data area 24, an address area 26, an identification area 28 and a usage area 30.
  • the data area 24 contains the actual ones
  • the address area 26 contains the memory address of the corresponding memory cell 22.
  • the identification area 28 contains information about the validity, the time of the last use and the frequency of use of the corresponding memory cell 22, which are also used in known CPU cache memories in accordance with the cache logic of the processor 12, so that this applies to them not in more detail must be received.
  • the use area 30 finally contains information about the use or configuration of the corresponding memory cell 22 as a cache memory or else as main memory.
  • the usage area 30 has a size of 2 bits, so that information about a total of four different uses or configurations of each memory cell 22 can be stored therein.
  • the value 00 of the area of use 30 of a specific memory cell 22 can indicate that this memory cell 22 as main memory, which is used in the central unit 10 of FIG. 1 is therefore available in addition to the main memory 14 on the main board, while the other values 01, 10 and 11 each use this memory cell 22 as a cache memory for various other memories or peripheral devices, such as a floppy disk drive CD-ROM drive and the main memory 14 on the motherboard, can specify.
  • the usage area 30 indicates the use of a memory cell 22 as a cache memory, access by the cache logic to this memory cell 22 is enabled, so that it can be deleted, for example, and overwritten by new data from the main memory 14. If, on the other hand, the usage information indicates the use as main memory, access by the cache logic to this memory cell 22 is blocked, so that processor 12 can use this memory cell 22 as main memory.
  • the usage information can be influenced, for example, by the application program that is currently running in the computer system according to its needs.
  • FIG. 3 shows a central unit 10 of a second embodiment.
  • the configurable memory 18 is different from the first embodiment of FIG. 1 already arranged directly on the processor chip 32 in the manner of a first-level cache memory.
  • the main memory 14 arranged on the main platform in the first embodiment is completely absent here, since the configurable memory 18 serves wholly or partly as the main memory.
  • the main plate of this central unit 10 is thus smaller and simpler than that of FIG. 1.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L'invention concerne une mémoire destinée à l'unité centrale d'une unité de calcul, cette unité centrale (10) présentant au moins un processeur comportant au moins une cellule de mémoire composée d'une zone de données, d'une zone d'adresse, et d'une zone d'identification, chaque cellule de mémoire présentant une zone d'utilisation servant à indiquer à chaque processeur de l'unité centrale si la cellule de mémoire peut être utilisée en tant que mémoire cache et/ou mémoire principale.
PCT/DE2000/004045 1999-11-16 2000-11-16 Memoire destinee a l'unite centrale d'une unite de calcul WO2001037099A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP99122771.1 1999-11-16
EP99122771 1999-11-16

Publications (1)

Publication Number Publication Date
WO2001037099A1 true WO2001037099A1 (fr) 2001-05-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/004045 WO2001037099A1 (fr) 1999-11-16 2000-11-16 Memoire destinee a l'unite centrale d'une unite de calcul

Country Status (1)

Country Link
WO (1) WO2001037099A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4580240A (en) * 1981-12-15 1986-04-01 Nippon Electric Co., Ltd. Memory arrangement operable as a cache and a local memory
EP0708404A2 (fr) * 1994-10-05 1996-04-24 International Business Machines Corporation Matrice entrelacée d'antémémoires de données ayant par ligne d'antémémoire plusieurs champs adressables par contenu

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4580240A (en) * 1981-12-15 1986-04-01 Nippon Electric Co., Ltd. Memory arrangement operable as a cache and a local memory
EP0708404A2 (fr) * 1994-10-05 1996-04-24 International Business Machines Corporation Matrice entrelacée d'antémémoires de données ayant par ligne d'antémémoire plusieurs champs adressables par contenu

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WILLE T: "RECHENGENIE IN DER PLASTIKKARTE. ÖCHIPKARTEN-CONTROLLER", FUNKSCHAU,DE,FRANZIS-VERLAG K.G. MUNCHEN, vol. 65, no. 7, 19 March 1993 (1993-03-19), pages 132 - 135, XP000349698, ISSN: 0016-2841 *

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