WO2001029970A2

WO2001029970A2 - Test circuit for integrated analog-to-digital converters

Info

Publication number: WO2001029970A2
Application number: PCT/US2000/023543
Authority: WO
Inventors: Jean-Yves Michel
Original assignee: Koninklijke Philips Electronics Nv; Philips Semiconductors, Inc.
Priority date: 1999-10-15
Filing date: 2000-08-28
Publication date: 2001-04-26
Also published as: WO2001029970A3; EP1145442A3; EP1145442A2; JP2003512754A

Abstract

A test circuit arrangement (10, 110) and method for functionally testing an analog-to-digital converter (ADC) (12, 112), such as an N-bit ADC, by testing for a missing digital output code. A digital code generator (19, 119), such as including an N-bit word generator or an N-bit counter reset by an M-bit timer, generates a digital output code that is compared with the digital output of the N-bit ADC. The comparison is performed by a missing code detection circuit (20, 120). In response to the comparison, the missing code detection circuit operatively drives, such as by controlling an integrator (24, 124), an analog input of the N-bit ADC toward the desired digital output code. The missing code detection circuit includes an output circuit (23), such as including a flip-flop, wherein a code detected output is set when each desired digital output code is detected in the digital output of the N-bit ADC. Implementation of a test circuit arrangement may include fabrication as a built-in test circuit in an integrated device, such as a semiconductor integrated circuit including the N-bit ADC to be tested.

Description

TEST CIRCUIT FOR INTEGRATED ANALOG-TO-DIGITAL

CONVERTERS

Field of the Invention

The invention is generally related to integrated circuit device design and architecture, and in particular, to functionally testing an analog-to-digital converter (ADC).

Background of the Invention

Analog-to-digital converters (ADC) are used to translate analog information, such as audio signals or measurements of physical variables (for example, temperature, force, or shaft rotation), into a form suitable for digital handling, which might involve any of these operations: (1) processing by a computer or by logic circuits, including arithmetical operations, comparison, sorting, ordering, and code conversion; (2) storing until ready for further handling; (3) displaying in numerical or graphical form; and (4) transmitting.

Commonly-used ADC conversion techniques include simple voltage-level comparators, direct or flash conversion, integrating conversion such as dual-slope conversion, and feedback conversion such as successive-approximations conversion, among other techniques known to those skilled in the art.

Just as a large number of techniques for conversion exist, analog-to-digital converters are fabricated in a number of ways, with the trend being for smaller and cheaper devices. The earliest analog-to-digital converters were large rack-panel chassis-type modules using vacuum tubes and requiring several watts of power. Since then, ADC's have evolved through circuit board, encapsulated-module, and hybrid constructions that require comparatively less space and power. The performance requirements for analog-to-digital converters also vary widely. For example, a laboratory oscilloscope may require a highly accurate measurement of a voltage at a tip probe. A relatively large analog-to-digital converter may thus require a number of discrete components having compensating circuitry and calibration capabilities in order to insure accuracy. During manufacture, performance testing may thus be required of such highly accurate and large analog-to-digital converters, rather than merely a brief test of functionality. Examples of performance testing would include providing a calibrated analog input signal to the analog-to- digital converter and verifying that the corresponding digital output code is produced. Another example would be testing for indecision zones, wherein the range of analog input signals is determined for which there exists an equal probability that one of two digital output codes will be produced. Another performance test would be for integral non-linearity. Performance testing may further include varying the operating conditions (e.g., temperature, pressure, power supply voltage) to assess the effect on performance. Requirements for highly accurate and large analog-to-digital converters often warrant the additional time required to test and the external test equipment for performing the test. In order to have confidence in a fielded device containing an analog-to-digital converter, often external testing devices must be incorporated or the device must be returned for periodic calibration testing. However, many applications use small, low-cost analog-to-digital converters that are to be used in applications requiring lower accuracy and/or less demanding operating environments. Functionality testing is often sufficient to have confidence in the manufacture and operation of such analog-to-digital converters, especially if the converter design is well centered and has sufficient margin to accommodate expected variations in manufacturing process. Integrated circuit fabrication techniques may provide repeatability in performance such that defects typically preclude functionality. For example, a flaw in the silicon wafer or in producing semiconductor circuits on the silicon wafer would result in open or closed electrical pathways that prevent operation altogether, rather than merely degradation of accuracy. Similar failures may occur during operation due to physical damage to the device or due to thermal cycles on conduction pathways that result in loss of function. Examples of small, low cost analog-to-digital converters include single-chip 12-bit analog-to-digital converters with the ability to interface with microprocessors in small integrated-circuit packages.

Also, integrated-circuit analog-to-digital converters, with 8-bit and better resolution and conversion rates of hundreds of megahertz, are commercially available. An example of applications for such analog-to-digital converters include a personal computer interface for a microphone or a joystick.

For an analog-to-digital converter, functionality testing means that for an analog input signal, a digital output code is produced. More specifically, for an operable range of analog input signals, the corresponding digital output code set is produced. A digital output code is missing if the analog-to-digital converter does not generate the digital output code in response to the corresponding analog input signal.

Thus, an analog-to-digital converter that has a missing digital output code would be deemed to have failed functionality testing.

Another consideration, especially for semiconductor integrated circuits, is the size of testing devices. Complex testing devices generally require more space, such as increased number of gates on a semiconductor device. Keeping the cost of manufacture low requires that higher numbers of semiconductor integrated circuits occupy the same wafer.

Economical production also dictates that functionality testing not unduly slow the production line. Thus, preferably each analog-to-digital converter would have a built-in test circuit arrangement so that each would not require testing by an external testing device. In addition, a simplified approach to testing the analog-to-digital converter would similarly improve production throughput by shortening the length of time required to test. Economical production would be further realized by eliminating the need for mixed signal external test equipment, which is generally more expensive than purely digital test equipment.

Therefore, a significant need exists in the art for a simplified approach to functionality testing of analog-to-digital converters is necessary, and in particular, an approach that may be built into a semiconductor integrated circuit containing the analog-to-digital converter. Summary of the Invention

The invention addresses these and other problems associated with the prior art by providing a test circuit arrangement and method for functionally testing an analog- to-digital converter (ADC). Consistent with one aspect of the invention, a circuit arrangement for testing an analog-to-digital converter includes a digital word generator configured to generate a plurality of digital output codes and a missing code detection circuit. The missing code detection circuit is coupled to receive and compare the digital output code generated by the digital word generator and the digital output generated by the analog- to-digital converter. Based on the comparison, the missing code detection circuit drives the analog-to-digital converter to generate the digital output code and indicates an inability to drive the analog-to-digital converter to one of the digital output codes.

Consistent with another aspect of the invention, an integrated circuit device includes an analog-to digital converter and a built-in self-test circuit arrangement. The analog-to-digital converter receives an analog input within an analog input range and generates in response thereto a corresponding digital output from a digital output code set. The built-in self-test circuit arrangement is configured to detect a missing digital output code of the analog-to-digital converter. The built-in self-test circuit includes a digital word generator configured to sequentially generate at an output, digital values from the digital output code set; a digital comparator configured to determine a difference between the digital output of the analog-to-digital converter and the digital value (or digital output code) from the digital word generator; an integrator, coupled to the digital comparator and configured to drive the analog input of the analog-to-digital converter in response to the difference between the digital output code and the digital value; and an output circuit operatively coupled to the digital comparator and configured to indicate when the digital output from the analog- to-digital converter matches the digital value output from the digital word generator.

Consistent with yet another aspect of the invention, a method for testing an analog-to-digital converter includes generating a digital output code; digitally comparing the digital output code with a digital output of the analog-to-digital converter; driving an analog input to the analog-to-digital converter in response to a difference between the digital output code and the digital output of the ADC; and indicating the presence of a missing digital output code in response to an inability to drive the analog-to-digital converter to output the digital output code.

These and other advantages and features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention.

Brief Description of the Drawings

FIGURE 1 is a block diagram of a first test circuit arrangement for functionally testing an N-bit analog-to-digital converter (ADC) consistent with the invention. FIGURE 2 is a diagrammatic view of an analog integrator referenced in Fig. 1.

FIGURE 3 is a block diagram of a second test circuit arrangement for functionally testing an N-bit analog-to-digital converter (ADC) consistent with the invention.

FIGURE 4 is an illustrative timing diagram for the second test circuit arrangement of Fig. 3.

Detailed Description

In the discussion below, indicating the presence of a missing code is illustrated by generating an output in response to the inability to drive an analog-to-digital converter to a certain digital output. However, it will be appreciated that indicating the presence of a missing code may alternatively or more specifically include affirmative or negative indications of whether a missing code has been detected (e.g., the absence of a signal indicating that a particular code has been detected), all digital codes were verified by testing, and/or testing is incomplete because of the presence of a missing code. Turning to the Drawings, wherein like numbers denote like parts throughout the several views, Fig. 1 illustrates a test circuit arrangement 10 for functionally testing an N-bit analog-to-digital converter ("N-bit ADC") 12 having an analog input 14 and a digital output 16. The analog input 14 may be characterized as having an analog input range, either a performance range for which the N-bit ADC 12 is designed or an operational range to which the N-bit ADC 12 is expected to be employed. An example of the latter is a 12-bit ADC design wherein only the 10 most-significant bits (MSB) are used or relied upon for accuracy, and thus the test circuit arrangement uses N as 10-bits and disregards the two least significant bits (LSB). Thus, "N-bit" denotes the number of serial or parallel output bits comprising a digital output code from the digital output 16. The various combinations of bits possible or expected to be employed in the output code may be all possible combination of bits or a range subset thereof.

The N-bit ADC 12 is functionally tested for a missing digital output code in the digital output 16 with a digital code generator 19 and a missing code detection circuit 20. The digital code generator 19 is illustrated as including an N-bit word generator 21 that generates a digital output 18. The missing code detection circuit 20 is shown as including comparison logic 22 that digitally compares the digital output (A) 16 of the N-bit ADC 12 with the digital output (B) 18 of generator 21 to operatively drive the analog input 14. The comparison logic 22 also includes an output circuit 23 to indicate the presence of the desired digital output 18 in the actual digital output 16. The comparison of the digital output (A) 16 and digital output (B) 18 may be accomplished by comparison logic 22, comprised of lumped component or integrated circuit logic. The comparison logic may drive the analog input 14 directly, or indirectly such as by driving an integrator 24 by generating an increase signal 25 when the digital output (A) 16 is less than the digital output (B) 18, and a decrease signal 26 when the digital output (A) 16 is greater than the digital output (B) 18. The increase and decrease signals 25, 26 may share a single communication path or be discretely provided as shown in Fig. 1. In addition, the increase and decrease signals 25, 26 may be of various formats. The increase and decrease signals 25, 26 are shown controlling an analog integrator 24 including an up input 32 receiving the increase signal 25 and a down input 34 receiving the decrease signal 26. The analog integrator 24 may provide a single output 36 to the analog input 14 of the N-bit ADC 12, as shown. Alternatively, if the N-bit ADC 12 has a differential analog input 14, the analog integrator 24 would be differential as well. Various implementations of an analog integrator 24 would be apparent to those skilled in the art, including a passive R-C (resistor-capacitor) circuit, a charge pump, and an operational amplifier with capacitively coupled feedback, among others.

An exemplary integrator 24 utilizing an operational amplifier 38 having a negative input 39 and a positive input 40 is illustrated in Fig. 2. Integrator 24 utilizes capacitively coupled feedback C, electrically coupled between the output and the negative input 39 of the operational amplifier 38. The positive input 40 of the operational amplifier 38 is electrically grounded. The up input 32 and a negative supply 42 are input to a multiplier 44. The down input 34 and a positive supply 46 are input to a multiplier 48. An example of multipliers 44, 48 would be a semiconductor integrated-circuit transistor controlled as switches, respectively, by the up and down inputs 32, 34. The outputs of multiplier 44 and multiplier 48 are electrically coupled to a first end of resistor R. The second end of resistor R is electrically coupled to the negative input 39. Appropriate values of R and C would be apparent for achieving an integrator with appropriate electrical characteristics for the analog input 14 of the N-bit ADC 12 and the clock rate of the test circuit arrangement 10.

Returning to Fig. 1 , detection of a missing digital output code may be performed by the comparison logic 22 as shown in Fig. 1 wherein the output circuit 23 provides a code detected output 50 when the actual digital output code (A) 16 equals the desired digital output code (B) 18. Various implementations of monitoring and reporting the code detected output 50 would be apparent, including an internal or external state machine (not shown) which verifies that the code detected output 50 is true at least momentarily for each desired digital output code (B) 18. Advantageously, a fault detected flag (not shown) may be provided in machine or human readable format when the test circuit arrangement 10 is unable to drive the N- bit ADC 12 to at least one desired digital output code 18.

Synchronization of the test circuit arrangement 10 may be provided by a clock signal 52 electrically coupled to the N-bit ADC 12 and N-bit word generator 21. In addition, some implementations of the analog integrator 24 and comparison logic 22 may also require synchronization by the clock signal 52. For example, the clock signal may reset the analog integrator 24 to either the lowest or highest value of the analog input 14 for the N-bit ADC 12. Also, the comparison logic 22 may utilize a clock signal for functions such as resetting the code detected output 50. The clock rate of the clock signal 52 would typically be the same for testing the N-bit ADC 12 as used for normal operation. Alternatively, higher clock rates for testing may be advantageously used to gain a higher confidence level in the functionality of the N-bit ADC 12 or to reduce the testing period. In addition, a plurality of clock rates may be used for various components of the test circuit arrangement 10, as will be discussed below with regard to Fig. 3. Referring to Fig. 3, a second test circuit arrangement 110 is shown with a digital code generator 119 including an M-bit timer 160 having a timer interval of M clock cycles and an N-bit counter 162. The M-bit timer 160 receives and counts a clock signal 152, changing state each M-cycles. The M-bit timer 160 is operably coupled to the N-bit counter 162 to periodically trigger with a timer signal 161 the N- bit counter 162 to the next digital output code in the sequence of digital output codes 116, typically the next higher or lower value possible with the illustrative example being the next higher binary code combination of N-bits.

A missing code detection circuit 120 is shown in Fig. 3 as including an analog integrator 124, a digital comparator 166 and a flip-flop 168. The digital comparator 166 compares the actual digital output code 116 from the N-bit ADC 112 and the desired digital output code 118. The digital comparator 166 provides, as an output to the integrator 124, a single integrator driving signal 170, which would have a value such as "1" if the digital output code 116 is smaller than the digital output 118 and "- 1" for the converse. When the actual digital output code 116 is equal to the digital output 118, the single integrator driving signal 170 may be "0". It would be apparent to those skilled in the art to implement an integrator 124 response to other formats of integrator driving signal, such as "1" or "0".

The digital comparator 166 also provides an output circuit cconfigured to output a set flag signal 172, to a set input 168a of the flip-flop 168 to set a flag output 168c of the flip-flop 168 to a code detected state such as "1". A reset input 168b of the flip-flop 168 is electrically coupled to the timer signal 161 to reset the flag output.

Driving the N-bit ADC 112 in a sequence of digital output codes 116 is advantageous in that a relatively short number of clock cycles of the clock signal 152 may comprise the interval M since the integrator 124 would be driving the analog input 114 to an adjacent value, either higher or lower, as illustrated in Fig. 4. The value of M may be also relatively short in order to assure that the N-bit ADC 112 responds within predetermined time constraints.

Referring to Fig. 4, an illustrative timing diagram is shown for the circuit arrangement 110 of Fig. 3. A relatively short period clock signal ("clock") is shown, generated by clock signal 152 and comprised of an approximately 50% duty cycle pulse train. From this clock signal 152, a timer signal ("timer") is generated by the M-bit timer 160, with a timer pulse provided each M pulses of the clock signal. A digital output code ("desired code") is generated by the N-bit counter 162, changing to the next digital code when the timer signal changes. In the illustrative example, the lower code "N-l" (i.e., one least significant bit lower) is output before the first illustrated timer pulse and "N" is output after the first illustrated timer pulse. After a second timer pulse, "N+l" (i.e., one least significant bit higher) is output.

An integrator output signal ("integrator") is shown as an analog plot with a generally increasing trend. Specifically, the integrator output signal increases when the digital output code 116 ("ADC output") is shown outputting a code lower (e.g., "N-3") than the digital output 118 and decreasing when the digital output code 116 is shown outputting a code higher (e.g., "N+l").

At the point where the ADC output is "N", meaning that the desired digital output code 118 is being generated by the N-bit ADC 112, then the flag signal changes state, such as illustrated by a "0" value going to a "1" that is held until after the next timer pulse is generated by the M-bit timer 160 to reset the flip flop 168. Alternatively, the flag signal may provide a pulse for only a portion of the remaining timer period. As a further alternative, the flag signal may be set only when a missing digital output code is detected rather than when each possible digital output code 116 is detected.

It will be apparent to those skilled in the art that test circuit arrangements 10, 110 may be fabricated in a number of ways including lumped value components or integrated circuit components incorporated into the design of integrated devices, such as including a semiconductor integrated circuit, having needs for analog-to-digital conversion.

Portions of test circuit arrangements 10, 110 may include, or be augmented by, a state machine (not shown) to initiate testing by starting necessary timing (e.g., start M-bit timer 160) and resetting components (e.g., reset N-bit counter 162) as required. A state machine would be i plementable by those of ordinary skill in the art having a benefit of this disclosure. For example, for analog-to-digital converters 12, 112 adapted to interface with a microprocessor, a state machine may be code executed by the microprocessor with operable connections to the circuit arrangements 10, 110. As another example, a small gate count integrated circuit may comprise the state machine allowing the test circuit arrangements 10, 1 10 to be economically fabricated in a semiconductor integrated circuit device. For example, built-in self-test may be automatically performed at the direction of the state machine upon initial application of power, or upon other initiating events (e.g., warm start reset signal). In addition, the state machine may perform a periodic built-in test functional test by testing a portion of the possible digital output code range 116 interspersed between normal operation of the N-bit ADC 112. Such use may be appropriate when the sample rate required of the N-bit ADC 112 for normal operation is far below its capability, and thus the normal output of the N-bit ADC 112 may be held for a test interval while functional testing is performed. Alternatively, the state machine may perform dedicated functional testing.

Also, the state machine may reduce the time required for functional testing by detecting when each desired digital output code is generated by the N-bit ADC 112 and immediately resetting the digital code generator 119, such as by resetting the M- bit timer 161, rather than waiting for the full M-bit timer period to expire.

In addition, the state machine may operably couple the test circuit arrangements 10, 110 to the analog-to-digital converters 12, 1 12, respectively, and operably uncouple the test circuit arrangements 10, 110 for normal usage, although other methods would be apparent to those skilled in the art such as a physical switch (not shown).

Detection of a missing digital output code with the output circuit may include use of a monitoring device (not shown), such as a logic tester to monitor the output of the digital comparators 22, 122.

Various additional modifications may be made to the illustrated embodiments without departing from the spirit and scope of the invention.

Claims

What is claimed is: 1. A circuit arrangement comprising: a digital word generator configured to generate a plurality of digital output codes; and a missing code detection circuit coupled to receive the digital output codes generated by the digital code generator, the missing code detection circuit configured to drive an analog-to-digital converter to output each of the plurality of digital output codes, and to indicate the presence of a missing code in response to an inability to drive the analog-to-digital converter to one of the plurality of digital output codes.

2. An integrated circuit device including the circuit arrangement of claim 1 and the analog-to-digital converter.

3. The integrated circuit device of claim 2, further comprising a semiconductor integrated circuit arrangement.

4. The circuit arrangement of claim 1, wherein the missing code detection circuit includes an integrator electrically coupled to drive the analog-to-digital converter.

5. The test circuit arrangement of claim 4, wherein the integrator comprises an operational amplifier including capacitively coupled feedback.

6. The test circuit arrangement of claim 4, wherein the integrator comprises a passive resistor-capacitor circuit arrangement.

7. The test circuit arrangement of claim 4, wherein the integrator comprises a charge pump.

8. The test circuit arrangement of claim 4, wherein the analog input of the analog-to-digital converter comprises a differential analog input, and wherein the integrator includes a differential output coupled to the differential analog input of the analog-to-digital converter.

9. The test circuit arrangement of claim 4, wherein the digital word generator further comprises a timer operably coupled to a counter, the counter responsive to the timer to sequentially generate the plurality of digital output codes.

10. An integrated circuit device including an analog-to-digital converter and a built-in self-test circuit arrangement, the built-in self-test circuit arrangement configured to detect missing digital output codes of an analog-to-digital converter adapted to receive an analog input within an analog input range and to generate in response thereto a digital output from a digital output code set, the built-in self-test circuit arrangement comprising: a digital word generator configured to sequentially generate at an output, digital values from the digital output code set; a digital comparator configured to determine a difference between the digital output from the analog-to-digital converter and the digital value output from the digital word generator; an integrator operably coupled to the digital comparator and configured to drive the analog input of the analog-to-digital converter in response to the difference between the digital output from the analog-to-digital converter and the digital value output from the digital word generator; and an output circuit operably coupled to the digital comparator and configured to indicate when the digital output from the analog-to-digital converter matches the digital value output from the digital word generator.

11. The integrated circuit device of claim 10, wherein the digital word generator comprises a counter and a timer, the timer configured to output a timing signal and the counter responsive to the timing signal to sequentially output digital values.

12. The integrated circuit device of claim 10, wherein the integrator comprises an operational amplifier including capacitively coupled feedback.

13. The integrated circuit device of claim 10, wherein the integrator comprises a passive resistor-capacitor circuit.

14. The integrated circuit device of claim 10, wherein the integrator comprises a charge pump.

15. The integrated circuit device of claim 10, wherein the analog input of the analog-to-digital converter comprises a differential analog input, and wherein the integrator includes a differential output coupled to the differential analog input of the analog-to-digital converter.

16. The integrated circuit device of claim 10, wherein the output circuit includes a flip-flop.

17. The integrated circuit device of claim 10, further comprising a state machine operatively coupled to the built-in self-test circuit, the state machine configured to initiate testing of the analog-to-digital converter.

18. A method of testing an analog-to-digital converter, the method comprising: generating a digital output code; digitally comparing the digital output code with a digital output of the analog-to-digital converter; driving an analog input to the analog-to-digital converter in response to a difference between the digital output code and the digital output of the analog-to-digital converter; and indicating the presence of a missing digital output code in response to an inability to drive the analog-to-digital converter to output the digital output code.

19 The method of claim 18, wherein driving the analog input to the analog-to-digital converter further comprises generating an integrator driving signal to an integrator electrically coupled to the analog input of the analog-to-digital converter.

20 The method of claim 18, wherein generating the digital output code further comprises: generating a timing signal; and sequentially generating a plurality of the digital output codes in response to the timing signal, wherein indicating the presence of the missing code includes indicating whether any of the plurality of digital output codes is missing.

21. The method of claim 20, wherein indicating the presence of a missing digital output code is performed in response to an inability to drive the analog-to- digital converter to output the digital output code within an interval of the timing signal.