JP2003512754A - Test circuit for integrated analog-to-digital converter - Google Patents

Abstract

The present invention solves the problems associated with the prior art by providing a test circuit arrangement and method for functionally testing an analog-to-digital converter (ADC). A test circuit arrangement (10, 110) and method for functionally testing an analog-to-digital converter (ADC), such as an N-bit ADC, by testing for a missing digital output code. The digital code generator (19, 119) generates a digital output code that is compared to the digital output of the N-bit ADC, such as including an N-bit word generator or an N-bit counter reset by an M-bit timer. The comparison is performed by the missing sign detection circuit (20, 120). In response to the comparison, the missing sign detection circuit drives the analog input of the N-bit ADC to operate to the desired digital output sign, such as by controlling an integrator (24, 124). The missing code detection circuit includes an output circuit (23) that, when each desired digital output code is detected in the digital output of the N-bit ADC, includes a flip-flop, the code whose output is detected is set. Including. Implementation of a test circuit arrangement includes fabrication as an embedded test circuit in an integrated device, such as a semiconductor integrated circuit including an N-bit ADC to be tested.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to integrated circuit device design and architecture, and more particularly to functionally testing analog-to-digital converters (ADCs).

[0002]

[Prior art]

An analog-to-digital converter (ADC) is an audio signal or a physical variable (for example,
Processing analog information such as temperature, force, or axis rotation) measurements by a computer or logic circuit that includes (1) arithmetic operations, comparisons, classifications, ordering, and sign conversions; ) Converting to a form suitable for digital processing, including storing until further processing, (3) displaying numerically or graphically, and (4) transmitting.

Commonly used ADC conversion techniques are known to those skilled in the art, including simple voltage level comparators, direct or flash conversions, integral conversions such as dual slope conversions, and feedback conversions such as successive approximation conversions. Included among other technologies.

Due to the large number of conversion technologies, analog-to-digital converters are manufactured in many ways, which tend to be smaller and cheaper. The earliest analog-to-digital converters were large rack-panel chassis-type modules that used vacuum tubes and required a few watts of power.
Since then, ADCs have evolved with circuit boards, encapsulation modules and hybrid structures that require relatively little space and power.

The performance requirements for analog-to-digital converters also differ significantly. For example, an oscilloscope for experiments needs to measure the voltage of a tip probe with high accuracy. As a result, relatively large analog-to-digital converters may require a large number of discrete components with compensation circuitry and calibration capability to ensure accuracy.
For this reason, such a high-precision and large analog-digital converter
Performance tests may be needed rather than just simple functional tests. Specific examples of performance tests would include providing a calibrated analog input signal to an analog-to-digital converter and verifying that a corresponding digital output code is produced. Another example would be a test for an indecision zone where the range of the analog input signal is determined so that one of the two digital output codes is produced with equal probability. Another performance test would be for integral nonlinearity. Performance testing will also include changing operating conditions (eg, temperature, pressure, supply voltage) to evaluate the impact on performance. The requirements for high accuracy and large analog-to-digital converters often require the additional time required to perform the test and external test equipment to perform the test. To make fielded devices, including analog-to-digital converters, reliable, it is often necessary to incorporate an external test device, or to return the device to a regular calibration test.

However, many applications use small, low cost analog-to-digital converters that are used in low precision and / or low operating environment applications. Functional testing is especially relevant to the manufacture of such analog-to-digital converters, especially if the converter is properly centered and designed with sufficient margin to accommodate expected changes in the manufacturing process. And is often sufficient to make the operation reliable. Integrated circuit manufacturing techniques produce repeatability in performance as defects typically interfere with functionality. For example, a defect in a silicon wafer or a defect in producing a semiconductor circuit on a silicon wafer not only deteriorates accuracy, but also causes an open or closed electrical path (
open or closed electrical pathway). Similar impairments can occur during operation due to physical damage to the device or due to thermal cycling on the conduction path leading to loss of functionality. Examples of small, low cost analog-to-digital converters include single-chip 12-bit analog-to-digital converters that can interface with microprocessors in small integrated circuit packages. Integrated circuit analog-to-digital converters with 8-bit, better resolution, and conversion rates of hundreds of megahertz are also commercially available. Specific examples of applications for such analog-to-digital converters include personal computer interfaces for microphones or joysticks.

In the case of an analog-digital converter, the functional test is for an analog input signal
Means that a digital output code is generated. More specifically, for the operational range of the analog input signal, a corresponding digital output code set is generated. If the analog-to-digital converter does not generate the digital output code in response to the corresponding analog input signal, then the digital output code is lost. Therefore, an analog-to-digital converter with a missing digital output code would be considered to have failed the functional test.

Another consideration is the size of the test device, especially for semiconductor integrated circuits. Generally, a complicated test device requires a larger space because the number of gates of a semiconductor device is increasing. In order to keep the manufacturing cost low, it is necessary to occupy more semiconductor integrated circuits on the same wafer.

To obtain an economical production, it is also necessary that the functional test does not overly slow the production line. For this reason, it would be preferable for each analog-to-digital converter to incorporate a test circuit arrangement therein so that testing by an external test device is unnecessary. In addition, the simplified approach to testing analog-to-digital converters would likewise reduce the time required for testing and consequently improve production throughput.

Furthermore, economical production may also be achieved by eliminating the need for mixed signal external test equipment, which is generally more expensive than pure digital test equipment.

Therefore, there is a need in the art for a simplified approach to functional testing of analog-to-digital converters, particularly one that can be incorporated into a semiconductor integrated circuit containing the analog-to-digital converter.

[0012]

[Means for Solving the Problems]

The present invention addresses the above and other problems associated with the prior art by providing a test circuit arrangement and method for functionally testing an analog-to-digital converter (ADC).

According to one aspect of the invention, a circuit arrangement for testing an analog-to-digital converter includes a digital word generator and a missing code detection circuit configured to generate a plurality of digital output codes. The missing code detection circuit is coupled to receive and compare the digital output code generated by the digital word generator and the digital output generated by the analog-to-digital converter. Based on this comparison, the missing code detection circuit indicates that the analog-to-digital converter cannot be driven to generate the digital output code and the analog-to-digital converter cannot be driven to one of the digital output codes.

According to another aspect of the invention, an integrated circuit device includes an analog-to-digital converter and a built-in self-test circuitry. The analog-to-digital converter receives the analog input within the analog input range and, in response, produces a corresponding digital output from the digital output code set. The built-in self-test circuit layout is
Lack of analog-to-digital converter configured to detect digital output code. The built-in self-test circuitry includes a digital word generator configured to sequentially generate a digital value from the digital output code set at the output, and a digital output of the analog-to-digital converter and a digital value from the digital word generator ( Or a digital comparator configured to determine the difference between the digital output code) and
An integrator coupled to the digital comparator and configured to drive the analog input of the analog-to-digital converter in response to the difference between the digital output sign and the digital value, and operatively coupled to the digital comparator. And configured to indicate when the digital output from the analog-to-digital converter matches the digital value output from the digital word generator.

According to yet another aspect of the present invention, a method of testing an analog-to-digital converter comprises generating a digital output code and digitally comparing the digital output code and the digital output of the analog-to-digital converter. And the digital output code
Missing due to driving the analog input to the analog-to-digital converter depending on the difference between the digital output of the ADC and the inability to drive the analog-to-digital converter to output the digital output code. Indicating the presence of a digital output code.

The above as well as additional advantages and features which characterize the present invention are pointed out with particularity in the claims annexed to and forming a part hereof. However,
For a better understanding of the invention and the advantages and objectives achieved by its use, reference should be made to the figures and the accompanying description which describes exemplary embodiments of the invention.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, an indication that a missing sign is present is indicated by producing an output in response to being unable to drive the analog-to-digital converter to a certain digital output. Alternatively, or more specifically, however,
Indicating the presence of a missing code indicates whether a missing code (eg, the absence of a signal indicating that a particular code has been detected) has been detected, whether all digital codes have been verified by testing, and / or It will also be appreciated that it includes a positive or negative indication as to whether the test is incomplete due to the presence of the missing sign.

Referring to the drawings where the same parts in each figure are labeled the same, FIG. 1 illustrates an N-bit analog converter (“N-bi”) having an analog input 14 and a digital output 16.
t ADC ”) 12 shows a test circuit arrangement 10 for functionally testing 12. The analog input 14 can be characterized as having an analog input range in the performance range designed for the N-bit ADC 12 or in the operating range in which the N-bit ADC 12 is expected to be used. In the latter implementation, only the 10 most significant bits are used or depend on the precision, so the test circuit arrangement uses N as 10 bits and the 2 least significant bits (LSBs). This is a 12-bit ADC design to ignore. Thus, “N bits” refers to the number of serial or parallel output bits with digital output code from digital output 16. The various combinations of possible or expected bits to be used in the output code can be all possible bit combinations or a range subset thereof.

The 12-bit ADC is functionally tested for the missing digital output code in the digital output 16 by the digital code generator 19 and the missing code detection circuit 20. Digital code generator 19 is shown to include an N-bit word generator 21 that produces a digital output 18. The missing sign detection circuit 20 drives the digital output (A) 16 of the N-bit ADC 12 to drive the analog input 14 to operate, and the digital output (B) of the generator 21 (B).
) 18 is shown to include comparison logic 22 that compares digitally with 18. The comparison logic 22 also includes an output circuit 23 to indicate the presence of the desired digital output 18 within the actual digital output 16.

A comparison between the digital output (A) 16 and the digital output (B) 18 is based on lumped c
omponent) or a comparison logic 22 comprising integrated circuit logic. The comparison logic is configured to generate an increment signal 25 when the digital output (A) 16 is less than the digital output (B) 18 and to
Is greater than the digital output (B) 18, the analog input 14 can be driven directly or indirectly by driving the integrator 24 by generating a decrease signal 26. The increase and decrease signals 25, 26 can share a single channel or can be provided separately as shown in FIG. Further, the increase and decrease signals 25, 26 can be in various formats.

Shown are the increasing and decreasing signals 25, 26 controlling the analog integrator 24, which includes an up input 32 receiving the increasing signal 25 and a down input 34 receiving the decreasing signal 26. The analog integrator 24 can provide a single output 36 to the analog input 14 of the N-bit ADC 12 as shown. Alternatively, if the N-bit ADC 12 has a differential analog input 14, then the analog integrator 24 will also be differential. Especially passive
Various implementations of the analog integrator 24, including an RC (resistor-capacitor) circuit, a charge pump, and an operational amplifier with capacitively coupled feedback, will be apparent to those skilled in the art.

A typical integrator 24 utilizing an operational amplifier circuit 38 having a negative input 39 and a positive input 40 is
It is shown in FIG. The integrator 24 uses a capacitively coupled feedback C that is electrically coupled between the output of the operational amplifier 38 and the negative input 39. Operational amplifier 3
The positive input 40 of 8 is electrically grounded. Up input 32 and negative power supply 42 are multiplier 4
Entered in 4. Down input 34 and positive power supply 46 are input to multiplier 48. Multiplier 4
An example of 4, 48 would be a semiconductor integrated circuit transistor controlled as a switch by up and down inputs 32, 34, respectively. The outputs of multiplier 44 and multiplier 48 are electrically coupled to the first end of resistor R. The second end of resistor R is electrically coupled to negative input 39. Appropriate electrical characteristics for the analog input 14 of the N-bit ADC 12 and suitable values for R and C to achieve an integrator with the clock speed of the test circuit arrangement 10 will be apparent.

Returning to FIG. 1, the detection of the missing digital output code is performed by the output circuit when the actual digital output code (A) 16 is equal to the desired digital output code (B) 18 as shown in FIG.
23 can be performed by the comparison logic 22 which provides the detected sign output 50. The code detected output 50 includes an internal or external state machine (not shown) that verifies that the output 50 is at least instantaneously true for each desired digital output code (B) 18. Various implementations of monitoring and reporting output 50 will be apparent. Test circuit arrangement 10 has at least one desired digital output code
If it is not possible to drive the N-bit ADC 12 to 18, a fault detected flag (not shown) can be advantageously provided in machine or human readable format.

The synchronization of the test circuit arrangement 10 can be provided by the clock signal 52 electrically coupled to the N-bit ADC 12 and the N-bit word generator. Moreover, some implementations of analog integrator 24 and comparison logic 22 also require synchronization by clock signal 52. For example, the clock signal can reset the analog integrator 24 to the minimum or maximum value of the analog input 14 for the N-bit ADC 12. Also, the comparison logic 22 can utilize the clock signal for functions such as resetting the output 50 for which the sign was detected. Typically, the clock speed of the clock signal 52 will be the same as used for normal operation and testing the N-bit ADC 12. Alternatively, a faster clock rate can be used for the test to obtain a higher confidence level in the functionality of the N-bit ADC 12 or to reduce the test period. In addition, multiple clock speeds may be used for various components of test circuit arrangement 10, as described below with respect to FIG.

FIG. 3 shows a second test circuit arrangement 11 having a digital code generator 119 including an M-bit timer 160 having an M clock cycle timer interval and an N-bit counter 162.
0 is shown. M-bit timer 160 receives and counts clock signal 152 and changes state every M cycles. The M-bit timer 160 is typically
The N-bit counter 162 is timerd to the next digital output code in the series of digital output codes 116, where the next larger or smaller value possible in the illustrated embodiment is a combination of the N-bit next larger binary codes. An N-bit counter 162 is operatively coupled for periodic triggering by signal 161.

As shown in FIG. 3, the missing code detection circuit 120 includes an analog integrator 124, a digital comparator 166, and a flip-flop 168. Digital comparator 166 is Nb
Compare the actual digital output code 116 from the it ADC 112 with the desired digital output code 118. The digital comparator 166 outputs a digital output code as an output to the integrator 124.
It provides a single integrator drive signal 170, which will have a value of "1" if 116 is less than the digital output 118, and "-1" for the opposite. Actual digital output code 1
If 16 equals the digital output 118, then the single integrator drive signal 170 can be a "0". It will be apparent to those skilled in the art to implement integrator 124 depending on other formats of the integrator drive signal, such as "1" or "0".

The digital comparator 166 also sets the flag output 168c of the flip-flop 168 to “1”.
Also provided is an output circuit configured to output a set of flag signals 172 to a set of inputs 168a of a flip-flop 168 for setting a sign such as The reset input 168b of flip-flop 168 is electrically coupled to timer signal 161 to reset the flag output.

Driving the N-bit ADC 112 into a series of digital output codes 116 includes an integrator 124
Is driving the analog input 114 to a larger or smaller adjacent value as illustrated in FIG. 4, so that a relatively short number of clock cycles of the clock signal 152 can have an interval M. The value of M can also be relatively short to ensure that the N-bit ADC 112 responds within predefined time constraints.

In FIG. 4, a timing diagram for the circuit arrangement 110 of FIG. 3 is shown. A relatively short period clock signal ("clock") generated by the clock signal 152 and consisting of about 50% duty cycle pulse train is shown. From this clock signal 152, a timer signal (“timer”) is generated by the M-bit timer 160, with each timer pulse providing M pulses of the clock signal. When the timer signal changes, the N-bit counter 162 changes to the next digital code and generates a digital output code (“desired code”). In the illustrated embodiment, a smaller code "N-1" (ie, one least significant bit lower) is output before the first illustrated timer pulse, where "N" is the first illustrated. Output after the timer pulse. After the second timer pulse, "N + 1" (ie one least significant bit higher)
Is output.

The integrator output signal (“integrator”) is shown as an analog plot, generally with an increasing trend. In particular, when the digital output code 116 (“ADC output”) indicates an output that is one code smaller (eg, “N-3”) than the digital output 118, the integrator output signal increases and is one code larger (eg, “N-3”). When the "N + 1") output is shown at digital output code 116, it is decreased.

At a position where the ADC output is “N”, which means that the desired digital output code 118 is being generated by the N-bit ADC 112, a “0” value indicates that the M-bit timer 160 is The flag signal changes state, as indicated by the generation of a time pulse and a change to "1" which is held until the flip-flop 168 is reset. Alternatively, the flag signal can provide pulses for only the portion of the remaining timer period. As another alternative, the flag signal may be set only when a missing digital output code is detected, rather than when each possible digital output code 116 is detected.

Test circuit arrangements 10, 110 often include lumped value components or integrated circuit components incorporated into the design of integrated devices, such as semiconductor integrated circuits that require analog-to-digital converters. It will be apparent to those skilled in the art that it can be manufactured by the method of.

The portion of the test circuit arrangement 10, 110 starts the required timing (eg, starts the M-bit timer 160) and resets the components as required (eg, resets the N-bit counter 162). A state machine (not shown) may be included in, or augmented by, a test to initiate the test. State machines could be implemented by those of ordinary skill in the art having the benefit of this disclosure. For example, an analog-to-digital converter 12 adapted to interface with a microprocessor 12
, 112, the state machine can be code executed by a microprocessor operably connected to the test circuit arrangement 10, 110. As another example, a small gate count integrated circuit can have a state machine that allows the test circuit arrangement 10, 110 to be economically manufactured in a semiconductor integrated circuit device.
For example, a built-in self-test is a state machine instruction in response to an initial power up,
Alternatively, it can be automatically executed in response to another start event (for example, a warm start reset signal). In addition, the state machine can perform periodic built-in test functional tests by testing a portion of the possible digital output code range 116 plugged during normal operation of N-bit ADC 112. If the sample rate required for the N-bit ADC 112 for normal operation is well below its capability, such use is appropriate and the normal output of the N-bit ADC 112 is It can be held for test intervals during the execution of functional tests. Alternatively, the state machine can perform specialized functional tests.

In addition, instead of waiting for the end of the entire M-bit timer period, the M-bit timer 161
By detecting when the N-bit ADC 112 produces each desired digital output code, such as by resetting, and instantly resetting the digital code generator 119, the state machine is required for functional testing. Time can be reduced.

In addition, the state machine provides a test circuit arrangement 10, 110 to the analog-to-digital converter 12.
, 112 respectively operatively coupled and tested for normal use with a circuit arrangement 10
, 110 can be operably removed. However, other methods such as physical switches (not shown) will be apparent to those skilled in the art.

In order to detect the missing digital output code by the output circuit, a digital comparator 22,
A monitoring device (not shown) may also be used, such as a logic tester that monitors the output of 122.

Various additional modifications can be made to the embodiments shown herein without departing from the spirit and scope of the invention.

[Brief description of drawings]

FIG. 1 shows a block diagram of a first test circuit arrangement for functionally testing an N-bit analog-to-digital converter (ADC) according to the present invention.

FIG. 2 shows a diagram of the analog integrator shown in FIG.

FIG. 3 shows a block diagram of a second test circuit arrangement for functionally testing an N-bit analog-to-digital converter (ADC) according to the present invention.

FIG. 4 shows a timing diagram illustrating the second test circuit arrangement of FIG.

[Explanation of symbols]

10 Test circuit layout 12 Digital-to-analog converter 20 Missing code detection circuit 21 word generator 24 integrator 38 Operational amplifier 110 Second test circuit layout 112 Digital-to-analog converter 119 Digital Code Generator 166 Philip Flop 120 Missing code detection circuit DESIRED digital output code

─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2G132 AA00 AA11 AB01 AC03 AD06                       AE14 AG01 AG08 AK07 AK29                       AL09                 5J022 AA01 AC04 BA06 CC03 CF01 [Continued summary] Embedded within integrated devices, such as semiconductor integrated circuits, including Manufacturing as a test circuit only is included.

Claims (21)

[Claims] 1. A digital word generator configured to generate a plurality of digital output codes,
And a missing code detection circuit coupled to receive the digital output code generated by the digital code generator, the missing code detection circuit driving an analog-to-digital converter to provide the plurality of digital signals. A circuit configured to output each of the output codes and to indicate the presence of a missing code in response to the inability to drive the analog-to-digital converter to one of the plurality of digital output codes. Placement. 2. An integrated circuit device comprising the circuit arrangement according to claim 1 and the analog-digital converter. 3.   The integrated circuit device of claim 2, further comprising a semiconductor integrated circuit arrangement. 4. The circuit arrangement according to claim 1, wherein the missing sign detection circuit includes an integrator electrically coupled to drive the analog-to-digital converter. 5. The test circuit arrangement according to claim 4, wherein the integrator comprises an operational amplifier including capacitively coupled feedback. 6. The test circuit arrangement according to claim 4, wherein the integrator comprises a passive resistance-capacitor circuit arrangement. 7.   The test circuit arrangement according to claim 4, wherein the integrator comprises a charge pump. 8. The analog input of the analog-to-digital converter has a differential analog input,
The test circuit arrangement of claim 4, wherein the integrator includes a differential output coupled to the differential analog input of the analog to digital converter. 9. The digital word generator includes a timer operably coupled to a counter, the counter responsive to the timer to sequentially generate the plurality of digital output codes. Test circuit layout described in. 10. An integrated circuit device including an analog-to-digital converter and a built-in self-test circuitry, wherein the built-in self-test circuitry is adapted to receive analog inputs within an analog input range. A converter is configured to detect a digital output code and to generate a digital output from the digital output code set accordingly, wherein the built-in self-test circuitry produces a digital value from the digital output code set. A digital word generator configured to sequentially generate at an output and configured to determine a difference between the digital output from the analog-to-digital converter and the digital value from the digital word generator. And a digital comparator that is operably coupled to the digital comparator. And configured to drive the analog input of the analog-to-digital converter in response to a difference between the digital output from the analog-to-digital converter and the digital value from the digital word generator. An integrator, operably coupled to the digital comparator, and configured to indicate when the digital output from the analog-to-digital converter matches the digital value from the digital word generator. And an integrated circuit device having an output circuit. 11. The digital word generator has a counter and a timer, the timer is configured to output a timing signal, and the counter sequentially generates digital values in response to the timing signal. Item 11. The integrated circuit device according to item 10. 12. The integrated circuit device of claim 10, wherein the integrator comprises an operational amplifier circuit that includes capacitively coupled feedback. 13. The integrated circuit device of claim 10, wherein the integrator has a passive resistance-capacitor circuit arrangement. 14.   11. The integrated circuit device of claim 10, wherein the integrator comprises a charge pump. 15. The analog output of the analog-to-digital converter has a differential analog input, and the integrator provides a differential output coupled to the differential analog input of the analog-to-digital converter. The integrated circuit device of claim 10 including. 16. The integrated circuit device of claim 10, wherein the output circuit comprises a flip-flop. 17. The method of claim 10, further comprising a state machine operably coupled to the built-in self-test circuit, the state machine configured to initiate testing of the analog-to-digital converter. Integrated circuit device. 18. A method of testing an analog-to-digital converter, the method generating a digital output code and digitally comparing the digital output code and a digital output of the analog-to-digital converter. Driving an analog input to the analog-to-digital converter according to a difference between the digital output code and the digital output of the analog-to-digital converter, and outputting the digital-output code to the analog-to-digital converter. Indicating the presence of a missing digital output code in response to being unable to drive as. 19. Driving the analog input to the analog to digital converter further comprises generating an integrator drive signal to an integrator electrically coupled to the analog input of the analog to digital converter. 19. The method of claim 18 having. 20. Generating the digital output code further comprises: generating a timing signal; and sequentially generating a plurality of the digital output codes in response to the timing signal; 19. The method of claim 18, wherein indicating presence includes indicating whether any of the plurality of digital codes are missing. 21. Representing the presence of a missing digital output code is responsive to the inability to drive the analog-to-digital converter to output the digital output code within an interval of the timing signal. 21. The method of claim 20, which is performed.