JP2735076B2 - Test method for analog / digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding the A / D converter test method, with a relatively simple configuration, it is possible to detect the presence / absence of an A / D converter abnormality in a short time, and to improve the test efficiency. It is possible to output an analog signal corresponding to the entire conversion range of the A / D converter, and gradually increase or decrease the analog signal in accordance with the logic level of the control signal.
A smoothing circuit for supplying to the D converter, and responding to the digital signal output from the A / D converter, determining whether or not the code of the digital signal is gradually increasing or decreasing by one, and based on the determination result. A control circuit for controlling the control signal to a predetermined logic level, wherein the code of the digital signal output from the A / D converter finally reaches the maximum value or the minimum value of the conversion range of the A / D converter. It is configured to determine whether there is an abnormality in the A / D converter based on whether the A / D converter is abnormal.

[Industrial applications]

The present invention relates to an analog / digital converter (hereinafter referred to as A / D converter).
In particular, the present invention relates to a technique for detecting the presence or absence of an abnormality in an A / D converter and evaluating the accuracy of the converter based on the detection.

In recent years, digitization has been progressing in various fields such as the video and audio fields, and accordingly, the demand for A / D converters for converting analog signals into digital signals has been increasing. The resolution and speed of such A / D converters have been increasing due to technological advances and market demands. As a result, the time required for testing and evaluation, gain errors, linearity errors, and missing codes ( The quantity of measurement items such as so-called bit omissions) is also increasing and becoming more complicated.

For this reason, there are demands for various methods, test devices, and the like that enable efficient testing and accuracy evaluation of the A / D converter.

[Conventional technology and problems to be solved by the invention]

As a method of testing and evaluating a conventional A / D converter, for example, a reference digital / analog (D / A) method for obtaining a non-linear error and a differential non-linear error (hereinafter referred to as LE and DLE, respectively) by an AC servo method is used. / A) Perform DC linearity test using a converter to find LE, detect missing codes by histogram method, or use LE, DL
There are known methods for obtaining E, performing a fast Fourier transform (FFT) test, and obtaining overall accuracy, that is, the number of effective bits.

For example, missing codes, monotonic abnormalities (see FIGS. 5 (a) and 5 (b); as shown by the dashed line, the state where the code 13 ₍₁₀₎ of the digital output signal D _OUT is missing, or the monotonicity of the output form In the case of detecting a local abnormality such as an abnormal state), the analog input signal is first sent to the A / D converter in a width sufficiently smaller than the voltage width of 1 LSB over the entire conversion range of the A / D converter. And then subjecting the digital output signal output from the A / D converter to data processing corresponding to each analog input signal, and detecting the presence or absence of the local abnormality based on the result of the data processing. I was

In other words, despite the fact that the A / D converter abnormality is local, it is necessary to perform an overall test over the entire conversion area of the converter and analyze the results, and then check for any abnormality or failure of the converter. Cannot be determined. Therefore, there is a problem that the time required for the test and the evaluation becomes longer with the increase in the resolution and the speed, and further, the configuration of the device for the test becomes complicated and the cost becomes high.

From the viewpoint of improving accuracy, it is preferable to increase the number of steps of the analog input signal.However, on the other hand, the time required for testing the A / D converter becomes longer by that amount, so from the viewpoint of improving test efficiency. It is disadvantageous.

Furthermore, the high-speed A / D converter used in the video bandwidth, often employing the full parallel or serial-parallel type as a method, in which in the method the resolution of a number of comparators (e.g. n bits, 2 ⁿ -1 Comparators) are used in parallel. Therefore, even when detecting a local abnormality such as a missing code caused by an abnormality in the comparator, it is disadvantageous in terms of time because the presence or absence of the abnormality can only be determined after confirming the operation of all the comparators. It is not preferable from the viewpoint of efficiently testing the converter.

SUMMARY OF THE INVENTION In view of the above-described problems in the related art, a main object of the present invention is to detect the presence / absence of an abnormality in an A / D converter in a relatively simple configuration in a short time, and thereby to improve the efficiency of a test. To provide a test method that can be used.

Another object of the present invention is to make it possible to efficiently evaluate the accuracy of the A / D converter based on the detection of the presence or absence of the abnormality.

[Means for solving the problem]

According to the present invention, in order to solve the above-described problems in the related art, it is possible to output an analog signal corresponding to the entire conversion range of an A / D converter, and to convert the analog signal to a logic level of a control signal. A smoothing circuit for gradually increasing or decreasing the digital signal in accordance with the digital signal output from the A / D converter, and determining whether the code of the digital signal is gradually increasing or decreasing by one in response to the digital signal output from the A / D converter. And a control circuit for controlling the control signal to a predetermined logic level based on the result of the determination.
It is possible to determine whether there is an abnormality in the A / D converter based on whether the code of the digital signal output from the D converter finally reaches the maximum value or the minimum value of the conversion range of the A / D converter. A method for testing an A / D converter is provided.

(Operation)

If the A / D converter is normal, the code of the digital signal is gradually increased (or decreased) by one from the A / D converter and output. Therefore, the control circuit outputs a control signal of a fixed logic level (either "H" level or "L" level). Thereby, the smoothing circuit gradually increases (or decreases) the analog signal in response to the "H" level (or "L" level) control signal, and the A / D
Supply to converter. Therefore, the A / D converter finally outputs an output code corresponding to the maximum value (or the minimum value) of the conversion range of the A / D converter.

On the other hand, if the A / D converter is abnormal, the code of the digital signal output from the A / D converter is output while increasing or decreasing without monotonically changing. In other words, the output is performed while generating a code jump without changing every time. Therefore, the logic level of the control signal output from the control circuit is not constant. Therefore, the smoothing circuit supplies the analog signal to the A / D converter while gradually increasing or decreasing the analog signal. That is, the output code of the A / D converter does not change in one direction in the direction of gradually increasing (or decreasing), but changes while increasing or decreasing. Therefore, the output code of the A / D converter cannot reach its maximum value even after a considerable time has elapsed.

As described above, by detecting whether the output code of the A / D converter finally reaches the maximum value (or the minimum value), it is possible to easily determine whether the A / D converter is abnormal. . Since this can be performed without using special data processing or the like, it is extremely preferable from the viewpoint of time reduction and efficient testing.

The details of other structural features and operations of the present invention will be described with reference to the accompanying drawings and embodiments described below.

〔Example〕

FIG. 1 shows the configuration of an apparatus to which the A / D converter test method of the present invention is applied. The device of the present embodiment has an A / D
It is applied to detect the presence / absence of a local abnormality such as missing converter code or monotonicity abnormality.

In the figure, reference numeral 1 denotes an A / D converter under test, which is an output signal (analog input signal) D _{IN of} a smoothing circuit 2 (described later) in response to a clock φ supplied from a control circuit 3 (described later). _Is converted into a digital output signal _DOUT . As an example, consider an 8-bit A / D converter, and the output signal D _OIT is 256 (= 2 ⁸ )
Output the exact code. Therefore, A / D converter 1
Is a digital output signal at the falling edge every time a predetermined number of clocks φ are input if the function is normal.
The code of D _OUT is gradually increased by +1. Setting the conversion range of the analog input D _IN to the _{VR L ~VR H (VR L <} VR H),
Correspondence between the input and output, when D _IN = VR _L is _{D OUT = 0 (10),} D IN
= When VR _H becomes D _OUT = 255 _(10). The subscript ₍₁₀₎ is
Represents decimal notation.

Smoothing circuit 2, the entire VR conversion region of the A / D converter 1 _L ~
An analog signal D _IN corresponding to VR _H can be output,
A function of smoothing the analog signal in accordance with the logical level of a control signal (determination result instruction signal) _CO supplied from the control circuit 3 and supplying the smoothed signal to the A / D converter 1 I have. Specifically, the smoothing circuit 2 gradually increases the analog signal D _IN when the control signal C _O is at “H” level, and gradually decreases the analog signal D _IN when the control signal C _O is at “L” level.

For example, as shown in FIG. 2 (a), the smoothing circuit 2 includes a resistor 21 connected between the input and output terminals, and a capacitor 22 connected between the output terminal and the ground. ing. Also, the speed of voltage change of the smoothing circuit dV / dt
The following _{conditions, dV / dt <(VR H} -VR L) / (2 n · φ T) ... [1] and _{dV / dt> (VR L -VR} H) / (2 n · φ T) ... [2] is selected. Here, n A / D converter resolution (bit), φ _T is the A / D converter conversion time (s / cycle), VR _H upper limit of the conversion range of the A / D converter (V), VR _L Represents the lower limit (V) of the conversion range of the A / D converter.

The above equation [1] is a condition for detecting the presence / absence of a local abnormality such as a missing code, a monotonic abnormality or the like in the A / D converter, and the equation [2] is an A / D converter as described later. Is a condition for causing the code before and after the abnormal point to be output. If the condition of equation [2] is not satisfied,
A / D converter will continue to output the output code of code-D _X and code D _Y of the anomaly. However, the code D _Y is, D _X - is defined by ^{(dV / dt) · 2 n} · φ T / (VR H -VR L).

The control circuit 3 includes a digital (D) outputs code memory 31 for temporarily storing the code of the digital output signal D _OUT output from the A / D converter 1, the comparator circuit
32, a memory control circuit 33, and a timing adjustment circuit 34 for generating an A / D converter operation clock φ. The comparison circuit 32 compares (subtracts) the code read from the memory 31 with the code output from the A / D converter 1, and sets the control signal _CO to the “H” level or the “L” based on the comparison result. "Has a level control function.

The memory control circuit 33 controls data holding and data reading for the D output code memory 31 and controls operations for the comparison circuit 32 in accordance with the logical level of the output C _O of the comparison circuit. Have. In particular,
When the output C _{O of the} comparison circuit is at “H” level, the code output from the A / D converter 1 is temporarily latched in the memory 31 and then sequentially taken into the comparison circuit 32. On the other hand, when the output C _O is "L" level of the comparison circuit, until the change in the output C _O is "H" level, the output card from the A / D converter 1 is held in the memory 31, the The held code is taken into the comparison circuit 32.

Now suppose that the current output code of A / D converter 1 is D _n ,
Assuming that the previous output code is D _n−1 , the control circuit 3 performs an operation as shown in Table 1 below with respect to the input signal D _OUT and the control signal C _O to the smoothing circuit 2. Here, the output code D _n of the current corresponds to the code output from the A / D converter 1, the front output code D _n-1 corresponding to the code read from the memory 31.

Next, the operation of the FIG. 1 apparatus will be described with reference to the signal waveform diagram of FIG. 3 and Table 1. Incidentally, the code D _n of the A / D converter digital output D _OUT is set in the initial state, that is at the beginning of the test such that 0 _(10).

(1) When the A / D converter 1 is normal (see FIG. 3 (a)) First, since the code D _n is 0 _(10), the control circuit 3 outputs a control signal C _O of "H" level And supplies it to the smoothing circuit 2. Thereby, the output of the smoothing circuit, that is,
The analog signal D _IN of the A / D converter 1 gradually increases. When the voltage of the analog signal D _IN rises to an extent that the A / D converter 1 can output the code of 1 ₍₁₀₎ , the A / D converter
1 ₍₁₀₎ is output as a new output code D _n from the converter 1.

At this time, the previous output code D _n-1 is stored in the D output code memory 31.
0 ₍₁₀₎ are held, after all, the comparison circuit 32 the previous output code D _n-1 (0 ₍₁₀₎₎ and the new output code is just output D _n-1 (1 ₍₁₀₎₎ Is subtracted. That is, D
_{Since n−1−} D _n = −1, the control circuit 3 outputs the control signal _Co at the “H” level. Therefore, the output of the smoothing circuit, that is, the analog signal D _IN of the A / D converter 1 gradually increases,
When A / D converter 1 is the voltage of the analog signal D _IN to the extent that code can output 2 ₍₁₀₎ rises, 2 ₍₁₀₎ is output as a new output code D _n from the A / D converter 1 .

At this time, the previous output code D _n-1 is stored in the D output code memory 31.
1 ₍₁₀₎ is held as a result. In the comparison circuit 32, the comparison between the previous output code D _n-1 (1 ₍₁₀₎ ) and the new output code D _n (2 ₍₁₀₎ ) just output is finally made. Subtraction processing is performed. Thereafter, similar steps are repeated.

In this case, since the A / D converter 1 is normal, the output code of the A / D converter 1 gradually increases by one. As a result, the control circuit 3 also continues to output the control signal _Co at the “H” level, so that the analog signal D _IN of the A / D converter 1 gradually increases. Therefore, as shown in FIG. 3 (a), and finally at the time of t _o, A / D converter 1 outputs an output code maximum value 255 _(10).

(2) When the A / D converter 1 is abnormal (see FIG. 3 (b)) For example, as shown in FIG.
₍₁₀₎ is not output and the output code is …… 11 ₍₁₀₎ → 12 ₍₁₀₎ →
14 ₍₁₀₎ A case where the code changes (a code is missing) will be described.

Initially, code D _n is 0 _(10), the control circuit 3 outputs a control signal C _o of "H" level, whereby, A / D
The analog signal D _{IN of the} converter gradually increases, and its output code gradually increases by one.

D output code memory 31 stores the previous output code D _n-1 as 12
₍₁₀₎ is held, and, when the 14 from the A / D converter 1 as an output code D _{n (10)} is outputted, the comparator circuit 32 is D
Subtract _n-1 -D _n = -2. Thereby, the control circuit 3
Outputs an “L” level control signal _Co and
The code D _n-1 (12 ₍₁₀₎ ) in 31 is retained. When the control signal _Co becomes “L” level, the output of the smoothing circuit, that is, the analog signal D _IN of the A / D converter 1 gradually decreases until the A / D converter 1 outputs a code of 12 _(10). When the voltage of the analog signal D _iN is lowered, the a / D converter 1 as a new output code D _n is 12 ₍₁₀₎ is output.

At this time, the previous output code D _n-1 is stored in the D output code memory 31.
Since 12 ₍₁₀₎ is held as
Performs subtraction processing between the previous output code D _n-1 (12 ₍₁₀₎ ) and the new output code D _n (12 ₍₁₀₎ ) just output. Since this result is 0, the control circuit 3 outputs the control signal _Co at the “H” level. Thereby, A / D converter analog signals D _IN of gradually increased, eventually, A / D converter outputs again 14 ₍₁₀₎ as the output code D _n. Thereafter, the above operation is repeated in a similar manner.

Accordingly, when there is an abnormality in the code missing, as shown in FIG. 3 (b), the A / D converter 1 converts the part with the code missing and the preceding and following codes (12 ₍₁₀₎ or 14 ₍₁₀₎ ). Output repeatedly. That is, the time t _o that would normally reach the maximum value 255 ₍₁₀₎ of the output code
In this case, the output code still shows 12 ₍₁₀₎ or 14 ₍₁₀₎ even after elapse.

Next, as another form of abnormality, as shown in FIG. 5 (b), the output code is: 11 ₍₁₀₎ → 12 ₍₁₀₎ → 11 ₍₁₀₎ → 12
₍₁₀₎ → 13 ₍₁₀₎ …… (in case of monotonic abnormality)
Will be described.

As with the code chipping, output code D _n is up to 12 ₍₁₀₎ increases normally by progressively 1.

D output code memory 31 stores the previous output code D _n-1 as 12
₍₁₀₎ is held, and, when the 11 from the A / D converter 1 as an output code D _{n (10)} is outputted, the comparator circuit 32 is D
_n-1 −D _n = −1 is subtracted. Thereby, the control circuit 3
Outputs an “L” level control signal C ₀ and
The code D _n-1 (12 ₍₁₀₎ ) in 31 is retained. When the control signal _Co becomes “L” level, the output of the smoothing circuit, that is, the analog signal D _IN of the A / D converter 1 gradually decreases. 12 ₍₁₀₎ is outputted as the output code D _n soon.

At this time, the previous output code D _n-1 is stored in the D output code memory 31.
Since 12 ₍₁₀₎ is held as
Performs subtraction processing between the previous output code D _n-1 (12 ₍₁₀₎ ) and the new output code D _n (12 ₍₁₀₎ ) just output. Since this result is 0, the control circuit 3 outputs the control signal _Co at the “H” level. Thereafter, the above operation is repeated in a similar manner.

Therefore, the A / D converter 1 repeatedly outputs codes between codes having abnormal monotonicity even in the case of monotonic abnormality as in the case of missing codes. Therefore, the maximum value 255 ₍₁₀₎ of the output code of the A / D converter 1 cannot be output.

As described above, a local abnormality such as a missing code or a monotonic abnormality in the A / D converter 1 causes the digital output signal D _OUT output from the A / D converter to finally _reach the maximum value of the output code. By detecting whether to reach,
It can be easily determined. Since this can be performed without using any special data processing or the like, it contributes to shortening of time and is very suitable from the viewpoint of efficient testing.

In the above-described embodiment, the case of detecting the presence / absence of code missing and monotonic abnormality of the A / D converter has been described. However, the configuration of FIG. 1 is slightly modified to perform the test and evaluation of the A / D converter. Differential nonlinearity error (DLE) useful for

The feature of this modification is that the circuit configuration shown in FIG. 2B or FIG. 2C is used as the smoothing circuit 2 with respect to the configuration of FIG. A triangular wave signal having good linearity over the entirety is generated, and the control circuit 3 detects a change point of the digital output signal D _OUT of the A / D converter to detect the control signal C _L.
(Indicated by a broken line in FIG. 1).

2 (b), the smoothing circuit 2 includes an inverter 23 and a CMOS transistor in addition to the configuration shown in FIG. 2 (a).
24 and 25, and a buffer 26. Further, in the form of (c), the smoothing circuit 2 includes an inverter
41, a resistor 42, 44 and an inverter 43, which constitute an integrating circuit, and a buffer 45.

In this case, similarly to the above-described embodiment, the control circuit 3 operates as shown in Table 2 below.

FIG. 4 shows the signal waveform of each part of this modified example.
As shown in the figure, the above-mentioned DLE can be measured by determining the relationship between the operation control clock φ of the A / D converter and the timing at which the control signal _CL is generated. This makes it possible to evaluate the accuracy of the A / D converter.

〔The invention's effect〕

As described above, according to the present invention, the presence / absence of an abnormality in the A / D converter can be detected in a short time with a relatively simple configuration, and the abnormality can be detected without using special data processing or the like. Determination can greatly contribute to the efficiency of testing and inspection. Further, since the DLE can be obtained by a simple modification, the accuracy of the A / D converter can be efficiently evaluated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an apparatus to which the A / D converter test method of the present invention is applied, and FIGS. 2 (a) to 2 (c) are circuits showing a configuration example of a smoothing circuit in FIG. FIGS. 3 (a) and 3 (b) are signal waveform diagrams for explaining the operation of the FIG. 1 apparatus, FIG. 4 is a signal waveform diagram for explaining the operation of a modification of the FIG. 1 apparatus, FIGS. 5A and 5B are diagrams for explaining an abnormal operation of the A / D converter. (Explanation of reference numerals) 1 ... A / D converter, 2 ... Smoothing circuit, 3 ... Control circuit, 21-26, 41-45 ... Triangular wave generation circuit, 31 ... D output code memory, 32 ... Comparison circuit, 33 ...... memory control circuit, 34 ...... timing adjustment circuit, D _IN ...... analog input signal, D _OUT ...... digital output signal, C _o, C _L ...... control signal, phi ...... clock.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sanroku Tsukamoto 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd. Hei 1-120125 (JP, A) JP-A-56-79965 (JP, A) JP-A-62-253226 (JP, A)

Claims (2)

(57) [Claims] An analog signal (D _IN ) corresponding to the entire conversion range of an analog / digital converter (1) can be output, and the analog signal is converted to a logic level of a control signal (C _O ). Gradually increase or decrease the analog /
In response to a smoothing circuit (2) supplied to the digital converter and a digital signal (D _OUT ) output from the analog / digital converter, the code of the digital signal gradually becomes 1
And a control circuit (3) for controlling whether the control signal is at a predetermined logic level based on the result of the determination, the digital signal output from the analog / digital converter. Is determined based on whether the code finally reaches the maximum value or the minimum value of the conversion range of the analog / digital converter. Test method for analog / digital converter. 2. The smoothing circuit (2) includes circuits (21 to 26, 41 to 45) for generating triangular wave signals having good linearity over the entire conversion range of the analog / digital converter. The control circuit (3) generates a clock (φ) for operating the analog / digital converter and detects a change point of the digital output signal of the analog / digital converter to instruct the detection. And outputting the control signal (C _L ) to determine the relationship between the clock and the timing at which the second control signal is generated, thereby evaluating the accuracy of the analog / digital converter. Item 2. The test method according to Item 1.