WO2001026306A1 - Moteur de service abr utilise dans un systeme de commutation par paquets - Google Patents

Moteur de service abr utilise dans un systeme de commutation par paquets Download PDF

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Publication number
WO2001026306A1
WO2001026306A1 PCT/KR2000/001099 KR0001099W WO0126306A1 WO 2001026306 A1 WO2001026306 A1 WO 2001026306A1 KR 0001099 W KR0001099 W KR 0001099W WO 0126306 A1 WO0126306 A1 WO 0126306A1
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WO
WIPO (PCT)
Prior art keywords
cell
selector
backward
queue length
engine
Prior art date
Application number
PCT/KR2000/001099
Other languages
English (en)
Inventor
Song Chong
Sung-Ho Kang
Young-In Choi
Original Assignee
Samsung Electronics Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co., Ltd. filed Critical Samsung Electronics Co., Ltd.
Priority to JP2001529148A priority Critical patent/JP2003511907A/ja
Priority to EP00966568A priority patent/EP1135895A1/fr
Priority to CA002351352A priority patent/CA2351352A1/fr
Publication of WO2001026306A1 publication Critical patent/WO2001026306A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H04L2012/5632—Bandwidth allocation
    • H04L2012/5635—Backpressure, e.g. for ABR

Definitions

  • the present invention relates generally to a packet switching system. More particularly, the present invention relates to an Available Bit Rate (ABR) service engine in a packet switching system.
  • ABR Available Bit Rate
  • Packet switching technology is utilized in the Asynchronous Transfer Mode (ATM) networks and the Internet networks.
  • ATM Asynchronous Transfer Mode
  • One of the general traffic management problems lies in the congestion flow control of the packet switching networks such as the ATM.
  • the ATM layer provides the following four services: Constant Bit Rate (CBR), Variable Bit Rate (VBR), Unspecified Bit Rate (UBR), and Available Bit Rate (ABR).
  • CBR Constant Bit Rate
  • VBR Variable Bit Rate
  • URR Unspecified Bit Rate
  • ABR Available Bit Rate
  • VBR Variable Bit Rate
  • a representative example of the elastic traffic services is the ABR service provided in the ATM networks.
  • the ATM forum has selected a closed-loop rate-based scheme as the flow control scheme for the ABR service due to its simplicity.
  • the closed-loop rate-based flow control scheme uses the feed back information from the network to control the rate at which each source can transmit the cells into the network.
  • the feed back information is conveyed to the source through specific control cells called resource management (RM) cells.
  • RM resource management
  • For the rate-based flow control information about the network congestion is written in the RM cell using mechanisms, such as explicit forward congestion indication
  • the ABR service does not require a complex traffic characterization and a call admission control at the source and at the switches, respectively. Due to this simplicity, it has been expected that the implementation and the deployment of the ABR service would be much easier than other bandwidth-guaranteed services, such as the CBR or the VBR service. In reality, however, the implementation of ABR-capable switches appears to be much more difficult than originally expected. The difficulty mainly lies in the designing of a simple, scalable, and stable ABR flow algorithm, more specifically an ER allocation algorithm in an asynchronous and distributed network environment.
  • ABR queues in the network can hardly be stabilized when the transmission rates of ABR sources are determined based on the network state information at different time.
  • a binary feed back mechanism either EFCI or RR marking, or both
  • the ABR queues in a steady state inevitably exhibits persistent oscillation with its magnitude and period.
  • Meerkov formulated the rate-based flow control problem as a discrete-time feedback control problem with the delay, and derived an ER allocation algorithm that achieves the asymptotic stability and allows for the arbitrary control of the closed-loop performance. This is described in "Feedback Control of
  • r[k] is the ER calculated by the switch at the discrete time k
  • q[k] is per- class ABR queue length at the time k
  • qT is a target queue length
  • ⁇ i and ⁇ j are controller gains
  • ⁇ max is the largest RTD of an ABR VC
  • I is an arbitrary constant greater than 0.
  • the remotely bottlenecked VCs cannot fairly share the link as the bottleneck occurring at another link if the transmission rates of the VCs are not limited by their PCRs (Peak Cell Rates). In contrast, if the algorithm (1) is applied, there exists no such an undesirable equilibrium point.
  • the above algorithm needs to be implemented in hardware with a minimal required memory capacity or hardware, and the operation accuracy is required to make the algorithm work.
  • an object of the present invention to provide an ABR service engine in a packet switching system, for which the ABR service algorithm can be implemented with minimal hardware or memory requirements and produce accurate operation results.
  • the above object of the present invention can be achieved by providing an ABR
  • a forward cell processing unit generates a first start signal and extracts CCR (Current Cell Rate) and MCR (Minimum Cell Rate) from a forward RM (Resource Management) cell upon receipt of the forward RM cell.
  • ) estimation unit determines whether (CCR-MCR) is less than ER
  • An ER engine calculates the ER by subtracting (((average queue length - previous average queue length) x first gain) ⁇ calculated
  • a backward cell processing unit determines whether the ER calculated by the ER engine is less than the sum of ER and MCR extracted from a backward RM cell upon receipt of the backward RM cell, then writes the calculated ER in the backward RM cell if the calculated ER is less than the sum of ER and MCR.
  • a timer feeds the second start signal to the
  • FIG. 1 illustrates the configuration of a packet switching network according to the preferred embodiment of the present invention
  • FIG. 2 is a block diagram of an I/O card for a switch shown in FIG. 1 ;
  • FIG. 3 is a block diagram of an ABR service engine according to the preferred embodiment of the present invention;
  • FIG. 4 illustrates the structure of an RM cell
  • FIG. 5 is a block diagram of a forward cell processing unit shown in FIG. 3;
  • FIG. 6 is a block diagram of a forward cell decoder shown in FIG. 5;
  • FIG. 7 is a block diagram of a cell element counter shown in FIG. 6;
  • FIGs. 8 and 9 illustrate cell buffering
  • FIG. 10 is a block diagram of an EFCI marker shown in FIG. 6;
  • FIG. 11 is a block diagram of a
  • FIG. 12 is a flowchart illustrating the operation of a ⁇ computation decider and a ⁇ calculator shown in FIG. 11 ;
  • FIG. 13 is a flowchart illustrating the operation of the
  • FIG. 14 is a block diagram of an ER engine shown in FIG. 3;
  • FIG. 15 is a block diagram of a gain selector shown in FIG. 14;
  • FIG. 16 is a flowchart illustrating the operation of the gain selector shown in
  • FIG. 15
  • FIG. 17 is a flowchart illustrating the operation of the ER engine shown in FIG.
  • FIG. 18 is a block diagram of a backward cell processing unit shown in FIG. 3;
  • FIG. 19 is a block diagram of a backward cell decoder shown in FIG. 18;
  • FIG. 20 is a block diagram of an Nr corrector.
  • FIG. 1 illustrates the configuration of a packet switching network for implementing the ABR service according to the preferred embodiment of the present invention.
  • the packet switching network includes a plurality of switches El, E2, and E3. Each switch is connected to a plurality of sources.
  • the first switch El is connected to a first through a Nth sources, SI to SN.
  • Each source transmits/receives data through a switch connected thereto. Data transmitted from the source reaches a destination in a so-called VC path having a plurality of nodes.
  • a source-generated RM cell is transmitted to a destination through a VC path.
  • the transmission direction of the cell is forward.
  • the destination processes the forward RM cell and transmits back to the source through the backward RM cell.
  • Switches are provided to write the allowed bandwidth information in the backward RM cell.
  • the source adapts its rate to changing network conditions based on the received bandwidth information.
  • the bandwidth- related information includes EFCI which provides information about the available bandwidth, CI (Congestion Indication) that allows a network element to indicate that there is congestion in the network, and NI (No Increase) that is used to prevent a source from increasing its ACR (Allowed Cell Rate).
  • EFCI in a data cell indicates congestion.
  • a switch calculates a bandwidth available for the ABR service, writes the calculated available bandwidth information on a backward RM cell, then transmits the backward RM cell to a source.
  • An ABR engine serving this function is provided in an input/output (I/O) port card of the switch.
  • FIG. 2 is a block diagram of the I/O port card.
  • the I/O port card 100 includes an I/O buffer management unit 102, an ABR service engine 104, and an output interface 106.
  • the I/O buffer management unit 102 is connected to the switch and responsible for I/O queuing.
  • the I/O buffer management unit 102 applies a queue write signal to the ABR service engine 104 for queue writing and a queue read signal to the ABR service engine 104 for queue reading.
  • the ABR service engine 104 processes the ABR algorithm and its related operations for the ABR service based on various parameters received from a microprocessor 108.
  • the output interface is connected to the switch and responsible for I/O queuing.
  • the I/O buffer management unit 102 applies a queue write signal to the ABR service engine 104 for queue writing and a queue read signal to the ABR service engine 104 for queue reading.
  • the ABR service engine 104 processes the ABR algorithm and its related operations for the ABR service based on various
  • 106 acts as a user network interface at the ATM layer.
  • FIG. 3 is a block diagram of the ABR service engine 104.
  • a forward cell processing unit 200 receives a forward RM cell and provides a first start signal to a
  • estimation unit 202 assumes the queuing in the output port.
  • the forward cell processing unit 200 extracts the CCR (Current Cell Rate) and the MCR (Minimum Cell Rate) from the forward RM cell and feeds them to the
  • CCR Current Cell Rate
  • MCR Minimum Cell Rate
  • the forward cell processing unit 200 marks the EFCI in a data cell among input forward cells.
  • a floating-point number system is used to provide precision and range in obtaining ER.
  • the floating-point number guarantees sufficient precision in order to prevent the problem associated with the feedback of ER value.
  • the floating-point number system includes all range of numbers that can be computed in the ER engine.
  • estimation unit 202 determines whether the received RM cell contributes to
  • ⁇ represents the updated ER measured by the ER engine 208 at a predetermined time interval.
  • estimation unit 202 estimates ]Q
  • estimation unit 202 uses ⁇ received from the ER engine 208.
  • ⁇ is the margin to avoid the underestimation of the number of locally bottlenecked VCs particularly near the steady state.
  • the CCR of a locally bottlenecked VC stays around the sum of the MCR and the common ER.
  • ⁇ the VC could be counted wrongly as a remotely bottlenecked VC even for a small perturbation in the CCR.
  • ⁇ 0.9 is the recommended choice.
  • the embodiment of the present invention is characterized in that the node keeps updating the ER periodically regardless of arrival of RM cells.
  • the benefit of the background calculation is that the latest ER prepared by the ER engine 208 is directly provided to the estimator unit 202, upon arrival of an RM cell in the corresponding node.
  • the ER engine 208 calculates the ER upon receipt of a third start signal that is generated periodically from the timer 210 and feeds the calculated ER to a backward cell processing unit 212 so that the backward cell processing unit 212 can write the calculated ER in a backward RM cell.
  • a queue counter 206 provides the current queue length and the number of queue variations to the ER engine 208 using the queue write signal and the queue read signal received from the I/O buffer management unit 102.
  • the queue counter 206 feeds the queue length to the forward cell processing unit 200 to allow the forward cell processing unit 200 to detect the EFCI congestion and write the EFCI mark.
  • the queue counter 206 feeds the queue length to the backward cell processing unit 212 to allow the backward cell processing unit 212 to detect "congestion” and "serious congestion” for RR service and to write NI (No Increase) and CI (Congestion Indication) marks in the backward RM cell.
  • the backward cell processing unit 212 determines whether the sum of the ER and MCR of a received backward RM cell is less than the ER transmitted from the ER engine 208. If the sum is less than the ER delivered from the ER engine 208, the backward cell processing unit 212 writes the ER of the ER engine 208 in the backward RM cell. In addition, the backward cell processing unit 212 detects congestion and serious congestion based on the received queue length and the NI and CI marks of the backward RM cell when detecting the RM cell. After completing the ER writing and NI and CI markings, the backward cell processing unit 212 calculates CRC for the backward RM cell and writes the CRC in the backward RM cell.
  • the timer 210 generates the second start signal every first predetermined period and provides it to the
  • the timer 210 also generates the third start signal every second predetermined period and provides it to the ER engine 208.
  • a microprocessor interface 204 provides parameters received from the microprocessor 108 to the
  • the parameters are latched in registers, which is a well-known technique and will not be described herein.
  • FIG. 4 illustrates the structure of an RM cell.
  • the RM cell is comprised of ATM Header, Protocol Identifier, Message Type, ER, CCR, MCR, Queue Length, Sequence Number, and CRC.
  • ATM Header has PTI (Payload Type Identifier) that defines a payload type. One PTI bit is used for EFCI.
  • DIR indicates which direction of data flow is associated with the RM cell,
  • BN indicates whether the RM cell is a backward explicit congestion notification (BECN) cell (i.e., non-source generated) or not, CI (Congestion Indication) allows a network element to indicate that there is congestion in the network, and NI (No Increase) is used to prevent a source from increasing its ACR (Allowed Cell Rate).
  • the CCR Current Cell Rate
  • the MCR Minimum Cell Rate
  • ER is an available bandwidth written in a backward source-generated RM cell by the ABR service engine as the RM cell passes through the switch. Only when the calculated available bandwidth of the ABR service engine is less than the existing available bandwidth, the former value is written in the ER field. Therefore, the smallest available bandwidth in the VC path is conveyed to the source.
  • FIG. 5 is a block diagram of the forward cell processing unit 200 that deals with forward RM cells.
  • a UTOPIA interface 300 of the forward cell processing unit 200 provides the UTOPIA interfacing.
  • UOPIA Physical Layer Interface for ATM
  • UOPIA defines the interface between the physical layer and the upper layer module, such as the ATM layer, is followed in the input of the cell decoder and the output of the cell encoder.
  • a forward cell decoder 302 receives a forward cell and an SOC (Start of Cell) signal and checks whether the forward cell is an RM cell or a data cell.
  • SOC Start of Cell
  • the forward cell decoder 302 determines whether the RM cell is source-generated or not. In the case of a source-generated RM cell, the forward cell decoder 302 performs CRC on the RM cell. If no CRC errors are detected, it generates a first start signal, extracts CCR and MCR from the RM cell, then provides the first start signal and the CCR & MCR to the
  • FIG. 6 is a detailed block diagram of the forward cell decoder 302. Referring to FIG. 6, a cell element counter 400 starts to count forward clock pulses when the SOC
  • FIG. 7 is a detailed block diagram of the cell element counter 400. Referring to FIG.
  • a flip-flop D has an input terminal D connected to a power supply, a clock terminal for receiving the SOC signal, and a reset terminal for receiving the reset signal.
  • the flip-flop D generates a cell start signal that becomes high upon receipt of the SOC signal and low upon receipt of the reset signal.
  • the cell start signal and the reset signal are applied to an AND gate (AND).
  • the AND gate generates a signal for resetting a counter (CNT) when both signals are low at the same time.
  • the counter counts forward clock pulses and is reset when the cell start signal and the reset signal are simultaneously generated.
  • the output of the counter and cell type/2 are applied to the input of a subtracter (AD).
  • the subtracter subtracts the cell type/2 from the output of the counter and outputs the subtraction result as a cell count.
  • the cell type/2 may be provided by the microprocessor 108.
  • the generated cell count by the cell element counter 400 is applied to a comparator 402.
  • the comparator 402 generates a PTI clock signal when the cell count indicates the position of PTI in the forward RM cell, a DIR_BN clock signal when it indicates the position of Message Type, a CCR clock signal when it indicates the position of CCR, and an MCR clock signal when it indicates the position of
  • CCR, and MCR clock signals of the first register unit 404 are applied to a PTI register 406, a DIR_BN register 408, a CCR register 410, and an MCR register 412, respectively.
  • the cell buffer MUX 414 reads 16 cell bits from a second register 420, and if the added header is five bytes, it reads 8 cell bits from the second register 420 and 8 bits from a first register 418. Thus, cells are arranged regardless of a 4-byte header or a 5 -bit header.
  • FIGs. 8 and 9 illustrate RM cell buffering in the first and second registers 418 and 420.
  • An RM cell is buffered in the first and second registers 418 and 419 at a byte level.
  • the first two bytes are buffered in the registers in alignment, as shown in FIG. 8.
  • the first two bytes of the RM cell are buffered in non-alignment, as shown in FIG. 9.
  • Headers are identified by cell type. If cell type is 0100, this indicates that the 4-byte header is added. If cell type is 0101, this indicates that the 5-byte header is added. That is, the header of the RM cell can be identified by checking the LSB (Least Significant Bit) of the cell type.
  • the cell buffer MUX 414 receives the LSB of the cell type. If the LSB is 0, the cell buffer MUX 414 reads 16 bits from the second register 420 and if the LSB is 1, the cell buffer MUX 420 reads 8 bits from the second register 414 and 8 bits from the first register 418.
  • the cell buffer MUX 414 arranges the read RM cell bits and outputs the RM cell to a second register unit 416.
  • the second register unit 416 outputs the received RM cell in synchronization to the forward clock signal to the PTI register 406, the DIR BN register 408, the CCR register 410, and the MCR register 410.
  • the PTI register 406, the DIR_BN register 408, the CCR register 410, and the MCR register 412 latch corresponding data received at the time when the PTI, DIR_BN, CCR, and MCR clock signals are respectively generated.
  • the PTI register 406, the DIR_BN register 408, the CCR register 410, and the MCR register 412 latch PTI, Message Type, CCR, and MCR of the RM cell and the CCR and MCR are fed to the
  • a RM cell detector 428 receives the Message Type and determines whether the corresponding cell is a forward source-generated RM cell by checking the DIR and BN of Message Type. If the cell is a forward source-generated RM cell, the RM cell detector 428 generates an RM start signal and feeds it to an EFCI marker 430 and an AND gate. The AND gate generates the first start signal when a CRC error detection signal and the RM start signal are concurrently generated and the generated first start signal is provided to the IQI estimation unit 202.
  • the EFCI marker 430 marks EFCI in the PTI of the cell header. If a header is added to the cell, the
  • the PTI may pass through the first to fifth registers 418 to 426 as lower eight bits or upper eight bits of the cell.
  • the EFCI marker 430 adaptively marks the EFCI, which will be described with reference to FIG. 10.
  • the PTI passes through the first to fifth registers 418 to 426 as the upper eight bits. If a 5-byte header is added to the cell, the PTI passes through the first to fifth registers
  • a first AND gate (AND1) of the EFCI marker 430 provides 1 to a first OR gate (OR1) when the congestion signal and the LSB of the cell type are 1 s concurrently.
  • the first OR gate OR-gates the EFCI bit of the PTI with the output of the first AND gate. That is, the EFCI of the PTI that has passed as the upper eight bits is marked to 1 when the congestion signal and the LSB of the cell type are Is at the same time.
  • a second AND gate (AND2) of the EFCI marker 430 provides 1 to a second OR gate (OR2) when the congestion signal and the LSB of a cell type inverted by the inverter are Is at the same time.
  • the second OR gate OR-gates the EFCI bit of the
  • the first to fifth registers 418 to 426 buffer the received forward cell along with the SOC signal and an Empty signal.
  • estimation unit 202 for estimating IQI using the first start signal and the CCR & MCR will be described hereinbelow with reference to FIG. 11.
  • the IQI estimation unit 202 is comprised of a ⁇ computation decider 500 for deciding whether an RM cell contributes to
  • the ⁇ computation decider 500 checks whether K*ER received from the ER engine 208 is less than the subtraction of the CCR (Current Cell Rate) and the MCR
  • a first register 506 in the ⁇ computation decider 500 provides the K*ER received from the ER engine 208 in synchronization with the SOC signal to a number system converter 508.
  • the number system converter 508 converts the K*ER to a 32-bit floating point number and outputs the floating point number as ER to an input terminal B of a first adder 510.
  • the first adder 510 receives the MCR and ER respectively through its input terminals A and B, adds the MCR and ER, and outputs the sum to a B input terminal of a comparator 512 through its output terminal C.
  • the comparator 512 receives the CCR and the sum of MCR and ER through its input terminals A and B, respectively, compares the sum with CCR, then provides the comparison result to an And gate 514. If the sum of MCR and ER is less than CCR, the AND gate 514 outputs a high signal to a second register 516 upon receiving the first start signal.
  • the second register 16 outputs the signal received from the AND gate 514 as the signal S upon receipt of a signal END_I_clk. That is, the signal S is 1 and applied to the ⁇ calculator 502 when there is no CRC error in a received cell and when K*ER is less than CCR-MCR.
  • the ⁇ calculator 502 calculates and accumulates the contribution degree ⁇ of RM cells received for the first period (i.e., a
  • Nrm is a forward RM cell transmission period negotiated upon establishment of a connection.
  • Nrm/first period (being the period of the second start signal) may be provided by the microprocessor 108.
  • a number system converter 518 in the ⁇ calculator 502 converts the CCR received from the forward cell processing unit 200 to a 32-bit floating point number.
  • a divider 520 receives the converted CCR and the Nrm/second start signal period upon the generation of the MCR clock signal and divides the Nrm/second start signal period by the CCR.
  • a third register 522 latches the output of the divider 520 on receiving a DONE signal from the divider 520.
  • a second adder 524 adds the previous ⁇ ⁇ prev and the output of the third register 522 upon receipt of the signal DONE from the divider 520.
  • a fourth register 526 latches the output of the second adder 524 according to a clock signal from an AND gate 528 when a DONE signal received from the second adder 524 and the signal S received from the AND gate 528 are Is at the same time, and outputs the latched value as ⁇ .
  • the ⁇ is fed to the
  • the ⁇ calculator 502 Upon receipt of the signal S, the ⁇ calculator 502 does not start to calculate ⁇ but outputs the calculated ⁇ , to thereby implement ⁇ computation in real time.
  • the divider 520 and the second adder 524 are reset by a reset signal generated through an inverter 530 and an AND gate 532 when the reset signal and the second start signal are simultaneously generated. Therefore, the accumulated ⁇ is reset to 0 every time the second start signal is generated.
  • the ⁇ computation decider 500 determines whether K*ER is less than CCR-MCR in step 600. If K*ER is less than CCR-MCR, the ⁇ calculator 502 calculates and then accumulates ⁇ in step 602.
  • calculator 504 activates the IQI calculator 504 upon receiving the second start signal and provides overall control to the IQI calculator 504.
  • a 1- ⁇ calculator 536 subtracts a low pass filtering parameter ⁇ of a IQI generation formula from 1.
  • a register unit 538 latches nr being a total
  • a first selector 540 selects some of a plurality of values received from the register unit 538 and transmits the selected values to a multiplier 542 or a third adder 544 under the control of the controller 534.
  • the multiplier 542 and the third adder 544 multiply and add their received outputs from the first selector 540 and transmit the operation results to the second selector 546.
  • the second selector 546 provides the outputs of the multiplier 542 and the third adder 544 to a limiter 548 or the register unit 538 under the control of the controller 534.
  • the limiter 548 simply outputs a value received from the second selector
  • the limiter 548 limits the value to 0 and outputs 0 as
  • the controller 534 controls the first and second selectors 540 and 546 to compute
  • the controller 534 controls the first selector 540 to feed nr and IQIprev to the third adder 544 and (1- ⁇ ) and ⁇ to the multiplier 542 in step 1.
  • the third adder 544 adds nr and IQIprev and feeds (
  • the multiplier 542 multiplies ⁇ by (1- ⁇ ) and feeds ⁇ x (1- ⁇ ) to the second selector 546.
  • the controller 534 controls the second selector 546 to feed back the outputs of the third adder 544 and the multiplier 542 to the register unit 538.
  • step 2 the controller 534 controls the first selector 540 to provide (
  • the controller 534 controls the second selector 546 to feed (
  • step 3 the controller 534 controls the first selector 540 to provide (
  • the controller 534 since
  • the limiter 548 limits
  • is applied to the ER engine 208.
  • Arithmetic units for floating point calculation may be used as the first to third adders, 510, 522, and 544 and the multiplier 542 in the
  • FIG. 14 is a block diagram of the ER engine 208.
  • estimation unit 202 will be described referring to FIG. 14.
  • a number system converter 700 in the ER engine 208 converts the target queue length qT, the second period ⁇ , and a comparison margin K to be multiplied by ER received from the microprocessor 114 through the microprocessor interface 204 to 32-bit floating point numbers and feeds them to a first selector 704.
  • the number system converter 700 also converts
  • a gain selector 702 receives a queue length gTH for gain selection and gains A0, Al, B0, and BI from the microprocessor 114 and the current queue length q from a register unit 714 and compares gTH with q. If q is less than gTH and Aland BI have never been selected as gains A and B, the gain selector 702 selects A0 and B0 as A and
  • the gain selector 702 selects Al and BI as A and B and provides them to the first selector 704. If q is greater than gTH, the gain selector 702 selects Al and BI as A and B and provides them to the first selector 704.
  • FIG. 15 is a block diagram of the gain selector 702. The operation of the gain selector 702 will be described with reference to FIG. 15.
  • a subtracter 800 subtracts gTH from q.
  • a comparator 802 determines whether the subtraction result is less than 0. If the subtraction result is less than 0, the comparator 802 outputs 0 and if the subtraction result is greater than 0, the comparator 802 outputs 1.
  • the output of the comparator 802 is applied as a clock signal to a flip-flop 804.
  • the flip-flop 804 is reset at an initialization state, outputs 0s, and then outputs Is received through its input terminal through its output terminal at rising edges of a clock signal. Since q is increased from 0 gradually, the flip-flop 804 outputs 0s until q reaches gTH and then outputs Is regardless of q.
  • the output of the flip-flop 804 is applied as a select signal to first and second selectors 806 and 808.
  • the first and second selectors 806 and 808 receive A0 & Aland B0 & BI, respectively. If the output of the flip-flop 804 is 0, they output A0 and B0 as A and B. If the output of the flip-flop 804 is 1, they output Aland BI as A and B.
  • the gain selector 702 determines whether q is less than gTH in step
  • step 902. If q is less than gTH, the gain selector 702 proceeds to step 902. Otherwise, it jumps to step 904.
  • step 902 the gain selector 702 checks whether the current state is an initialization state where Aland BI are not selected as A and B. In the initialization state, the gain selector 902 selects A0 and B0 as A and B in step 906.
  • the first selector 704 provides qr, ⁇ ,
  • the multiplier 706, the divider 708, and the adder 710 subject their received values to multiplication, division, and addition and output operation results to a second selector 712.
  • the second selector 712 transmits the operation results of the multiplier 706, the divider 708, and the adder 710 to the register unit 714 under the control of the ER engine controller 730.
  • the register unit 714 is comprised of a first register portion 716, a second register portion 722, and a third register portion 728.
  • the first register portion 716 includes a first register 718 for latching the average queue length q received from the second selector
  • the second register portion 722 includes feedsback operation results received from the second selector 712 to the first selector 704.
  • the third register portion 728 includes a third register 724 for latching ER delivered from the second selector 712 and outputting the latched ER to the first selector 704 and a fourth register 726 for transmitting the ER latched in the third register 724 as the previous ER ERprev to the first selector 704.
  • the ER engine controller 730 controls the first and second selectors 704 and
  • ER ER PREV - ⁇ -r ⁇ ⁇ q - q PREV ⁇ - T ⁇ r x (q - Q, ⁇ (6).
  • the ER engine controller 730 controls the first selector 704 to send the queue variation number and the queue length received from the number system converter 700 to the divider 708 and
  • the ER engine controller 730 controls the second selector 712 to feed back q received from the divider 708 to the first selector 704 through the first register 714 and the co ⁇ ected
  • q is provided to the gain selector 702 so that the gain selector 702 can select A and B by comparing q with gTH.
  • step 2 the ER engine controller 730 controls the first selector 704 to send ⁇ received from the number system converter 700 and the gain B selectively received from the gain selector 702 to the multiplier 706.
  • the multiplier 706 multiplies ⁇ by the gain B and transmits the product (1) to the second selector 712.
  • the ER engine controller 730 controls the second selector 712 to feed back (1) to the first selector 704 through the second register portion 722.
  • step 3 the ER engine controller 730 controls the first selector 704 to provide q latched in the first register 718 and qprev latched in the second register 720 to the adder 710 and (1) and the co ⁇ ected
  • the divider 708 divides (1) by the corrected
  • the ER engine controller 730 controls the second selector 712 to feed back
  • step 4 the ER engine controller 730 controls the first selector 704 to provide q latched in the first register 718 and qr received from the number system converter 700 to the adder 710. Then, the adder 710 subtracts qr from q and transmits the subtraction result (3) to the second selector 712. The ER engine controller 730 controls the second selector 712 to feed back (3) to the first selector 704 through the second register portion
  • step 5 the ER engine controller 730 controls the first selector 704 to provide
  • the multiplier 706 multiplies (q-qprev) by A and provides the product (4) to the second selector 712.
  • the ER engine controller 730 controls the second selector 712 to feed back (4) to the first selector 704 through the second register portion 722.
  • the divider 708 divides (1) by corrected
  • the ER engine controller 730 controls the second selector 712 to feed back (1)/
  • step 6 the ER engine controller 730 controls the first selector 704 to provide
  • the multiplier 706 multiplies (3) by (5) and provides the product (6) to the second selector 712.
  • the divider 708 divides (4) by the corrected
  • the ER engine controller 730 controls the second selector 712 to feed back (6) and (7) to the first selector 704 through the second register portion 722.
  • step 7 the ER engine controller 730 controls the first selector 704 to provide
  • the ER engine controller 730 controls the second selector 712 to feed back (7) to the first selector 704 through the second register portion 722.
  • step 8 the ER engine controller 730 controls the first selector 704 to provide
  • the adder 710 subtracts (8) from ERprev and outputs the sum as ER to the second selector 712.
  • the ER engine controller 730 controls the second selector 712 to feed back ER to the first selector 704 through the third register 726.
  • step 9 the ER engine controller 730 controls the first selector 704 to provide ER received from the third register 726 and K received from the number system converter 700 to the multiplier 706.
  • the multiplier 706 converts ER in the floating point format to a 16-bit integer by adding ER and K and outputs the integer as K*ER through the second register portion 722.
  • K*ER is the final ER output from the ER engine 208.
  • the multiplier 706, the divider 708, and the adder 710 are repeatedly used in steps 1 through 9 to reduce hardware requirements.
  • Arithmetic units for floating point computation are used as the multiplier 706, the divider 708, and the adder 710 to increase computation accuracy.
  • FIG. 18 is a block diagram of the backward cell processing unit 212 for processing backward RM cells. The configuration and operation of the backward cell processing unit 212 will be described referring to FIG. 18.
  • a UTOPIA interface 1000 in the backward cell processing unit 212 provides UTOPIA interfacing.
  • a backward cell decoder 1002 receives the SOC signal and a backward cell from the UTOPIA interface 1000 and determines whether the backward cell is a source-generated RM cell. If the received cell is a source-generated RM cell, the backward cell decoder 1002 reads ER and MCR from the RM cell and feeds them to an ER writing decider 1008. Upon receipt of the ER from the ER writing, the backward cell decoder 1002 writes the ER in the RM cell.
  • the backward cell decoder 1002 marks NI or CI in the RM cell according to the NI and CI received from a congestion detector 1006.
  • the backward cell decoder 1002 receives CRC for the RM cell with ER and NI/CI marked from a CRC check and generation unit 1004 and writes the CRC in the RM cell.
  • the CRC check and generation unit 1004 detects CRC e ⁇ ors from the received backward RM cell, generates CRC for the RM cell with ER and NI/CI marked, and transmits the CRC to the backward cell decoder 1002.
  • the congestion detector 1006 receives a high queue threshold qHT and a low queue threshold qLT from the microprocessor 108.
  • the ER writing decider 1008 determines whether the sum of the MCR of the input RM cell received from the backward cell decoder 1002 and ER received from the ER engine 208 is less than the ER of the input
  • the ER writing decider 208 provides the ER delivered from the ER engine 208 to the backward cell decoder 1002.
  • FIG. 19 is a block diagram of the backward cell decoder 1002. Referring to FIG. 19, a cell element counter 1100 starts to count backward clock pulses when the
  • SOC signal is generated, outputs the count value as a cell count, and is reset by a reset signal that is generated when the cell count represents a whole RM cell.
  • the 1102 generates the PTI clock signal every time the cell count indicates the position of the PTI in the RM cell, the DIR_BN clock signal every time the cell count indicates the position of Message Type, the ER clock signal every time the cell count indicates the position of ER, the MCR clock signal every time the cell count indicates the position of
  • the PTI, DIR BN, ER, MCR, and END clock signals are output from the comparator 1102 in synchronization to the backward clock signal through a first register unit 1104.
  • An inverter inverts the EN clock signal received from the first register unit 1104 and outputs the inverted signal as the reset signal.
  • the first register unit 1104 applies the PTI, DIR_BN, ER, and MCR clock signals to a PTI register 1106, a DIR_BN register 1108, an ER register 1 110, and an MCR register 1112, respectively.
  • a cell buffer MUC 1 114 reads 16 cell bits from the second register 1120 if a 4- byte header is added, and 8 cell bits from the second register 1120 and 8 cell bits from the first register 1118 if a 5-byte header is added.
  • a second register unit 1116 outputs a received RM cell in synchronization to the backward clock signal to the PTI, DIR_BN, ER, and MCR registers 1106, 1108, 1110, and 1112.
  • the above registers latch their received data when the PTI, DIR_N, ER, and MCR clock signals are generated, separately. As a result, the registers latch PTI, Message Type, ER, and MCR of the RM cell, respectively.
  • An RM cell detector 1132 receives PTI and Message Type to determine whether the received backward cell is a source-generated backward RM cell.
  • An ER writing decider 1008 receives ER and MCR to decide as to whether to write ER delivered from the ER engine 208 in the received RM cell.
  • the RM cell detector 1132 determines whether a co ⁇ esponding cell is a source- generated backward RM cell by checking the PTI and DIR & BN included in Message Type. In the case of a source-generated backward RM cell, the RM cell detector 1132 generates an RM start signal.
  • First to fifth registers 418 to 426 buffer receive forward cells and output buffered SOC and Empty signals as SOC and Enable signals.
  • An NI & CI marker 1124 is interposed between the third register 1122 and the fourth register 1126.
  • the NI & and CI marker 1124 marks NI and CI of an RM cell buffered between the third and fourth registers 1122 and 1126 with NI and CI information received from the congestion detector 1006.
  • An ER writer 1128 is interposed between the fourth and fifth registers 1128 and 1130. The ER writer 1128 writes the ER received from the ER writing decider 1008 in the ER field of an RM cell buffered between the fourth and fifth registers 1126 and 1130.
  • NI and CI markings and the ER writing are well known and their detailed description is avoided here.
  • the reason for writing ER in an RM cell buffered between the fourth and fifth registers 1126 and 1130 is that the RM cell should be buffered during the time taken for the ER writing decider 1008 to decide whether the ER is to be written or not since the decision is made after reading MCR despite MCR subsequent to ER in position.
  • a received backward RM cell is buffered using a few registers, thereby preventing unnecessary use of memory.
  • Nr may vary Nr without prior notice and variation of Nr has a great influence on each computation. Therefore, an Nr corrector can be added to the ABR service engine 104.
  • FIG. 20 is a block diagram of the Nr corrector.
  • the first register 1200 latches Nr and provides it to a second register 1202 and a subtracter 1204.
  • the second register 1202 latches the Nr received from the first register 1200 as the previous Nr.
  • the subtracter 1204 obtains the variation of Nr, Ndiff by subtracting the Nr received from the second register 1202 from the Nr received from the first register 1200.
  • a comparator 1206 determines whether Ndiff is 0. If Ndiff is not 0, the comparator 1206 enables an adder 1208 to add the previous Nr and Ndiff, thereby co ⁇ ecting Nr.
  • the co ⁇ ected Nr is fed as the previous Nr to the adder 1208 through a third register 1210.
  • the co ⁇ ected Nr is provided to the
  • the ABR service engine implements an ABR service algorithm in such a way that (1) maximal link utilization and minimal cell loss are guaranteed regardless of RTDs in an ABR closed loop; (2) ABR queue size requirements are minimized by ensuring asymptotical stabilization of ABR queues: (3) the MAX-MIN fairness based on the ATM forum standards is guaranteed by ensuring a fair share of an available bandwidth to each user; (4) communication network environmental change is fast reacted to such as changes in the number of ABR users and the ABR bandwidth; (5) all functions including EFCI, RR, and ER markings are provided as specified in the ATM forum traffic management specification; (6) high utilization, low cell loss, and the MAX-MIN fair rate allocation are achieved through the existence of an asymptotically stable operating point; (7) high responsiveness to network loading changes is achieved at multiple time scales, i.e., at the cell level rate changes of VBR and ABR VCs and at the cell level arrivals and departures of VBR
  • estimation and ER computation are performed not in real time but at every predetermined period.
  • estimation and the ER computation facilitate the control operation allow the ABR service engine to reuse arithmetic units, thereby minimizing the hardware requirements.
  • Internal floating point computation is implemented using the floating point calculators so that operation results are more accurate.
  • the ABR service engine obviates the need for storing an input backward RM cell by employing the scheme of deciding as to whether ER is to be written in the RM cell while buffering the RM cell in a few registers. As a result, memory use is minimized.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Signal Processing (AREA)

Abstract

L'invention concerne un moteur de service de débit binaire disponible (ABR) utilisé dans un système de commutation par paquets. Une unité de traitement de cellules avant génère un premier signal de départ et extrait un débit de cellule courant (CCR) et de débit de cellule minimum (MCR) d'une cellule de gestion de ressources (RM) avant, lorsqu'elle reçoit la cellule RM avant. Une unité d'estimation du nombre (|Q|) de circuits virtuels étranglés localement détermine si (CCR-MCR) est inférieur au débit binaire explicite (ER) lorsqu'elle reçoit le premier signal de départ, considère que la cellule RM reçue contribue à (|Q|) si (CCR-MCR) est inférieur à ER, accumule le degré de contribution et calcule |Q|. Un moteur ER calcule ER lorsqu'il reçoit un troisième signal de départ. Une unité de traitement de cellules arrière détermine si le ER calculé par le moteur ER est inférieur à la somme de ER et de MCR extraits d'une cellule RM arrière lorsqu'elle reçoit la cellule RM arrière et écrit le ER calculé dans la cellule RM arrière si le ER calculé est inférieur à la somme de ER et de MCR. Une horloge envoie le deuxième signal de départ à l'unité d'estimation de |Q| à chaque première période et le troisième signal de départ au moteur ER à chaque deuxième période.
PCT/KR2000/001099 1999-10-02 2000-10-02 Moteur de service abr utilise dans un systeme de commutation par paquets WO2001026306A1 (fr)

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JP2001529148A JP2003511907A (ja) 1999-10-02 2000-10-02 パケット交換システムの利用可能なビット率サービス装置
EP00966568A EP1135895A1 (fr) 1999-10-02 2000-10-02 Moteur de service abr utilise dans un systeme de commutation par paquets
CA002351352A CA2351352A1 (fr) 1999-10-02 2000-10-02 Moteur de service abr utilise dans un systeme de commutation par paquets

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US60/157,421 1999-10-02

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EP1135895A1 (fr) 2001-09-26
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KR100383571B1 (ko) 2003-05-14
CN1339210A (zh) 2002-03-06
KR20010050809A (ko) 2001-06-25

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