WO2001013431A1

WO2001013431A1 - Apparatuses for forming wire bonds from circuitry on a substrate to a semiconductor chip, and methods of forming semiconductor chip assemblies

Info

Publication number: WO2001013431A1
Application number: PCT/US2000/040680
Authority: WO
Inventors: Michael Bettinger; Ronald W. Ellis; Tracy Reynolds
Original assignee: Micron Technology, Inc.
Priority date: 1999-08-19
Filing date: 2000-08-18
Publication date: 2001-02-22
Also published as: KR20020035576A; AU7883000A; WO2001013431A9; JP2003527742A; KR100721274B1

Abstract

The invention encompasses a method of forming a semiconductor chip assembly. A substrate (12) has a pair of opposing surfaces (12, 13) and circuitry (16) formed on one of the opposing surfaces. A semiconductor chip (14) is joined to the substrate. A plurality of wires (28) join to the circuitry and extend over bonding pads (25) formed on the semiconductor chip. The wires are pressed down to about the bonding of the semiconductor chip with a tool (106). The tool is lifted from the wires, and the wires are adhered to the bonding pads of the semiconductor chip. The invention also encompasses an apparatus which comprises a support (102) for supporting the substrate (12) and the semiconductor chip (14), a pressing tool (106) movably mounted relative to the substrate, and which has deflecting surface (120) configured to press the wires into a slit (18) of the substrate when the pressing tool is moved toward the substrate. The deflecting surface is substantially planar, and has a sufficient length to extend within a predominate portion of the slit.

Description

Apparatuses For Forming Wire Bonds From Circuitry On _A

Substrate To A Semiconductor Chip, And Methods Of

Forming Semiconductor Chip Assemblies

TECHNICAL FIELD

The invention pertains to methods and apparatuses for forming

semiconductor chip assemblies. In particular aspects, the invention

pertains to methods and apparatuses for forming wire bonds in board-

on-chip packages.

BACKGROUND OF THE INVENTION

10 A prior art method of forming a board-on-chip package (which

11 can be generally referred to as a die package) is described with

₁₂ reference to Figs. 1-5. Referring first to Fig. 1, such illustrates a

i3 fragment of an assembly 10 comprising an insulative material

i₄ substrate 12. Substrate 12 can comprise, for example, a circuit board.

is Substrate 12 comprises a top surface 13 and slits 18 extending

16 therethrough. Circuitry 16 is formed on top of surface 13.

i7 Circuitry 16 and slits 18 form repeating patterns across top surface 13.

18 The repeating patterns define separate units 19, 21 and 23, each of

i9 which ultimately forms a separate board-on-chip package.

20 Referring to Figs. 2-4, an enlarged segment of substrate 12,

₂i I corresponding to unit 21, is shown in three different views. Fig. 2 is

22 a top view similar to the view of Fig. 1, Fig. 3 is view along the

23 I line 2-2 of Fig. 2, and Fig. 4 is a view along the line 4-4 of Fig. 3. Substrate 12 is inverted in the view of Fig. 3 relative to the view of

Figs. 1 and 2. Accordingly, surface 13 (referred to as a top surface in

referring to Figs. 1 and 2) is a bottom surface in the view of Fig. 3.

In referring to Fig. 3, surface 13 will be referred to as a first surface.

Substrate 12 comprises a second surface 15 in opposing relation

relative to first surface 13. A semiconductive material-comprising chip

(or die) 14 is adhered to surface 15 via a pair of adhesive strips 20.

Strips 20 can comprise, for example, tape having a pair of opposing

surfaces 22 and 24, with adhesive being provided on both of such

t opposing surfaces. Strips 20 typically comprise insulative material.

a Wire bonds 28 (only some of which are labeled in Fig. 2) extend from

i2 circuitry 16 and through slit 18 to electrically connect circuitry 16 to

i3 bonding pads 25 (only some of which are labeled in Fig. 2) associated

i-f with chip 14, and to accordingly electrically connect circuitry 16 with

is circuitry (not shown) comprised by chip 14. Chip 14 comprises a

i6 surface 17 which faces surface 15 of substrate 12. The bonding pads

i7 are on surface 17. (The wire bonds and bonding pads are not shown

is in Fig. 4 for purposes of clarity in the illustration.)

19 Fig. 5 illustrates further processing of the assembly 10.

20 Specifically, Fig. 5 illustrates units 19 and 21 of Fig. 1 after a first

21 encapsulant 40 is provided over wire bonds 28, and a second

22 encapsulant 42 is provided over chips 14 associated with units 19

3 and 21. First and second encapsulants 40 and 42 can comprise the same material and typically comprise an insulative material, such as, for

example, cured epoxy.

Conductive balls 31 are formed over portions of circuitry 16

(shown in Figs. 1 and 2) to form a ball grid array over circuitry 16.

Such array can subsequently be utilized to form a plurality of

interconnects from circuitry 16 to other circuitry (not shown).

Conductive balls 31 can be formed of, for example, tin, copper or gold.

Substrate 12 is subjected to a singulation process which separates

units 19 and 21 from one another, and thus forms individual board-on-

ιo chip packages from units 19 and 21. The singulation process can

u include, for example, cutting through encapsulant 42 and substrate 12.

i Difficulties can occur in the formation of the wire bonds

i3 associated with a board-chip-package. Among the methods commonly

!■* utilized for forming such wire bonds are a TESSERA™ process and a

is so-called tab bonding process. In either of such processes, the wires

i6 utilized for wire-bonding initially have one end bonded to circuitry 16.

17 The wires are provided to extend at least partially across slit 18 so that

is a second end (which is not bonded to circuitry 16) extends over or past

19 slit 18. A rod is then utilized to push the wires into slit 18 and to

20 hold the wires against chip 14 during an ultrasonic welding process.

2i The ultrasonic welding adheres the second end of the wires to bonding

22 pads 25. It would be desirable to develop alternative methods for forming wire bonds.

SUMMARY OF THE INVENTION

In one aspect, the invention encompasses a method of forming a

semiconductor chip assembly. A substrate is provided. Such substrate

has a pair of opposing surfaces and circuitry formed on one of the

opposing surfaces. A semiconductor chip is joined to the substrate.

The semiconductor chip has bonding regions thereon. A plurality of

ιo wires join to the circuitry and extend over the bonding regions of the

// semiconductor chip. The wires are pressed down to about the bonding

12 regions of the semiconductor chip with a tool. The tool is lifted from

a the wires, and subsequently the wires are adhered to the bonding

i4 regions of the semiconductor chip.

is In another aspect, the invention encompasses an apparatus for

i6 forming wire bonds from circuitry on a substrate to a semiconductor

17 chip joined to the substrate. Such apparatus comprises a support for

is supporting the substrate and the semiconductor chip. The apparatus

i9 further comprises a pressing tool movably mounted relative to the

20 substrate, and which has a deflecting surface configured to press the

2i wires into a slit of the substrate when the pressing tool is moved

22 toward the substrate. The deflecting surface is substantially planar, and

23 has a sufficient length to extend within a predominate portion of the slit.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

Fig. 1 is a diagrammatic, fragmentary view of a prior art

semiconductor assembly at a preliminary step of a die package forming

process.

10 Fig. 2 is an expanded view of a portion of the Fig. 1 assembly.

// Fig. 3 is a cross-sectional view along the line 3-3 of Fig. 2.

i2 Fig. 4 is a cross-sectional view along the line 4-4 of Fig. 3.

i3 Fig. 5 is a view of a portion of the Fig. 1 assembly shown being

14 subjected to prior art processing subsequent to that of Figs. 1-4.

is Fig. 6 is a diagrammatic, fragmentary, perspective view of an

i6 apparatus of the present invention being utilized to process a

i semiconductor chip assembly.

is Fig. 7 is a diagrammatic, top view of a tool encompassed by an

19 apparatus of the present invention.

20 I Fig. 8 is a cross-sectional, fragmentary view of the Fig. 6

2i apparatus shown at a processing step subsequent to that of Fig. 6, and

22 shown along the line 8-8 of Fig. 6.

23 Fig. 9 is a view of the Fig. 6 apparatus, shown along line 8-8

and shown at a processing step subsequent to that illustrated in Fiσ. 8

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of the

constitutional purposes of the U.S. Patent Laws "to promote the

progress of science and useful arts" (Article 1, Section 8).

The invention encompasses a new apparatus and method for

forming wire bonds. Referring to Fig. 6, an apparatus 100 of the

lo present invention is shown in fragmentary, perspective view.

;/ Apparatus 100 comprises a support 102 configured to support a

i2 semiconductor chip assembly 104, and a tool 106 configured to displace

i3 wires associated with semiconductor chip assembly 104 to form wire

i bonds.

is In the shown embodiment, semiconductor chip assembly 104

i6 comprises a portion of a prior art board-on-chip assembly of the type

1 described in the Background section of this disclosure with reference to

is Figs. 1-5. Accordingly, assembly 104 comprises a substrate 12, a

1 semiconductive material chip 14, and adhesive strips 20 joining chip 14

20 to substrate 12. Further, substrate 12 comprises an upper surface 13

2i having circuitry 16 formed thereon and a lower surface 15 to which

22 semiconductive material chip 14 is joined. Chip 14 has an upper

23 surface 17 having bonding pads 25 thereon (bonding pads 25 are not shown in Fig. 6 for purposes of clarity in the illustration, but are shown

in, for example, Fig. 2). Bonding pads 25 typically comprise a metal,

such as, for example, aluminum which can be ultrasonically welded to

bonding wires. Bonding pads 25 can be generically referred to herein

as bonding regions to indicate that the areas 25 simply constitute

regions to which wire bonds will be connected with chip 14, and do not

necessarily comprise the structures associated with bonding "pads".

A slit 18 extends through substrate 12, and specifically extends

from upper surface 13 of substrate 12 to lower surface 15 of

10 substrate 12. The bonding pads 25 (not shown in Fig. 6) are exposed

n through slit 18. A plurality of bonding wires 28 (only some of which i2 are labeled) are electrically connected with circuitry 16 and extend at

13 least partially over slit 18. The electrical connection of wires 28 to

i-f circuitry 16 preferably comprises a form of adhesion of wires 28 to

is circuitry 16, such that one end of each wire is bonded to circuitry 16,

i6 and accordingly adhered over upper surface 13 of substrate 12. Each

17 wire 28 has a second end which is not fixed, with such second end

s being configured to be bonded with a pad 25. In the shown

i embodiment, some of wires 28 extend entirely across slit 18, and some

20 of wires 28 extend only partially across slit 18. It is to be understood

2i that in particular embodiments of the invention, all of wires 28 can

22 extend entirely across slit 18, or none of wires 28 can extend entirely

23 across slit 18. Slit 18 is rectangular in shape, and comprises a length "x" and a

width "y". Further, slit 18 comprises a pair of ends 107 and 109

spaced from one another by length "x".

One of wires 28 is labeled as a first wire 110, and comprises the

wire closest to end 107. Another of wires 28 is labeled as a second

wire 112 and constitutes the wire closest to end 109. First wire 110 is

spaced from end 107 by a gap 114, and second wire 112 is spaced from

end 109 by a gap 116.

Tool 106 comprises a deflecting surface 120 configured to extend

ιo within gap 18 and push wires 28 down to about bonding pads 25 (with

u the term "about" indicating that the wires can be pressed all the way

i to contact bonding pads 25, or can be pressed into slit 18 to a distance

i3 which leaves wires 28 elevated above pads 25). Tool 106 is shown in

i-f Fig. 7 in a view which is upside down from that of Fig. 6, and which

is more clearly shows deflecting surface 120. Fig. 7 further shows that

i6 deflecting surface 120 is substantially planar, and that tool 106

1 comprises other substantially planar surfaces 122 and 124 which are

is connected to deflecting surface 120 through sidewalls 126 and 128,

i respectively. Planar surfaces 122 and 124 are preferably configured to

20 rest upon surface 13 (or, more specifically, circuitry over upper

2i surface 13) when deflecting surface 120 is inserted within slit 18. In

22 the shown preferred embodiment, sidewalls 126 and 128 extend non-

23 perpendicularly relative to planar surfaces 120, 122 and 124. Such non- perpendicular extension of sidewalls 126 and 128 relative to the planar

surfaces avoids formation of a "tight corner" in wires 28 when the wires

are deflected into slit 18 by tool 106. The term "tight corner" bein°*

utilized to refer to a corner which is less than or equal to about 90°.

Tight corners can be undesirable, in that they can reduce current flow

through a wire, and can also weaken the wire to cause breakage of

the wire.

Deflecting surface 120 has a length "z" which is preferably about

the same length as the length "x" of slit 18. Length "z" is preferably

10 least long enough to extend over a predominate portion of slit 18, and

// more preferably is long enough to extend from first wire 110 to second

i2 wire 112, such that the entire plurality of wires 28 are deflected

13 simultaneously by tool 106 when the tool is moved into slit 18. In

i-f particular embodiments, length "z" is long enough to extend past both

is of wires 110 and 112 (i.e., into gaps 114 and 116) to compensate for

i minor misalignment of surface 120 relative to slit 18.

i7 It is noted that the views of Figs. 6 and 7 show apparatus 100

18 as being a fragment. In preferred embodiments, apparatus 100 is

i utilized before singulation of individual chip packages from a substrate

20 (with the singulation being described with reference to prior art Fig. 5).

2i Apparatus 100 preferably comprises a repeating number of tools 106

22 such that there is a tool corresponding to each of the slits 18 repeated

3 across a substrate 12 (with the repeated slits described with reference to prior art Fig. 1) such that an entire substrate panel can be

simultaneously processed by moving a plurality of tools 106 into the

plurality of slits 18. In alternative embodiments, apparatus 100 can

comprise less tools 106 than there are slits 18 in a substrate, and the

tools 106 can be moved stepwise from one slit 18 to another across a

substrate panel.

Referring to Fig. 8, apparatus 100 is shown at a processing step

subsequent to that of Fig. 6, and in a cross-sectional view along line 8-8

of Fig. 6. Tool 106 has now been moved into slit 18 such that

10 deflecting surface 120 is pushing an end of wire 28 onto a surface of

// chip 14, and specifically onto a bonding pad 25. (A gap is shown

12 between tool 106 and wire 28 for clarity of illustration of wire 28. In

1 practice, tool 106 would be pressed against wire 28.) Although only one

i-t wire 28 is shown being deflected, it is to be understood that preferably

is all of the wires 28 of Fig. 6 are being simultaneously deflected by

i insertion of tool 106 into slit 18. Fig. 8 also shows that planar

7 surfaces 122 and 124 are configured to rest on circuitry 16 as deflecting

is surface 120 deflects wires 28 against pads 25. Surfaces 122 and 124 can

19 accordingly aid in holding the bonded ends of wires 28 onto circuitry 16

20 during the deflection of wire 28 by deflecting surface 120. Fig. 8 also

2i shows that sidewalls 126 and 128 extend non-perpendicularly relative to

22 the substantially planar surface 17 of chip 14.

23 Referring to Fig. 9, apparatus 100 is shown from the same view

as Fig. 8, and at a processing step subsequent to that of Fiσ. 8.

Specifically, tool 106 has been lifted to remove deflecting surface 120

from within slit 18, and wire 28 is adhered to pad 25. In the shown

embodiment, ultrasonic energy 150 is provided to adhere wire 28 to

pad 25. In particular embodiments, pad 25 can comprise, for example,

an aluminum surface; wire 28 can comprise, for example, gold or copper;

and the ultrasonic energy can effectively diffuse pad 25 and wire 28 to

weld wire 28 to pad 25.

ιo In preferred embodiments, tool 106 is entirely removed from within

a slit 18 prior to provision of ultrasonic energy to weld wire 28 to pad 25.

Such is in contrast to, for example, the Tessera™ process (described

i above with reference to prior art) wherein a wire is held in place during

i-f provision of ultrasonic energy. Also, the invention differs from both the

is tab bonding and Tessera™ processes in that most, and preferably all, of

i6 the wire bonds extending across a slit are simultaneously deflected in

17 a method of the present invention. In contrast, in the Tessera™ and

is tab bonding processes, the wires are deflected sequentially into a slit.

i9 It is noted that although the invention is described above with

20 reference to board-on-chip semiconductor fabrication processes, the

i invention can have application to other processes wherein wires are to

22 be deflected, as well as to other applications wherein wires are to be

3 utilized for wire bonding a semiconductor chip to circuitry. It is further noted that although ultrasonic welding is disclosed as a method of

bonding wire 2S to pad 25, the invention can be utilized with other

methods of adhering a wire to a semiconductor substrate, including, for

example, the utilization of a conductive epoxy.

In compliance with the statute, the invention has been described

in language more or less specific as to structural and methodical

features. It is to be understood, however, that the invention is not

limited to the specific features shown and described, since the means

herein disclosed comprise preferred forms of putting the invention into

10 effect. The invention is, therefore, claimed in any of its forms or

/ modifications within the proper scope of the appended claims

i appropriately interpreted in accordance with the doctrine of equivalents.

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Claims

CLAIMS:

1. A method of forming a semiconductor chip assembly, comprising:

providing a substrate having a pair of opposing surfaces and circuitry formed on one of said opposing surfaces;

joining a semiconductor chip to the substrate, the semiconductor chip having bonding regions;

forming a plurality of wires joined to the circuitry and extending

over the bonding regions;

pressing the wires down to about the bonding regions of the

semiconductor chip with a tool;

lifting the tool from the wires; and

after lifting the tool, and with the tool no longer pressing the

wires, adhering the wires to the bonding regions.

2. The method of claim 1 wherein the semiconductor chip is

adjacent the other of the opposing surfaces of the substrate.

3. The method of claim 1 wherein the adhering comprises

ultrasonic welding.

4. A method of forming a semiconductor chip assembly, comprising:

providing a substrate having circuitry formed thereover and a slit

extending therethrough;

joining a semiconductor chip to the substrate, the semiconductor

chip being beneath the substrate and having an upper surface facing the

substrate, the semiconductor chip having bonding regions associated with

its upper surface;

forming a plurality of wires joined to the circuitry and extending

at least partially across the slit;

pressing the wires into the slit with a tool configured to press the

wires down to about the upper surface of the semiconductor chip;

lifting the tool from the wires; and

after lifting the tool, and with the tool no longer pressing the

wires down to about the upper surface of the semiconductor chip,

adhering the wires to the bonding regions associated with the upper

surface of the semiconductor chip.

5. The method of claim 4 wherein at least some of the wires

extend entirely across the slit prior to the pressing. / 6. The method of claim 4 wherein all of the wires extend entirely across the slit prior to the pressing.

7. The method of claim 4 wherein none of the wires extend

entirely across the slit.

8. The method of claim 4 wherein the adhering comprises

ultrasonic welding.

9. A method of forming a semiconductor chip assembly comprising:

providing a substrate having circuitry formed thereover and a slit

extending therethrough; the slit having a length and a width, and having

a pair of ends spaced from one another by the length, the pair of ends

being a first end and a second end;

joining a semiconductor chip to the substrate, the semiconductor

chip being beneath the substrate and having an upper surface facing the

substrate, the semiconductor chip having bonding regions associated with

10 its upper surface;

// forming a plurality of wires joined to the circuitry and extending

i at least partially across the width of the slit, a first wire being closer

i3 to the first end than any of the other wires of the plurality of wires,

i4 and a second wire being closer to the second end than any of the other

is wires of the plurality of wires;

i6 pressing the plurality of wires into the slit with a tool configured

i7 to press the wires down to about the upper surface of the semiconductor

is chip, the tool extending from the first wire to the second wire and

i9 pressing the first and second wires simultaneously into the slit; and

20 after pressing the wires into the slit, adhering the wires to the

2i bonding regions associated with the upper surface of the semiconductor

22 chip.

23 / 10. The method of claim 9 wherein the adherinσ the wires comprises ultrasonically welding the wires to the bonding regions.

11. The method of claim 9 further comprising:

lifting the tool from the wires; and

wherein the adhering the wires occurs after lifting the tool and

with the tool no longer pressing the wires down to about the upper

surface of the semiconductor chip.

12. The method of claim 9 wherein at least some of the wires

extend entirely across the width of the slit prior to the pressing.

13. The method of claim 9 wherein a first gap is between the

first wire and the first end, wherein a second gap is between the second

wire and the second end, and wherein the tool extends into at least one

of the first and second gaps.

14. The method of claim 13 wherein the tool extends into both

of the first and second gaps.

15. An apparatus for forming wire bonds from circuitry on a

substrate to a semiconductor chip joined to the substrate; wherein the

substrate has a pair of opposing surfaces; wherein the circuitry is

proximate one of the opposing surfaces of the substrate and the

semiconductor chip is proximate an other of the opposing surfaces of

the substrate; wherein a slit extends through the substrate from the one

of the opposing surfaces to the other of the opposing surfaces; wherein

the slit has a length and a width, and has a pair of ends spaced from

one another by the length; and wherein a plurality of bonding wires are

10 provided to extend at least partially across the slit, the apparatus

u comprising:

i a support for supporting the substrate and semiconductor chip; and

i3 a pressing tool movably mounted relative to the substrate, the

i-f pressing tool having a deflecting surface configured to press the wires

is into the slit when the pressing tool is moved toward the substrate, the

16 deflecting surface being substantially planar and having a sufficient length

i7 to extend across a predominate portion of the length of the slit.

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16. An apparatus for forming wire bonds from circuitry on a substrate to a semiconductor chip joined to the substrate; wherein the

substrate has a pair of opposing surfaces; wherein the circuitry is

proximate one of the opposing surfaces of the substrate and the

semiconductor chip is proximate an other of the opposing surfaces of

the substrate; wherein a slit extends through the substrate from the one

of the opposing surfaces to the other of the opposing surfaces; wherein

the slit has a length and a width, and has a pair of ends spaced from

one another by the length, the pair of ends being a first end and a

10 second end; and wherein a plurality of bonding wires are provided to

/ extend at least partially across the slit, a first wire being closer to the

i2 first end than any of the other wires of the plurality of wires, and a

1 second wire being closer to the second end than any of the other wires

n of the plurality of wires, the apparatus comprising:

is a support for supporting the substrate and semiconductor chip; and

16 a pressing tool movably mounted relative to the substrate, the

17 pressing tool having a deflecting surface configured to press the wires

is into the slit when the pressing tool is moved toward the substrate, the

19 deflecting surface being substantially planar and having a sufficient length

20 to extend from the first wire to the second wire. 1

2

3

17. The apparatus of claim 16 wherein the pressing tool is

further configured to press the wires against a surface of the

semiconductor chip when the tool is moved toward the substrate.

^■18. The apparatus of claim 16 wherein a first gap is between

the first wire and the first end of the slit, wherein a second gap is

between the second wire the second end of the slit, and wherein the

deflecting surface is sufficiently long to extend into at least one of the

first and second gaps.

19. The apparatus of claim 18 wherein the deflecting surface is

sufficiently long to extend into both of the first and second gaps.

20. The apparatus of claim 16 wherein the pressing tool has a

first surface configured to press ends of the wires against the substrate

as the deflecting surface presses other ends of the wires into the slit,

the first surface being joined to the deflecting surface by a sidewall.

21. The apparatus of claim 16 wherein the pressing tool has a

first surface configured to press ends of the wires against the substrate

as the deflecting surface presses other ends of the wires into the slit

wherein the semiconductor chip has a substantially planar surface facing

the substrate, the first surface being joined to the deflecting surface by

a sidewall, the sidewall extending non-perpendicularly relative to the

plane of the substantially planar surface of the semiconductor chip.

22. The apparatus of claim 16 wherein the pressing tool has a

first surface configured to press ends of the wires against the substrate

as the deflecting surface presses other ends of the wires into the slit,

the first surface being substantially planar, the first surface being joined

to the deflecting surface by a sidewall, the sidewall extending non-

perpendicularly relative to the plane of the planar first surface.

23. The apparatus of claim 16 wherein the pressing tool has a

first surface configured to press ends of the wires against the substrate

as the deflecting surface presses other ends of the wires into the slit,

the first surface being joined to the deflecting surface by a sidewall, the

sidewall extending non-perpendicularly relative to the plane of the planar

deflecting surface.