JPH06163730A - Electronic parts - Google Patents
Electronic partsInfo
- Publication number
- JPH06163730A JPH06163730A JP43A JP31174192A JPH06163730A JP H06163730 A JPH06163730 A JP H06163730A JP 43 A JP43 A JP 43A JP 31174192 A JP31174192 A JP 31174192A JP H06163730 A JPH06163730 A JP H06163730A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- bumps
- electronic component
- wire
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75743—Suction holding means
- H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数個のチップが搭載
されるマルチチップパッケージタイプの電子部品に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip package type electronic component on which a plurality of chips are mounted.
【０００２】[0002]
【従来の技術】電子部品として、複数個のチップを有す
るマルチチップパッケージタイプのものが知られてい
る。図６はワイヤボンダでワイヤリング中のこの種従来
の電子部品１を示している。図中、２は基板であり、複
数個のチップ３が搭載されており、またその下面にはバ
ンプ（突出電極）４が多数個突設されている。基板２は
その下面のバンプ４をヒートブロック５に着地させて載
置されている。ヒートブロック５は、ワイヤ８のボンデ
ィング性を向上させるために、基板２やチップ３を加熱
するものである。６はワイヤボンダのホーンであり、そ
の先端部にはキャピラリツール７が保持されている。2. Description of the Related Art As an electronic component, a multi-chip package type having a plurality of chips is known. FIG. 6 shows a conventional electronic component 1 of this kind during wiring with a wire bonder. In the figure, reference numeral 2 denotes a substrate on which a plurality of chips 3 are mounted, and a large number of bumps (protruding electrodes) 4 are provided on the lower surface of the substrate. The substrate 2 is mounted with the bumps 4 on the lower surface thereof landing on the heat block 5. The heat block 5 heats the substrate 2 and the chip 3 in order to improve the bondability of the wire 8. Reference numeral 6 is a horn of a wire bonder, and a capillary tool 7 is held at its tip.
【０００３】ヒートブロック５により基板２を加熱し、
ホーン６を上下方向に揺動させながら、キャピラリツー
ル７に挿通されたワイヤ８によりチップ３の上面の電極
と基板２の上面の回路パターンの電極を接続する。回路
パターンの電極とバンプ４はスルーホールなどにより接
続されている。ワイヤ８による接続が終了したならば、
チップ３やワイヤ８を保護するための合成樹脂９を塗布
することにより、電子部品１は完成する。このようなマ
ルチチップタイプの電子部品１は複数のチップ３がパッ
ケージされているので、高集積化が著しく向上するとい
う長所を有している。The substrate 2 is heated by the heat block 5,
While swinging the horn 6 in the vertical direction, the electrode on the upper surface of the chip 3 and the electrode of the circuit pattern on the upper surface of the substrate 2 are connected by the wire 8 inserted through the capillary tool 7. The electrodes of the circuit pattern and the bumps 4 are connected by through holes or the like. When the connection by wire 8 is completed,
The electronic component 1 is completed by applying the synthetic resin 9 for protecting the chip 3 and the wires 8. Since such a multi-chip type electronic component 1 has a plurality of chips 3 packaged, it has an advantage that the degree of high integration is significantly improved.
【０００４】[0004]
【発明が解決しようとする課題】ところが上記従来の電
子部品１のバンプ４は基板２の下面全面に広く分布して
突設されており、バンプ４をヒートブロック５に着地さ
せて基板２を加熱するため、ヒートブロック５の熱は基
板２に伝わりにくく、ワイヤ８をボンディングしにくい
という問題点があった。However, since the bumps 4 of the conventional electronic component 1 are widely distributed and projected on the entire lower surface of the substrate 2, the bumps 4 are landed on the heat block 5 to heat the substrate 2. Therefore, there is a problem that the heat of the heat block 5 is hard to be transferred to the substrate 2 and the wire 8 is hard to be bonded.
【０００５】また上述したワイヤボンディングを行うの
に先立って、基板２にバンプ４を形成するが、この場
合、バンプ形成面を上面にして基板２をテーブルなどに
載置し、その表面にスタッドバンプ法などによりバンプ
を形成する。しかしながらこのようにしてバンプを形成
する場合、後工程でチップ３が搭載される基板２の回路
パターンの形成面を前記テーブルに載置するため、回路
パターン面が汚れたり傷ついたりしやすいという問題点
があった。Prior to the above-mentioned wire bonding, the bumps 4 are formed on the substrate 2. In this case, the substrate 2 is placed on a table or the like with the bump forming surface being the upper surface, and the stud bumps are placed on the surface. The bump is formed by a method or the like. However, when the bumps are formed in this way, the circuit pattern forming surface of the substrate 2 on which the chip 3 is mounted is placed on the table in a later step, and thus the circuit pattern surface is easily soiled or damaged. was there.
【０００６】更には、上記のようにして完成した電子部
品１を、プリント基板のような主基板に搭載する場合、
バンプ４を主基板の電極にボンディングするために、電
子部品１に押圧治具などにより上方から荷重を付与する
ことにより、バンプ４をプリント基板の電極に強く押し
付けねばならないが、基板２の下面全面に突設されたす
べてのバンプ４に均等な押圧力を付与することはきわめ
て難しく、ボンディング不良になりやすいという問題点
があった。Furthermore, when the electronic component 1 completed as described above is mounted on a main board such as a printed board,
In order to bond the bumps 4 to the electrodes of the main board, the bumps 4 must be strongly pressed against the electrodes of the printed board by applying a load to the electronic component 1 from above with a pressing jig or the like. It is extremely difficult to apply a uniform pressing force to all the bumps 4 projecting from the above, and there is a problem that defective bonding is likely to occur.
【０００７】そこで本発明は上記従来の問題点を解消で
きるマルチチップパッケージタイプの電子部品を提供す
ることを目的とする。Therefore, an object of the present invention is to provide a multi-chip package type electronic component which can solve the above-mentioned conventional problems.
【０００８】[0008]
【課題を解決するための手段】このために本発明は、基
板と、この基板の上面の周縁部に立設された立壁と、こ
の基板の上面の立壁の内部に搭載された複数個のチップ
と、立壁の下方の基板の下面の周縁部に集中的に配列し
て突設されてチップの電極と接続されるバンプとから電
子部品を構成するものである。To this end, the present invention is directed to a substrate, an upright wall provided upright on the peripheral edge of the upper surface of the substrate, and a plurality of chips mounted inside the upright wall of the upper surface of the substrate. And the bumps that are arranged in a concentrated manner on the peripheral portion of the lower surface of the substrate below the standing wall to project from and be connected to the electrodes of the chip.
【０００９】[0009]
【作用】上記構成によれば、基板表面へのバンプの形
成、基板をヒートブロックなどの加熱手段で加熱しなが
らのワイヤボンディング、電子部品に荷重を付与しなが
らの電子部品の主基板への搭載を有利に行える。According to the above structure, bumps are formed on the surface of the substrate, wire bonding is performed while the substrate is heated by a heating means such as a heat block, and electronic components are mounted on the main substrate while applying a load to the electronic components. Can be advantageously performed.
【００１０】[0010]
【実施例】次に、図面を参照しながら本発明の実施例を
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１１】図１は電子部品の斜視図、図２は平面図で
ある。この電子部品１１は、基板２と、基板２の上面の
周縁部に立設された枠形の立壁１２と、基板２の上面の
立壁１２の内部に搭載された複数個（本実施例では４
個）のチップ３とを有している。またバンプ４は立壁１
２の下方の基板２の下面の周縁部に集中的に突設されて
いる。チップ３や、チップ３とバンプ４を接続するワイ
ヤ８を保護するために、立壁１２の内部には合成樹脂１
３が塗布されている。すなわちこの電子部品１１は、基
板２の上面周縁部に立壁１２を設け、この立壁１２の直
下に対応する基板２の下面周縁部にバンプ４を集中的に
突設し、基板２の下面中央部はバンプ４が突設されてい
ないフラットな面になっている点において、図６に示す
従来の電子部品１と構成が相違している。FIG. 1 is a perspective view of an electronic component, and FIG. 2 is a plan view. The electronic component 11 includes a substrate 2, a frame-shaped standing wall 12 provided upright on the peripheral portion of the upper surface of the substrate 2, and a plurality of electronic components 11 mounted inside the standing wall 12 on the upper surface of the substrate 2 (4 in this embodiment).
Chips 3). The bump 4 is the standing wall 1
It is provided in a concentrated manner on the lower edge of the substrate 2 below the peripheral edge of the substrate 2. In order to protect the chip 3 and the wires 8 connecting the chips 3 and the bumps 4, the synthetic resin 1 is provided inside the standing wall 12.
3 is applied. That is, in this electronic component 11, the standing wall 12 is provided on the peripheral portion of the upper surface of the substrate 2, and the bumps 4 are concentratedly projected on the peripheral portion of the lower surface of the substrate 2 which is directly under the standing wall 12, and the central portion of the lower surface of the substrate 2 is provided. Differs from the conventional electronic component 1 shown in FIG. 6 in that it has a flat surface on which the bumps 4 are not provided.
【００１２】図３はワイヤ８とバンプ４の接続構造を示
している。基板２の上面には回路パターン１４が銅箔な
どにより形成されており、この回路パターン１４の電極
１５にワイヤ８の下端部が接続されている。またワイヤ
８の上端部はチップ３の電極１０に接続されている。回
路パターン１４の他端部にはスルーホール１６が基板２
を貫通するように穿孔されている。このスルーホール１
６の内面はメッキ手段などにより導電路が形成されてい
る。基板２の下面には回路パターン１８が形成されてい
る。この回路パターン１８の一端部はスルーホール１７
に接続されており、また他端部には電極１９が形成され
ており、この電極１９にバンプ４が突設されている。FIG. 3 shows a connection structure of the wire 8 and the bump 4. A circuit pattern 14 is formed of copper foil or the like on the upper surface of the substrate 2, and the lower end of the wire 8 is connected to the electrode 15 of the circuit pattern 14. The upper end of the wire 8 is connected to the electrode 10 of the chip 3. A through hole 16 is provided at the other end of the circuit pattern 14 for the substrate 2.
It is perforated so as to penetrate. This through hole 1
A conductive path is formed on the inner surface of 6 by plating means or the like. A circuit pattern 18 is formed on the lower surface of the substrate 2. One end of this circuit pattern 18 has a through hole 17
And an electrode 19 is formed on the other end, and a bump 4 is projected on the electrode 19.
【００１３】次に図４（ａ）（ｂ）（ｃ）（ｄ）（ｅ）
を参照しながら、電子部品１１の製造方法を説明する。
まず図４（ａ）に示すように基板２の周縁部にボンド２
１を塗布し、立壁１２をこのボンド２１で基板２の上面
に接着する。Next, FIG. 4 (a) (b) (c) (d) (e)
A method of manufacturing the electronic component 11 will be described with reference to FIG.
First, as shown in FIG. 4A, a bond 2 is formed on the peripheral portion of the substrate 2.
1 is applied and the standing wall 12 is adhered to the upper surface of the substrate 2 with this bond 21.
【００１４】次に図４（ｂ）に示すように、基板２を表
裏反転させてテーブル２２上に載置し、バンプ４を形成
する。本実施例のバンプ形成方法はスタッドバンプ法と
して知られるものであって、以下のようにして行われ
る。まずワイヤボンダのホーン６の先端部に保持された
キャピラリツール７にワイヤ８を挿通し、キャピラリツ
ール７から導出するワイヤ８の下端部にトーチ２３を接
近させてこのトーチ２３に高電圧を印加することによ
り、電気的スパークを発生させてワイヤ８の下端部にボ
ール８ａを形成する。Next, as shown in FIG. 4B, the substrate 2 is turned upside down and placed on the table 22 to form the bumps 4. The bump forming method of this embodiment is known as a stud bump method and is performed as follows. First, the wire 8 is inserted into the capillary tool 7 held at the tip of the horn 6 of the wire bonder, the torch 23 is brought close to the lower end of the wire 8 drawn out from the capillary tool 7, and a high voltage is applied to the torch 23. As a result, an electric spark is generated to form a ball 8a at the lower end of the wire 8.
【００１５】次にトーチ２３を側方へ退去させたうえ
で、ホーン６を下方へ回転させてキャピラリツール７を
下降させることにより、ボール８ａを基板２の電極１９
に押し付けてボンディングし、次いでホーン６を上方へ
回転させてキャピラリツール７を上昇させ、ボール８ａ
とワイヤ８の境目を切断すれば、ボール８ａは基板２の
電極１９に転着されてバンプ４となる。この場合、図示
するように立壁１２がテーブル２２に接地し、後工程で
チップ３が搭載される基板２の回路パターン１４の形成
面２４はテーブル２２に接地しないので、回路パターン
１４の形成面２４が汚れたり傷ついたりするのを解消で
きる。なおバンプの形成方法としては、スクリーン印刷
とリフローを組み合わせた半田バンプ法も知られてい
る。Next, the torch 23 is laterally retracted, and then the horn 6 is rotated downward to lower the capillary tool 7 to move the ball 8a to the electrode 19 of the substrate 2.
To bond to the ball 8a by rotating the horn 6 upward to raise the capillary tool 7.
When the boundary between the wire 8 and the wire 8 is cut, the ball 8a is transferred to the electrode 19 of the substrate 2 and becomes the bump 4. In this case, as shown in the drawing, the standing wall 12 is grounded to the table 22, and the formation surface 24 of the circuit pattern 14 of the substrate 2 on which the chip 3 is mounted in a later step is not grounded to the table 22. Therefore, the formation surface 24 of the circuit pattern 14 is formed. It can eliminate the stains and scratches. A solder bump method that combines screen printing and reflow is also known as a bump forming method.
【００１６】次に図４（ｃ）に示すように、ボンディン
グ装置（図外）のコレット１０にチップ３を真空吸着
し、チップ３を基板２の上面の所定座標位置に搭載す
る。Next, as shown in FIG. 4C, the chip 3 is vacuum-sucked to the collet 10 of the bonding apparatus (not shown), and the chip 3 is mounted at a predetermined coordinate position on the upper surface of the substrate 2.
【００１７】次に図４（ｄ）に示すように、ワイヤ８に
よりチップ３の電極１０と基板２の電極１５を接続する
ワイヤリングを行う。このワイヤリングは、図６に示し
た従来方法と同様の方法によりワイヤボンダにより行わ
れるので、その詳細な説明は省略する。Next, as shown in FIG. 4D, wiring for connecting the electrode 10 of the chip 3 and the electrode 15 of the substrate 2 with the wire 8 is performed. Since this wiring is performed by a wire bonder in the same method as the conventional method shown in FIG. 6, detailed description thereof will be omitted.
【００１８】このワイヤリングは、基板２をヒータを内
蔵し加熱手段としてのヒートブロック５上に載置して行
われるが、図示するようにヒートブロック５の平面寸法
を基板２の平面寸法よりも小さくしておくことにより、
基板２の下面中央部のフラットな面をヒートブロック５
に接地させ、基板２の周縁部のバンプ４はヒートブロッ
ク５に接地しないようにする。このようにすれば、ヒー
トブロック５と基板２の間にはバンプ４は介在しないの
で、ヒートブロック５により基板２を直接加熱すること
ができ、したがって図６に示す従来手段よりも熱効率よ
く基板２やチップ３を加熱できる。This wiring is carried out by mounting the substrate 2 on a heat block 5 having a built-in heater as a heating means, and as shown in the drawing, the plane dimension of the heat block 5 is smaller than the plane dimension of the substrate 2. By keeping
The flat surface in the center of the bottom surface of the substrate 2 is covered with the heat block 5
The bumps 4 on the peripheral portion of the substrate 2 are not grounded to the heat block 5. In this way, since the bumps 4 are not interposed between the heat block 5 and the substrate 2, the substrate 2 can be directly heated by the heat block 5, and therefore the substrate 2 can be more efficiently heat-treated than the conventional means shown in FIG. The chips and chips 3 can be heated.
【００１９】ワイヤリングが終了したならば、図４
（ｅ）に示すようにディスペンサ２５などの塗布手段に
より、立壁１２の内部に合成樹脂１３を塗布し、チップ
３やワイヤ８を封止して保護する。以上の工程により電
子部品１１は完成する。When the wiring is completed, FIG.
As shown in (e), the synthetic resin 13 is applied to the inside of the standing wall 12 by the application means such as the dispenser 25, and the chip 3 and the wire 8 are sealed and protected. The electronic component 11 is completed through the above steps.
【００２０】図５は電子部品１１を主基板２６に搭載し
ている様子を示している。２７は押圧治具であって、立
壁１２の上面に押し付けることにより、バンプ４を主基
板２６にボンディングする。このように立壁１２を押圧
すれば、大きな押圧力を与えることができる。しかもバ
ンプ４は立壁１２の下方に集中的に配列されているの
で、バンプ４を基板２の下面全面に突設する従来の電子
部品１よりも、すべてのバンプ４を均等で且つ強い力で
主基板２６に押圧して確実にボンディングすることがで
きる。FIG. 5 shows a state in which the electronic component 11 is mounted on the main board 26. A pressing jig 27 presses the upper surface of the standing wall 12 to bond the bumps 4 to the main substrate 26. By pressing the standing wall 12 in this manner, a large pressing force can be applied. Moreover, since the bumps 4 are concentratedly arranged below the standing wall 12, all the bumps 4 are uniformly and strongly applied as compared with the conventional electronic component 1 in which the bumps 4 are projected on the entire lower surface of the substrate 2. It is possible to press the substrate 26 for reliable bonding.
【００２１】[0021]
【発明の効果】以上説明したように本発明によれば、基
板の下面にバンプを形成する際には立壁がテーブルに接
地し、基板の回路パターンの形成面はテーブルに接地し
ないので回路パターンの形成面が汚れたり傷ついたりす
ることはない。またワイヤリングを行う際には、バンプ
を介在させずに基板を加熱手段により直接加熱できるの
で熱効率が著しく向上し、更には電子部品を主基板に搭
載する際には、立壁に押圧力を加えることによりその下
方に集中的に配列されたバンプを均等でしかも強い力で
主基板に押し付けて確実にボンディングできる。As described above, according to the present invention, when the bumps are formed on the lower surface of the substrate, the standing wall is grounded to the table, and the circuit pattern forming surface of the substrate is not grounded to the table. The forming surface does not get dirty or scratched. In addition, when wiring is performed, the substrate can be directly heated by the heating means without interposing bumps, so that the thermal efficiency is remarkably improved. Furthermore, when electronic components are mounted on the main substrate, pressing force should be applied to the standing wall. As a result, the bumps concentratedly arranged therebelow can be pressed evenly and with a strong force against the main substrate for reliable bonding.
【図１】本発明の一実施例の電子部品の斜視図FIG. 1 is a perspective view of an electronic component according to an embodiment of the present invention.
【図２】本発明の一実施例の電子部品の平面図FIG. 2 is a plan view of an electronic component according to an embodiment of the present invention.
【図３】本発明の一実施例の電子部品のワイヤとバンプ
の接続構造を示す斜視図FIG. 3 is a perspective view showing a wire / bump connection structure of an electronic component according to an embodiment of the present invention.
【図４】（ａ）本発明の一実施例の電子部品の製造工程
図 （ｂ）本発明の一実施例の電子部品の製造工程図 （ｃ）本発明の一実施例の電子部品の製造工程図 （ｄ）本発明の一実施例の電子部品の製造工程図 （ｅ）本発明の一実施例の電子部品の製造工程図4A is a manufacturing process diagram of an electronic component according to an embodiment of the present invention. FIG. 4B is a manufacturing process diagram of an electronic component according to an embodiment of the present invention. FIG. 4C is a manufacturing process diagram of an electronic component according to an embodiment of the present invention. Process drawing (d) Manufacturing process drawing of electronic component of one embodiment of the present invention (e) Manufacturing process drawing of electronic component of one embodiment of the present invention
【図５】本発明の一実施例の電子部品の主基板への搭載
中の側面図FIG. 5 is a side view of the electronic component according to the embodiment of the present invention during mounting on a main substrate.
【図６】従来の電子部品の製造中の側面図FIG. 6 is a side view of the conventional electronic component during manufacturing.
２ 基板 ３ チップ ４ バンプ １０ チップの電極 １１ 電子部品 １２ 立壁 2 substrate 3 chip 4 bump 10 chip electrode 11 electronic component 12 standing wall
Claims (1)
れた立壁と、この基板の上面の前記立壁の内部に搭載さ
れた複数個のチップと、前記立壁の下方の前記基板の下
面の周縁部に集中的に配列して突設されて前記チップの
電極と電気的に接続されるバンプとを有することを特徴
とする電子部品。1. A substrate, an upright wall provided upright on a peripheral portion of an upper surface of the substrate, a plurality of chips mounted inside the upright wall of the upper surface of the substrate, and a substrate below the upright wall. An electronic component having bumps that are arranged in a concentrated manner on a peripheral portion of a lower surface so as to project and are electrically connected to the electrodes of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4311741A JP3003435B2 (en) | 1992-11-20 | 1992-11-20 | Electronic component manufacturing method and electronic component bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4311741A JP3003435B2 (en) | 1992-11-20 | 1992-11-20 | Electronic component manufacturing method and electronic component bonding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06163730A true JPH06163730A (en) | 1994-06-10 |
| JP3003435B2 JP3003435B2 (en) | 2000-01-31 |
Family
ID=18020921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4311741A Expired - Fee Related JP3003435B2 (en) | 1992-11-20 | 1992-11-20 | Electronic component manufacturing method and electronic component bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3003435B2 (en) |
-
1992
- 1992-11-20 JP JP4311741A patent/JP3003435B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3003435B2 (en) | 2000-01-31 |
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