WO2001001638A1

WO2001001638A1 - Method and arrangement for time and space switching data between incoming and outgoing bit streams, each belonging to a different clock domain

Info

Publication number: WO2001001638A1
Application number: PCT/SE2000/001372
Authority: WO
Inventors: Joachim Roos
Original assignee: Net Insight Ab
Priority date: 1999-06-28
Filing date: 2000-06-28
Publication date: 2001-01-04
Also published as: SE9902442D0; SE9902442L; AU6038800A

Abstract

An arrangement (200) and a method are disclosed having a capability of bridging between clock domains in a digital switch. The bridging is accomplished by means of a time slot mapping table (370) containing information typically regarding both time and space switching of the time slot data entries between incoming and outgoing bit streams. By incorporating instructions in the time slot mapping table (370) having the purpose of providing an indication of whether of not to actually transfer data to an output port (330), it is possible to obtain the effect of bridging between the different clock domains. In other words, a selection in made based on the information in the mapping table (370) to obtain a selected subset of time slot data entries to be transferred from an input frame buffer (300) to an output bit stream, the feature of selecting a subset and not the entire set of time slots from input bit streams having the effect of lowering the bit rate.

Description

METHOD AND ARRANGEMENT FOR ΗME AND SPACE SWITCHING DATA BETWEEN INCOMING AND OUTGOING BIT STREAMS, EACH BELONGING TO A DIFFERENT CLOCK DOMAIN

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method and an arrangement capable of switching data between bit streams having different bit rates and being divided into time 5 slots.

STATE OF THE ART

According to prior art, switching arrangements capable of switching data in a time division multiplexed context typically use a control unit that maps each incoming slot 0 number to the outgoing slot number. Such mapping may involve both a mapping in the time domain, i.e. control of the order in which time slot data are written into each bit stream, and a mapping in the space domain, i.e. controlling which time slot data goes to which bit 5 stream. For example, so-called time-space-time (TST) switches are described in "Data and Computer Communications", 4th ed., by Williams Stallings, Mac illan Publishing Company. International patent application WO9925099 and US-patents 4,005,272, 4,809,261 0 as well as 5,128,929 show state-of-the-art switches.

However, prior art switches all show limitation as to the possibilities of switching time slots in space and time. In particular, prior art switches show limitations as to switching data between bit streams having different bit 5 rates in different parts, or domains, within the switch.

SUMMARY OF THE INVENTION

An object of the invention is therefore to provide a switch which solves a problem of providing greater freedom as to the possibilities of switching time slots in space and time between bit streams of different bit rates in a digital switch.

According to one aspect of the invention, the object is achieved by a method for switching data between a first bit stream of a first bit rate and a second bit stream of a second bit rate. The second bit rate is lower than the first bit rate. The bit streams are divided into recurring frames and each of the recurring frames are divided into time slots. The method comprises the steps of receiving said first bit stream at the first bit rate, temporarily storing each frame of time slot data from said first bit stream as a set of time slot data, selectively reading, for each frame of said second bit stream, a selected set of time slot data from the presently temporarily stored set of time slot data, and transmitting said selected set of time slot data into said second bit stream at the second bit rate, said second bit rate relating to the first bit rate as the size of the selected set relates to the size of the temporarily stored set.

According to a second aspect of the invention, the object is achieved by an arrangement for switching data between a first bit stream of a first bit rate and a second bit stream of a second bit rate. The second bit rate is lower than the first bit rate. Each of the bit streams are divided into recurring frames and each of said recurring frames are divided into time slots. The arrangement comprises means for receiving said first bit stream at the first bit rate, means for temporarily storing each frame of time slot data from said first bit stream as a set of time slot data, means for selectively reading, for each frame of said second bit stream, a selected set of time slot data from the presently temporarily stored set of time slot data, and means for transmitting said selected set of time slot data into said second bit stream at the second bit rate, said second bit rate relating to the first bit rate as the size of the selected set relates to the size of the temporarily stored set.

The invention discloses means and a method in a switch to solve the problem relating to switching data in bit streams where the bit streams are of different bit rates. In fact one aspect of the invention is to provide a simple, and yet easy to implement, method performing the function of a bridge between different bit rates in a switch. According to an embodiment of the invention, the core of a switch may, if so required, operate at a clock rate different from clock rates of the input and/or output domains of the switch. For example, the core of the switch may operate at a bit rate of 2 Gbps, providing approximately 3900 64-bit time slots per 125μs frame, whereas an output port of the switch may operate at a bit rate of 1 Gbps, providing only approximately 1950 64-bit time slots per 125 μs frame.

The capability of acting as a bridge between clock domains is accomplished by means of a time slot mapping table containing information typically regarding both time and space switching of the time slot data entries between incoming and outgoing bit streams. By incorporating instructions in the time slot mapping table having the purpose of providing an indication of whether or not to actually transfer data to an output bit stream, it is possible to obtain an effect of bridging between the different clock domains. In other words, a selection is made based on the information in the mapping table to obtain a selected subset of time slot data entries to be transferred from the frame buffer to an output bit stream, the feature of selecting a subset and not the entire set of time slots from input bit streams having the effect of lowering the bit rate. The actual indicator of whether or not to use, or transfer, a particular time slot data entry may be of different character depending on the particular implementation of the invention. One example of a use- indicator is a specific usage flag associated with a particular time slot data entry where the flag comprises a simple binary digit, zero or one. Also a more direct skip instruction may be coded in the information carried by the time slot mapping table by replacing a time slot identifier representing a valid time slot number with an identifier representing an invalid time slot number.

It is to be noticed that an advantage is gained by having an essentially even distribution of slot mapping table entries that indicate that data is to be disregarded or skipped. Such a distribution of skip instructions results in an essentially constant rate of data arriving to the FIFO-buffer and thereby avoiding any risk of overflowing or emptying the FIFO-buffer. This is an advantage in that a shallow FIFO-buffer can be used.

A particular advantage of this solution is that a switch and a method in a switch according to this inventive solution provide a large amount of flexibility while still being simple.

SHORT DESCRIPTION OF THE DRAWINGS Figure 1 schematically shows a switching arrangement according to the present invention.

Figure 2 schematically shows a first embodiment of a slot mapping table of the kind shown in figure 1.

Figure 3 schematically shows a second embodiment of a slot mapping table of the kind shown in figure 1.

PREFERRED EMBODIMENTS A switching arrangement according to the present invention will now be described with reference to figure 1, wherein the switching arrangement 200 is arranged to switch time slot data between two input bit streams and two output bit streams. It is to be assumed that the bit streams contain time slots of data in recurring frames according to the art .

It is to be noted that the switching arrangement disclosed is preferably a part of a digital switch capable of switching digital data streams of any format, packaged as packet data according to, e.g., the IP- standard, or being in more or less simple synchronous bit streams in a circuit switched network. A switch comprising the switching arrangement and switching method subject of the present invention preferably also includes means (not shown) capable of interfacing streams of digital data in any format between the arrangement discussed here and any digital data network in which a switch comprising the present arrangement is implemented.

In figure 1, a first input bit stream is received at a first input port 210a of the switching arrangement 200 and a second input bit stream is received at a second input port 210b of the switching arrangement 200. Each frame of the first and second input bit stream is sequentially passed on and written into a frame buffer 300a and 300b respectively. Means (not shown) for providing frame and time slot synchronization with respect to frames that are written into the frame buffers 300a and 300b are also provided.

For each output bit stream, the switching arrangement 200 comprises an output multiplexor 310, an output port 330, an output slot counter 350, a slot mapping table 370, a delay unit 340 and a FIFO-buffer 395 capable of buffering data from the frame buffers in a first-in-first-out manner. The output port 330 derives a frame synchronization signal for the respective output bit stream. The frame synchronization signal is provided to synchronize the operation of the respective output slot counter 350, and is also provided to the respective buffer 395 via the respective delay unit 340. The output slot counter 350 sequentially addresses the entries of the slot mapping table 370, stepping through the slot mapping table once for each outgoing frame at a slot frequency essentially corresponding to the number of time slots within a frame of the input bit stream, i.e. the number of slots per frame stored in one of the frame buffers. Thus at each specific point in time, the output slot counter will point at a respective entry of the slot mapping table 370. The slot mapping table will in turn provide two signals based upon the readouts from this entry, one designating the input port from which time slot data for the current outgoing time slot is to be collected, which signal is sent to the respective multiplexor 310, and one designating which input time slot position, i.e. from which entry of the frame buffer, that the time slot data is to be collected from, which signal is sent to both frame buffers, as will be described more in detail below with reference to figures 2 and 3.

As the time slot position i, selected by the slot mapping table 370, is provided to each one of the two frame buffers in random access, this causes the readout of the i : th entry from each one of the two frame buffers 300a, 300b. These two readouts from the frame buffers are then sent to the output multiplexors 310 that are controlled by the respective slot mapping table 370. In the respective multiplexor, it is decided which one of said two readouts, i.e. from which input port, that is to be passed on to the FIFO-buffer, as designated by the input port selection signal from the slot mapping table 370. Thus, the slot mapping table 370 uses the respective multiplexor 310 to retrieve data from a specific selected time slot data entry of a selected one of the two frame buffers .

A configuration signal (not shown) from a node controller controlling the updating of the slot mapping table is provided thereto.

The function of the delay unit 395 is to delay, for each outgoing frame, the provision of the output frame synchronization signal to the FIFO-buffer 395 so that the readout from the FIFO-buffer 395 will start a short period of time after the point in time when the slot mapping table 370 starts causing readouts of data to the FIFO-buffers 395 from the frame buffers 300. This is provided in order to make sure that the FIFO-buffer 395 will not run empty during the readout of a frame of data therefrom.

A first embodiment of a slot mapping table of the kind shown in figure 1 will now be described with reference to figure 2. The slot mapping table (SMT) is a table in which the allocated channels are defined. As indicated in figure 1, there is one slot mapping table for each output bit stream. The slot mapping table shown in figure 2, which for example may be the slot mapping table 370 in figure 1, is one frame deep and comprises two logical memory areas or columns 410,420, each column comprising a number of fields corresponding to the number of time slots within a frame of the input bit streams, so that each entry of the slot mapping table, comprising one field from each column, uniquely identifies an input port and a time slot thereof. Each field of the first column 410 defines an input port (or input frame buffer) , and each field of the second column 420 defines a time slot thereof (or a frame buffer data entry thereof) . The slot mapping table thus defines the slot schedule of a sequence of time slot data transferred to the FIFO-buffer 395, and incorporates switching in both the time and space domains .

The slot mapping table is scanned in order once every outgoing frame, at a slot rate corresponding to the number of slots stored per frame in one of the frame buffers, to define the mapping into each output time slot thereof, and the output of the slot mapping table directly designates the associated time slot data that is to be retrieved from the frame buffers. Thus, only a simple counting mechanism, as will be discussed below, is required for the generation of sequential addresses to the slot mapping table, which translates those into random references used for data retrieval in the frame buffers .

Thus, using the exemplifying slot mapping table shown in figure 2, the first time slot of each frame to be outputted to the FIFO-buffer 395 will contain data from the first time slot from each frame of the input bit stream received at the first port A. At a next slot count, no time slot will be provided from any incoming bit stream to the FIFO-buffer, as an instruction to disregard (or skip) a time slot data entry is encountered. At a third slot count, time slot data will be fetched from the second time slot of each frame of the first input bit stream. At the fourth time slot count again no data will be transferred to the FIFO-buffer 395 due to the skip instruction encountered in the slot number field of the first column 410. Thus, it is to be noticed that by providing the slot mapping table with appropriate content fields of the first column 410, either a valid slot identifier or an identifier indicating an invalid slot or a skip instruction, an arbitrary rate of time slot transfer to the FIFO-buffer 395 is obtained. A second embodiment of a slot mapping table is shown in figure 3. Similar to the slot mapping table shown in figure 2, the table of figure 3 comprises two columns 510,520 containing fields with information defining an input port (or input frame buffer) , as well as a time slot thereof (or a frame buffer data entry thereof) . In addition to these two columns 510,520, a third column 530 contains fields of data in the form of binary flags. The flags, denoted as in-use flags, indicate whether or not the mapping instruction provided by the data entries designating the input port and the input slot number in the fields of the other two columns 510,520, should be actually read from the buffer. Consequently, if the in- use flag is set to zero (0), indicating that the corresponding entry is not to be used for mapping, no data at all will be read out from the frame buffers to the respective FIFO-buffer during the time slot count at which said entry is addressed.

With respect to the slot mapping tables illustrated in figures 2 and 3, it is also possible to provide an alternative method to prevent time slot data entries from being transmitted to the output bit stream via the FIFO- buffer 395. Instead of providing signals designating a skip instruction or an in-use flag which lead to a non- transfer of time slot data from the frame buffers to the FIFO-buffer 395, a so-called idle pattern generated by an idle pattern generator (not shown) on a signal provided by the slot mapping table, is transferred to the buffer instead. In such a case, filtering or masking of the pattern is preferably performed within circuitry of the FIFO-buffer 395, leading to a non-forwarding of such idle patterns to the output bit stream.

Claims

1. Method for switching data between a first bit stream of a first bit rate and a second bit stream of a second bit rate, each of said bit streams being divided into recurring frames and each of said recurring frames being divided into time slots, said second bit rate being lower than said first bit rate, said method comprising the steps of: receiving said first bit stream at the first bit rate; temporarily storing each frame of time slot data from said first bit stream as a set of time slot data; regularly selecting for reading, for each frame of said second bit stream, a selected set of time slot data from the presently temporarily stored set of time slot data; and transmitting said selected set of time slot data into said second bit stream at the second bit rate, said second bit rate relating to the first bit rate as the size of the selected set relates to the size of the temporarily stored set.

2. Method as claimed in claim 1, wherein said first and second bit streams are provided, respectively, from a first and a second set of bit streams.

3. Method as claimed in claim 1 or 2, wherein said storing comprises storing each frame of time slot data from said first bit stream in a plurality of time slot data entries of a frame buffer.

4. Method as claimed in any one of the preceding claims, wherein said selective reading comprises the steps of: providing slot mapping instructions associated with said stored time slot data; and reading, for the time slots of each frame of said second bit stream, time slot data from said stored time slot data, said reading being conditional on said slot mapping instructions.

5. Method as claimed in claim 4, wherein said condition decides whether or not reading is to be performed.

6. Method as claimed in claim 4 or 5, wherein said reading is being conditioned for each and every available slot mapping instruction.

7. Method as claimed in any one of claims 4-6, wherein said providing slot mapping instructions comprises providing usage flags associated with stored time slot data, said usage flags capable of being in one of at least a first state and a second state, said usage flags in their at least first and second state identifying time slot data to be transmitted and disregarded, respectively, in transmission in said second bit stream.

8. Method as claimed in any one of claims 4-6, wherein said providing slot mapping instructions comprises providing usage flags associated with stored time slot mapping instructions and wherein said usage flags in their first and second states identifies whether the slot mapping instructions shall be acted upon or disregarded, respectively.

9. Method as claimed in any one of claims 4-6, wherein said providing slot mapping instructions comprises providing identifications of validity of stored time slot data, said time slot data providing time slot data for transmission in said second bit stream; and providing invalidity information in stored time slot data, said invalidity information providing time slot data to be disregarded in transmission in said second bit stream.

10. Method as claimed in any one of the preceding claims, wherein said transmitting step comprises buffering said selected set of time slot data.

11. Method as claimed in claim 10, further comprising for each frame of said second bit stream, delaying commencement of the data retrieval from said buffering with respect to commencement of the selective reading of stored time slot data.

12. Method as claimed in claim 10 or 11, wherein said buffering is performed in a first-in-first-out manner.

13. Arrangement (200) for switching data between a first bit stream of a first bit rate and a second bit stream of a second bit rate, each of said bit streams being divided into recurring frames and each of said recurring frames being divided into time slots, said second bit rate being lower than said first bit rate, comprising: means (210) for receiving said first bit stream at the first bit rate; means (300) for temporarily storing each frame of time slot data from said first bit stream as a set of time slot data; means (370) for regularly selecting for reading, for each frame of said second bit stream, a selected set of time slot data from the presently temporarily stored set of time slot data; and means for transmitting said selected set of time slot data into said second bit stream at the second bit rate, said second bit rate relating to the first bit rate as the size of the selected set relates to the size of the temporarily stored set.

14. Arrangement as claimed in claim 13, wherein said first and second bit streams are provided, respectively, from a first and a second set of bit streams.

15. Arrangement as claimed in claim 13 or 14, wherein said storing means (300) comprises means for storing each frame of time slot data from said first bit stream in a plurality of time slot data entries of a frame buffer.

16. Arrangement as claimed in any one of claims 13-15, wherein said means (370) for selective reading comprises: means for providing slot mapping instructions associated with said stored time slot data; and means for reading, for the time slots of each frame of said second bit stream, time slot data from said stored time slot data, said reading being conditional on said slot mapping instructions.

17. Arrangement as claimed in claim 16, wherein said condition decides whether or not reading is to be performed.

18. Arrangement as claimed in claim 16 or 17, wherein said means for reading comprises means for being conditioned for each and every available slot mapping instruction.

19. Arrangement as claimed in any one of claims 16-18, wherein said means for providing slot mapping instructions comprises means for providing usage flags associated with stored time slot data, said usage flags capable of being in one of at least a first state and a second state, said usage flags in their at least first and second state identifying time slot data to be transmitted and disregarded, respectively, in transmission in said second bit stream.

20. Arrangement as claimed in any one of claims 16-18, wherein said means for providing slot mapping instructions comprises means for providing usage flags associated with stored time slot mapping instructions and wherein said usage flags in their first and second states identifies whether the slot mapping instructions shall be acted upon or disregarded, respectively.

21. Arrangement as claimed in any one of claims 16-18, wherein said means for providing slot mapping instructions comprises means for providing identifications of validity of stored time slot data, said time slot data providing time slot data for transmission in said second bit stream; and means for providing invalidity information in stored time slot data, said invalidity information providing time slot data to be disregarded in transmission in said second bit stream.

22. Arrangement as claimed in any one claims 13-21, wherein said means for transmitting comprises means (395) for buffering said read time slot data.

23. Arrangement as claimed in claim 22, further comprising means (340) capable of, for each frame of said second bit stream, delaying commencement of the data retrieval from said buffering with respect to commencement of the selective reading of stored time slot data .

24. Arrangement as claimed in claim 22 or 23, wherein said means (395) for buffering is a first-in-first-out buffer.

25. Method for switching slots of frames between ports of a switch in a communication network, comprising: providing a set of slot mapping instructions for mapping of data slots to an output port of said ports, the number of slot mapping instructions of said set of slot mapping instructions being larger than the actual number of slots to be mapped to said output port per frame , defining a subset of the slot mapping instructions of said set of slot mapping instructions to be identified as not providing instructions for data to be mapped to said output port, and switching, to said output port, data in accordance with only those slot mapping instructions of said set of slot mapping instructions that are not identified as not providing instructions for data to be mapped to said output port.

26. Method as claimed in claim 25, wherein said switching comprises the steps of: scanning in order, at a defined slot rate, said set of slot mapping instructions for said output port once for each frame of data to be switched to said output port, and switching, for each so scanned slot mapping instruction, data to said output port in accordance therewith, given that the subject slot mapping instruction is not identified as not providing instructions for data to be mapped to said output port, data thereby being mapped to said output port at a rate that is lower than said defined slot rate.

27. Method as claimed in claim 25 or 26, wherein said defining a subset of the slot mapping instructions of said set of slot mapping instructions as not providing instructions for data to be mapped to said output port comprising distributing said subset of slot mapping instructions evenly among said set of slot mapping instructions so as to facilitate for an even, spread-out output stream of data slots to said output port.

28. Arrangement for switching slots of frames between one or more input ports to one or more output ports of said arrangement, said arrangement operating at a defined frame rate, comprising: means for storing a set of slot mapping instructions for mapping of data slots to an output port of said ports, the number of slot mapping instructions of said set of slot mapping instructions being larger than the actual number of slots to be mapped to said output port per frame, means for defining a subset of the slot mapping instructions of said set of slot mapping instructions to be identified as not providing instructions for data to be mapped to said output port, and means for switching, to said output port, data in accordance with only those slot mapping instructions of said set of slot mapping instructions that are not identified as not providing instructions for data to be mapped to said output port.

29. Arrangement according to claim 28, said switching means comprising: means for scanning in order, at a defined slot rate, said set of slot mapping instructions for said output port once for each frame of data to be switched to said output port, and means for switching, for each so scanned slot mapping instruction, data to said output port in accordance therewith, given that the subject slot mapping instruction is not identified as not providing instructions for data to be mapped to said output port, data thereby being mapped to said output port at a rate that is lower than said defined slot rate.

30. Arrangement according to claim 28 or 29, said means for defining a subset of the slot mapping instructions of said set of slot mapping instructions as not providing instructions for data to be mapped to said output port being arranged to distribute said subset of slot mapping instructions evenly among said set of slot mapping instructions so as to facilitate for an even, spread-out output stream of data slots to said output port.