WO2000078108A1 - Mounting material, mounting circuit using it and printed wiring board using it - Google Patents

Mounting material, mounting circuit using it and printed wiring board using it Download PDF

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Publication number
WO2000078108A1
WO2000078108A1 PCT/JP2000/003937 JP0003937W WO0078108A1 WO 2000078108 A1 WO2000078108 A1 WO 2000078108A1 JP 0003937 W JP0003937 W JP 0003937W WO 0078108 A1 WO0078108 A1 WO 0078108A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
mounting material
solder
nickel
mounting
Prior art date
Application number
PCT/JP2000/003937
Other languages
French (fr)
Japanese (ja)
Inventor
Kinji Saijo
Kazuo Yoshida
Hiroaki Okamoto
Shinji Ohsawa
Original Assignee
Toyo Kohan Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Kohan Co., Ltd. filed Critical Toyo Kohan Co., Ltd.
Priority to AU52494/00A priority Critical patent/AU5249400A/en
Publication of WO2000078108A1 publication Critical patent/WO2000078108A1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3473Plating of solder
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0355Metal foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0361Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0361Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0384Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/281Applying non-metallic protective coatings by means of a preformed insulating foil

Definitions

  • the present invention relates to a mounting material for manufacturing a mounting circuit, such as a semiconductor package, on which solder bumps are arranged with high density and high accuracy, a mounting circuit formed using the same, and a printed wiring formed with the mounting material. Regarding the board.
  • solder layer is formed on a part of a wiring layer on a printed wiring board, and this solder layer has been used to mount electronic components such as a semiconductor package.
  • electronic components such as a semiconductor package.
  • electronic devices have become smaller and denser in recent years, there has been a demand for narrower pitch solder layers on printed wiring boards and higher positioning accuracy.
  • solder coating method (2) solder printing method (3) soldering method, but for (1) and (2) the solder layer size
  • solder layer size there were problems such as large variations in (3) and a large amount of time required for (3).
  • Means for solving the problem of the above method is disclosed in Japanese Patent Application Laid-Open No. 7-66545, and FIGS. 8 and 9 show the manufacturing steps. Prepare the solder foil-clad laminate as shown in Fig. X? Then, the solder foil is etched to form a pattern. Then, as shown in FIG. 9, it is melt-transferred onto the printed wiring board.
  • the above-described method for forming a solder layer still has the following problems to be solved.
  • a step of transferring the solder pattern once formed is required, and there has been a problem that the number of manufacturing steps is increased.
  • the present invention is intended to solve the above-described problems, and has a composition-size uniformity on a circuit, a good positional accuracy, a mounting circuit on which solder bumps are formed, a printed wiring board, and the like.
  • An object of the present invention is to provide a mounting material for forming a semiconductor device. Disclosure of the invention
  • the mounting material of the present invention is characterized in that a solder layer, a nickel layer, and a copper layer are sequentially laminated.
  • the mounting material according to the present invention is characterized in that a copper layer having a nickel layer and a solder layer are sequentially laminated on one surface with a two-layered nickel layer as an intermediate layer.
  • the mounting material of the present invention is characterized in that a resin film is laminated on the copper layer side of the mounting material.
  • the solder layer of the mounting material is selectively etched while leaving the copper layer to form a solder bump, and the remaining copper layer is subjected to pattern etching to form a circuit.
  • the printed wiring board of the present invention is characterized in that a mounting material is selectively etched to form a circuit with solder bumps on a resin film.
  • solder foil in a vacuum chamber, after processing pre-activate the bonding surface of the nickel plating foil or Stevenage gel plated copper-clad resin film, and the solder foil ⁇ the two Ggeru plated Laminate copper foil or copper clad resin film with Nigel
  • FIG. 1 is a schematic explanatory diagram of a mounting material according to an embodiment of the present invention.
  • FIG. 2 is a process explanatory view of a method for manufacturing a mounting circuit according to an embodiment of the present invention.
  • FIG. 3 is a process explanatory view of a method for manufacturing a mounting circuit according to an embodiment of the present invention.
  • FIG. 4 is a process explanatory view of a method for manufacturing a mounting circuit according to one embodiment of the present invention.
  • FIG. 5 is an explanatory process diagram of a method of manufacturing a mounting circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic explanatory diagram of a printed wiring board according to one embodiment of the present invention.
  • FIG. 7 is an explanatory diagram of a manufacturing method of mounting material according to the 0 light of the embodiment.
  • FIG. 8 is an explanatory diagram of a conventional method for manufacturing a printed wiring board.
  • FIG. 9 is an explanatory diagram of a conventional method for manufacturing a printed wiring board.
  • nickel plating nickel plating
  • copper foil copper layer 12 (preferably 100 to 100 m thick) forming the circuit. 1) (preferably 0.5 to 3 m) to produce a nickel-plated copper foil 13 (see FIG. 1).
  • the nickel-plated copper foil 13 is wound around a rewind reel 23 in a clad plate manufacturing apparatus as shown in FIG.
  • the solder foil 10 forming the solder bump is wound around the rewind reel 25.
  • the nickel-plated copper foil 13 and the solder foil 10 are simultaneously rewound from the rewind reels 23, 25, and a part of them is wound around the electrode rolls 27, 28 protruding into the etching chamber 26, and etched.
  • a sputter etching process is performed to activate it.
  • the activation processing as the applicant has disclosed in JP-1 one 2 2 4 1 8 4 JP above, extremely low pressure of 1 1 X 1 0 ' ⁇ 1 X 1 0- 2 P a
  • (2) Nickel-plated copper foil 13 with a bonding surface and solder foil 10 are each grounded to one electrode A, and between electrodes A and B are insulated and supported. Applying an alternating current of 1 MHz to cause a glow discharge, and 3 and the area of the electrode exposed in the plasma generated by the glow discharge is 1/3 or less of the area of the electrode B, and 4 This is performed by performing an etching process.
  • a clad material for forming a printed wiring board can be manufactured by using a nickel-plated copper-clad resin film 20 (see FIG. 6) instead of the nickel-plated copper foil. .
  • a clad plate having a multilayer structure can be manufactured by one press welding.
  • a mounting circuit is manufactured through the following steps described with reference to FIGS.
  • solder foil 10 and nickel plating 11 were performed. Then, the copper foil 12 is removed leaving the solder bumps 16.
  • a commercially available solder etchant on copper for example, Enstrip TL-142 Conc, manufactured by Meltecs Inc.
  • a photoresist film 17 is formed on the circuit-forming copper foil, subjected to iT, and then exposed and developed to form a circuit-forming pattern.
  • the copper foil 12 is etched using ferric chloride or sulfuric acid + hydrogen peroxide.
  • a circuit 18 is formed.
  • the mounting circuit 19 can be manufactured.
  • the resin film 20 can be obtained as shown in FIG.
  • a printed wiring board 200 having a circuit on which solder bumps 16 are formed can be manufactured.
  • the printed wiring board 200 can also be formed by forming the mounting circuit 19 shown in FIG. 5 and then laminating the resin film 20.
  • the solder layer, nickel layer, and copper layer are pressed at a low reduction rate of 0.1 to 3%, the flatness of the joint interface can be maintained by suppressing the stress at the joint interface, and the workability is recovered. No heat treatment is required for this purpose, and no intermetallics are formed at the interface, so that a mounting circuit having excellent selective etching properties can be manufactured using this mounting material.
  • the mounting material described above is selectively used. Since the circuit with the bump is formed on the resin film by the touching, it can be used as it is as a printed wiring board.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

A mounting circuit and a printed wiring board, in each of which a composition/size on a circuit is uniform, a position accuracy is good and a solder bump is formed, and a mounting material for forming them, are provided. The mounting material is characterized in that a solder layer (10), a nickel layer (11) and a copper layer (12) are laminated in this order. Further, the mounting material is characterized in that, in its one face, the copper layer (12) having the nickel layer (11) and the solder layer (10) are laminated in order, with the nickel layer (11) being an intermediate layer. Further, in the mounting material, a resin film (20) is laminated on a copper layer (12) side of the mounting material (14).

Description

明 細 書 実装用材料、 それを用いた実装用回路それを用いたプリント配線板  Description Mounting material, mounting circuit using it, printed wiring board using it
¾ 技術分野 ¾ Technical field
本発明は、 半導体パッケージ等の高密度、 高精度に半田バンプが配置された実 装用回路を製造するための実装用材料、 それを用いて形成する実装用回路、 それ が形成されたプリン卜配線板に関する。  The present invention relates to a mounting material for manufacturing a mounting circuit, such as a semiconductor package, on which solder bumps are arranged with high density and high accuracy, a mounting circuit formed using the same, and a printed wiring formed with the mounting material. Regarding the board.
10 背景技術 10 Background technology
従来、 プリント配線板上には、 配線層の一部に半田層を形成しており、 この半 田層により半導体パッケージ等の電子部品を実装してきた。 そして、 近年の電子 機器の小型化、 高密度化に伴い、 プリント配線板上の半田層の狭ピッチ化、 高位 置精度化が求められてきた。  Conventionally, a solder layer is formed on a part of a wiring layer on a printed wiring board, and this solder layer has been used to mount electronic components such as a semiconductor package. As electronic devices have become smaller and denser in recent years, there has been a demand for narrower pitch solder layers on printed wiring boards and higher positioning accuracy.
^ 半田層の形成方法としては (1 ) 半田コート法 (2 ) 半田印刷法 (3 ) 半田め つき法等が代表的な方法であつたが、 (1 ) 、 (2 ) については半田層サイズの ばらつきが大きい、 (3 ) については多大な時間を要する等の課題があった。 上記方法の課題を解決する手段が特開平 7— 6 6 5 4 5公報に開示されており、 図 8、 図 9にその製造工程を示す。 図 8に示すように、 半田箔張り積層板を準備 X? し、 半田箔をエッチングしてパターンを形成する。 そして、 図 9に示すようにプ リント配線板上に溶融転写する。 ^ The typical methods of forming the solder layer are (1) solder coating method (2) solder printing method (3) soldering method, but for (1) and (2) the solder layer size However, there were problems such as large variations in (3) and a large amount of time required for (3). Means for solving the problem of the above method is disclosed in Japanese Patent Application Laid-Open No. 7-66545, and FIGS. 8 and 9 show the manufacturing steps. Prepare the solder foil-clad laminate as shown in Fig. X? Then, the solder foil is etched to form a pattern. Then, as shown in FIG. 9, it is melt-transferred onto the printed wiring board.
しかし、 上記した半田層の形成方法では、 なお以下の解決すべき課題を有して いた。 即ち、 パターンエッチングにより半田パターンを形成した後、 一度形成し た半田パターンを転写する工程が必要であり、 製造工程が多くなるという課題が あった。 また、 プリント配線板上に転写する際には高精度に位置決めする必要が あり、 回路の微細化に伴い、 その位置精度に問題が生じる可能性を有していた。 本発明は、 上記のような課題を解決しょうとするものであり、 回路上に組成 - サイズが均一で、 位置精度も良く、 半田バンプが形成された実装用回路、 プリン ト配線板、 およびそれらを形成するための実装用材料を提供することを課題とす る。 発明の開示 However, the above-described method for forming a solder layer still has the following problems to be solved. In other words, after forming a solder pattern by pattern etching, a step of transferring the solder pattern once formed is required, and there has been a problem that the number of manufacturing steps is increased. In addition, when transferring onto a printed wiring board, it was necessary to position with high precision, and with the miniaturization of the circuit, there was a possibility that a problem might occur in the position precision. The present invention is intended to solve the above-described problems, and has a composition-size uniformity on a circuit, a good positional accuracy, a mounting circuit on which solder bumps are formed, a printed wiring board, and the like. An object of the present invention is to provide a mounting material for forming a semiconductor device. Disclosure of the invention
本発明の実装用材料は、 半田層と、 ニッケル層と、 銅層とが順次積層されてい ることを特徴とする。  The mounting material of the present invention is characterized in that a solder layer, a nickel layer, and a copper layer are sequentially laminated.
本発明の実装用材料は、 片面に、 ニッケル層を具備する銅層と半田層とが、 二 jp ッケル層を中間層として順次積層されたことを特徴とする。  The mounting material according to the present invention is characterized in that a copper layer having a nickel layer and a solder layer are sequentially laminated on one surface with a two-layered nickel layer as an intermediate layer.
本発明の実装用材料は、 実装用材料の銅層側に樹脂フィルムを積層したことを 特徴とする。  The mounting material of the present invention is characterized in that a resin film is laminated on the copper layer side of the mounting material.
本発明の実装用回路は、 実装用材料の半田層を、 銅層を残して選択エッチング して半田バンプを形成し、 残つた銅層にパターンエッチングを施して回路を形成 In the mounting circuit of the present invention, the solder layer of the mounting material is selectively etched while leaving the copper layer to form a solder bump, and the remaining copper layer is subjected to pattern etching to form a circuit.
)|f したことを特徴とする。 ) | f.
本発明のプリント配線板は、 実装用材料に選択エッチングを施し、 樹脂フィル ム上に半田バンプ付きの回路を形成したことを特徴とする。  The printed wiring board of the present invention is characterized in that a mounting material is selectively etched to form a circuit with solder bumps on a resin film.
本発明の実装用材料は、 真空槽内で半田箔と、 ニッケルめっき銅箔またはニッ ゲルめつき銅張り樹脂フィルムの接合面を予め活性化処理した後、 前記半田箔と } 前記二ッゲルめつき銅箔又は二ッゲルめつき銅張り樹脂フィルムを積層して 0 . Mounting material of the present invention, a solder foil in a vacuum chamber, after processing pre-activate the bonding surface of the nickel plating foil or Stevenage gel plated copper-clad resin film, and the solder foil} the two Ggeru plated Laminate copper foil or copper clad resin film with Nigel
1〜3 %の圧下率で冷間圧接することによって形成し、 その際、 前記活性化処理 を、 ① 1 X 1 0 '〜1 X 1 0— 2 P a の極低圧不活性ガス雰囲気中で、 ②接合面を 有する前記銅箔と前記ニッケルめっきをそれぞれアース接地した一方の電極 Aと し、 絶縁支持された他の電極 Bとの間に 1〜 5 0 MHzの交流を印加してグロ一 ^放電を行わせ、 ③かつ、 前記グロ一放電によって生じたプラズマ中に露出される 電極の面積が、 電極 Bの面積の 1ノ 3以下で、 ④スパッ夕エッチング処理するこ とによって行うようにしたことを特徴とする。 図面の簡単な説明 Formed by cold welding at 1-3% of reduction ratio, in which, the activation treatment, in ① 1 X 1 0 '~1 X 1 0- 2 P in extremely low pressure inert gas atmosphere of a (2) The copper foil having the joint surface and the nickel plating are each used as one electrode A grounded to ground, and an AC of 1 to 50 MHz is applied between the electrode A and the other electrode B which is insulated and supported, and the ^ Discharge, ③ and the area of the electrode exposed to the plasma generated by the glow discharge is 1 to 3 times or less of the area of the electrode B. And so on. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の一実施の形態に係る実装用材料の概略説明図である。 図 2は、f 本発明の一実施の形態に係る実装用回路の製造方法の工程説明図である。 図 3は、 本発明の一実施の形態に係る実装用回路の製造方法の工程説明図である。 図 4は、 本発明の一実施の形態に係る実装用回路の製造方法の工程説明図である。 図 5は、 本発明の一実施の形態に係る実装用回路の製造方法の工程説明図である。 図 6は、 本発明の一実施の形態に係るプリント配線板の概略説明図である。 図 7は、 本発 ,0 明の一実施の形態に係る実装用材料の製造方法の説明図である。 図 8は、 従来の プリント配線板の製造方法の説明図である。 図 9は、 従来のプリント配線板の製 造方法の説明図である。 発明を実施するための最良の形態 FIG. 1 is a schematic explanatory diagram of a mounting material according to an embodiment of the present invention. FIG. 2 is a process explanatory view of a method for manufacturing a mounting circuit according to an embodiment of the present invention. FIG. 3 is a process explanatory view of a method for manufacturing a mounting circuit according to an embodiment of the present invention. FIG. 4 is a process explanatory view of a method for manufacturing a mounting circuit according to one embodiment of the present invention. FIG. 5 is an explanatory process diagram of a method of manufacturing a mounting circuit according to an embodiment of the present invention. FIG. 6 is a schematic explanatory diagram of a printed wiring board according to one embodiment of the present invention. 7, the onset is an explanatory view of a manufacturing method of mounting material according to the 0 light of the embodiment. FIG. 8 is an explanatory diagram of a conventional method for manufacturing a printed wiring board. FIG. 9 is an explanatory diagram of a conventional method for manufacturing a printed wiring board. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明における実装用回路の製造方法を添付図に従って、 説明する。 ま ず、 後のエッチングなどによって実装用回路を形成した際、 回路を形成する銅箔 (銅層) 1 2 (厚み 1 0〜 1 0 0 mが好適である)の片面にニッケルめっき (二 ッケル層) 1 1 ( 0 . 5〜3 mが好適である)を施し、 ニッケルめっき銅箔 1 3 を製造する (図 1参照)。  Hereinafter, a method for manufacturing a mounting circuit according to the present invention will be described with reference to the accompanying drawings. First, when a mounting circuit is formed by etching or the like, nickel plating (nickel plating) is applied to one side of a copper foil (copper layer) 12 (preferably 100 to 100 m thick) forming the circuit. 1) (preferably 0.5 to 3 m) to produce a nickel-plated copper foil 13 (see FIG. 1).
次に、 ニッケルめっき銅箔 1 3を、 図 7に示すようなクラッド板製造装置にお ける巻き戻しリール 2 3に巻き付ける。 また、 半田バンプを形成する半田箔 1 0 を巻き戻しリール 2 5に巻き付ける。  Next, the nickel-plated copper foil 13 is wound around a rewind reel 23 in a clad plate manufacturing apparatus as shown in FIG. The solder foil 10 forming the solder bump is wound around the rewind reel 25.
巻き戻しリール 2 3、 2 5からニッケルめっき銅箔 1 3と半田箔 1 0とを同時 に巻き戻し、 その一部をエッチングチャンバ 2 6内に突出した電極ロール 2 7、 2 8に巻き付け、 エッチングチャンバ 2 6内において、 スパッ夕エッチング処理 して活性化する。 この際、 活性化処理は、 本出願人が先に特開平 1一 2 2 4 1 8 4号公報で開示 したように、 ① 1 X 1 0 '〜 1 X 1 0— 2 P a の極低圧不活性ガス雰囲気中で、 ② 接合面を有するニッケルめっき銅箔 1 3と半田箔 1 0をそれぞれアース接地した 一方の電極 Aとし、 絶縁支持された他の電極 Bとの間に 1〜 5 0 MHzの交流を I 印加してグロ一放電を行わせ、 ③かつ、 前記グロ一放電によって生じたプラズマ 中に露出される電極の面積が、 電極 Bの面積の 1 / 3以下で、 ④スパッ夕エッチ ング処理することによって行う。 The nickel-plated copper foil 13 and the solder foil 10 are simultaneously rewound from the rewind reels 23, 25, and a part of them is wound around the electrode rolls 27, 28 protruding into the etching chamber 26, and etched. In the chamber 26, a sputter etching process is performed to activate it. In this case, the activation processing, as the applicant has disclosed in JP-1 one 2 2 4 1 8 4 JP above, extremely low pressure of ① 1 X 1 0 '~ 1 X 1 0- 2 P a In an inert gas atmosphere, (2) Nickel-plated copper foil 13 with a bonding surface and solder foil 10 are each grounded to one electrode A, and between electrodes A and B are insulated and supported. Applying an alternating current of 1 MHz to cause a glow discharge, and ③ and the area of the electrode exposed in the plasma generated by the glow discharge is 1/3 or less of the area of the electrode B, and ④ This is performed by performing an etching process.
その後、 真空槽 2 9内に設けた圧延ユニット 3 0によって冷間圧接し、 巻き取 りロール 3 2に卷き取り、 図 1に示すように、 半田バンプ付き実装用回路形成用 |C クラッド材 1 4を製造する。  Then, it is cold-welded by a rolling unit 30 provided in a vacuum chamber 29, wound up on a winding roll 32, and as shown in FIG. 1, for forming a mounting circuit with solder bumps. Manufacture 14
なお、 上記においては、 銅箔 (銅層) に予めニッケルめっき (ニッケル層) を したものを圧接する例を説明したが、 ニッケルめっきに代えて上記クラッド板製 造装置を用いて銅箔 (銅層) にニッケル箔 (ニッケル層) を圧接したものを用い ることもできる。  In the above description, an example in which a copper foil (copper layer) that has been previously plated with nickel (nickel layer) is pressure-welded has been described, but instead of nickel plating, the copper foil (copper layer) is formed using the above-described clad plate manufacturing apparatus. A layer in which a nickel foil (nickel layer) is pressed against the layer may be used.
i また、 上記においては、 ニッケルめつきした銅箔の代わりにニッケルめっきし た銅張り樹脂フィルム 2 0 (図 6参照)を用いることで、 プリント配線板形成用ク ラッド材を製造することもできる。  i In the above, a clad material for forming a printed wiring board can be manufactured by using a nickel-plated copper-clad resin film 20 (see FIG. 6) instead of the nickel-plated copper foil. .
さらに、 上記巻き戻しリールを 3台以上設けこれらのリールに銅箔、 銅箔張り 樹脂フィルムゃ二ッゲル箔材などを設置し、 3台以上のリ一ルから箔材の供給を 同時に受けることにより、 1回の圧接で多層構造のクラッド板を製造することも できる。  In addition, three or more of the above-mentioned rewind reels are installed, and copper foil, copper-foiled resin film, Nigger foil, etc. are installed on these reels, and foil materials are simultaneously supplied from three or more reels. In addition, a clad plate having a multilayer structure can be manufactured by one press welding.
上記実装用材料を所望の大きさに切断した後、 図 2〜図 9を参照して説明する 以下の工程を経て実装用回路を製造する。  After the above mounting material is cut into a desired size, a mounting circuit is manufactured through the following steps described with reference to FIGS.
まず、 図 2に示すように、 半田箔 (半田層) 1 0の表面にフォトレジスト膜 1 5 ^ を形成した後、 露光 ·現像し、 半田バンプ形成用のパターンを作製する。  First, as shown in FIG. 2, after forming a photoresist film 15 ^ on the surface of the solder foil (solder layer) 10, exposure and development are performed to produce a pattern for forming a solder bump.
図 3に示すように、 半田箔 1 0およびニッケルめっき 1 1の選択エッチングを 行い、 銅箔 1 2を、 半田バンプ 1 6を残して除去する。 この選択エッチングに用 いるエッチング液としては、 市販の銅上の半田エッチング液 (例えば、 メルテツ クス (株)社製、 エンストリップ T L - 1 4 2コンク) などが好適に用いられる。 次に、 図 4に示すように、 回路形成用銅箔上にフォトレジスト膜 1 7を形成し iT た後、 露光 '現像し、 回路形成用のパターンを作製する。 As shown in Fig. 3, the selective etching of solder foil 10 and nickel plating 11 was performed. Then, the copper foil 12 is removed leaving the solder bumps 16. As an etchant used for the selective etching, a commercially available solder etchant on copper (for example, Enstrip TL-142 Conc, manufactured by Meltecs Inc.) or the like is preferably used. Next, as shown in FIG. 4, a photoresist film 17 is formed on the circuit-forming copper foil, subjected to iT, and then exposed and developed to form a circuit-forming pattern.
図 5に示すように、 塩化第二鉄や硫酸 +過酸化水素等を用いて銅箔 1 2をエツ チング処理する。 これにより、 回路 1 8を形成する。 以上の工程により、 実装用 回路 1 9が作製できる。  As shown in FIG. 5, the copper foil 12 is etched using ferric chloride or sulfuric acid + hydrogen peroxide. Thus, a circuit 18 is formed. Through the above steps, the mounting circuit 19 can be manufactured.
また、 図 1に示した実装用材料として、 銅箔に樹脂シートがあらかじめ積層さ ,0 れている材料を用いて上記の製造工程を施せば、 図 6に示すように、 樹脂フィル ム 2 0上に半田バンプ 1 6が形成された回路を有するプリント配線板 2 0 0が作 製できる。  Also, if the above-described manufacturing process is performed using a material in which a resin sheet is preliminarily laminated on a copper foil as the mounting material shown in FIG. 1, the resin film 20 can be obtained as shown in FIG. A printed wiring board 200 having a circuit on which solder bumps 16 are formed can be manufactured.
なお、 プリント配線板 2 0 0は、 図 5に示した実装用回路 1 9を作成した後に、 樹脂フィルム 2 0を積層して形成することもできる。  The printed wiring board 200 can also be formed by forming the mounting circuit 19 shown in FIG. 5 and then laminating the resin film 20.
産業上の利用可能性 Industrial applicability
以上説明してきたように、 請求項 1〜 3及び 6記載の実装用材料においては、 半田層、 ニッケル層、 銅層のそれぞれの層の厚みが一定であるので、 半田バンプ の厚みサイズがそろい、 半導体パッケージを搭載しても傾いたり、 接続不良が出 0 たりしない。  As described above, in the mounting material according to claims 1 to 3 and 6, since the thickness of each of the solder layer, the nickel layer, and the copper layer is constant, the thickness of the solder bumps is uniform, Even if a semiconductor package is mounted, it does not tilt or no connection failure occurs.
また、 半田層、 ニッケル層、 銅層を 0 . 1〜3 %の低圧下率で圧接するため、 接合界面のストレスを低く抑えることによって接合界面の平坦度を保持でき、 か つ、 加工性回復のための熱処理も不要であり界面に合金属は生成しないので、 こ の実装用材料を用いて選択エッチング性に優れた実装用回路を製造することがで さる。  Also, since the solder layer, nickel layer, and copper layer are pressed at a low reduction rate of 0.1 to 3%, the flatness of the joint interface can be maintained by suppressing the stress at the joint interface, and the workability is recovered. No heat treatment is required for this purpose, and no intermetallics are formed at the interface, so that a mounting circuit having excellent selective etching properties can be manufactured using this mounting material.
請求項 5記載のプリント配線板においては、 上記した実装用材料を選択的にェ ツチングしてバンプ付きの回路を樹脂フィルム上に形成するようにしているので、 そのままプリント配線板として用いることができる。 In the printed wiring board according to claim 5, the mounting material described above is selectively used. Since the circuit with the bump is formed on the resin film by the touching, it can be used as it is as a printed wiring board.

Claims

請 求 の 範 囲 The scope of the claims
1. 半田層と、 ニッケル層と、 銅層とが順次積層された実装用材料。 1. A mounting material in which a solder layer, a nickel layer, and a copper layer are sequentially laminated.
2. 片面にニッケル層を具備する銅層と半田層とが、 ニッケル層を中間層とし ΙΓ て順次積層された実装用材料。  2. A mounting material in which a copper layer having a nickel layer on one side and a solder layer are sequentially laminated using the nickel layer as an intermediate layer.
3. 請求項 1又は 2の実装用材料の銅層側に樹脂フィルムを積層した実装用材 料。  3. A mounting material in which a resin film is laminated on the copper layer side of the mounting material according to claim 1 or 2.
4. 請求項 1〜 3のいずれかの実装用材料の半田層を、 銅層を残して選択エツ チングして半田バンプを形成し、 残った銅層にパターンエッチングを施して回路 4. Selective etching is performed on the solder layer of the mounting material according to any one of claims 1 to 3 while leaving the copper layer to form a solder bump, and the remaining copper layer is subjected to pattern etching.
,C を形成した実装用回路。 , C mounting circuit.
5. 請求項 3の実装用材料に選択エッチングを施し、 樹脂フィルム上に半田バ ンプ付きの回路を形成したプリント配線板。  5. A printed wiring board obtained by subjecting the mounting material of claim 3 to selective etching to form a circuit with a solder bump on a resin film.
6. 前記実装用材料は、 真空槽内で半田箔と、 ニッケルめっき銅箔またはニッ ケルめっき銅張り樹脂フィルムの接合面を予め活性化処理した後、 前記半田箔と 6. The mounting material is prepared by activating the bonding surface of a solder foil and a nickel-plated copper foil or a nickel-plated copper-clad resin film in a vacuum chamber in advance, and then
,)f 前記二ッゲルめつき銅箔又は二ッゲルめつき銅張り樹脂フィルムを積層して 0. ,) f The above-mentioned Nigel-coated copper foil or Nigel-coated copper-clad resin film is laminated.
1〜3 %の圧下率で冷間圧接することによって形成し、 その際、 前記活性化処理 を、 ① 1 X 1 0 '〜 1 X 1 0— 2 P a の極低圧不活性ガス雰囲気中で、 ②接合面を 有する前記銅箔と前記ニッケルめっきをそれぞれアース接地した一方の電極 Aと し、 絶縁支持された他の電極 Bとの間に 1〜50 MHzの交流を印加してグロ一Formed by cold welding at 1-3% of reduction ratio, in which, the activation process, ① 1 X 1 0 '~ 1 X 1 0- 2 in extremely low pressure inert gas atmosphere of P a (2) The copper foil having the joint surface and the nickel plating are each used as one electrode A grounded to ground, and an alternating current of 1 to 50 MHz is applied between the electrode A and the other electrode B which is insulated and supported.
^ 放電を行わせ、 ③かつ、 前記グロ一放電によって生じたプラズマ中に露出される 電極の面積が、 電極 Bの面積の 1Z 3以下で、 ④スパッタエッチング処理するこ とによって行うようにしたことを特徴とする請求項 1〜 3記載の実装用材料。 ^ Discharge is performed, and ③ and the area of the electrode exposed in the plasma generated by the glow discharge is 1Z3 or less of the area of the electrode B, and ④ sputter etching is performed. 4. The mounting material according to claim 1, wherein:
PCT/JP2000/003937 1999-06-16 2000-06-16 Mounting material, mounting circuit using it and printed wiring board using it WO2000078108A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1255295A1 (en) * 2000-01-12 2002-11-06 Toyo Kohan Co., Ltd. Semiconductor device, metal laminated plate for fabricating circuit on semiconductor, and method of fabricating circuit
CN113324202A (en) * 2021-06-07 2021-08-31 厦门天马微电子有限公司 Lamp strip, backlight unit and display device including lamp strip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01224184A (en) * 1988-03-02 1989-09-07 Toyo Kohan Co Ltd Method and device for manufacturing clad metal plate
JPH05167225A (en) * 1991-12-12 1993-07-02 Nitto Denko Corp Formation of electrode forming transfer sheet and external electrode of electronic part

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01224184A (en) * 1988-03-02 1989-09-07 Toyo Kohan Co Ltd Method and device for manufacturing clad metal plate
JPH05167225A (en) * 1991-12-12 1993-07-02 Nitto Denko Corp Formation of electrode forming transfer sheet and external electrode of electronic part

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1255295A1 (en) * 2000-01-12 2002-11-06 Toyo Kohan Co., Ltd. Semiconductor device, metal laminated plate for fabricating circuit on semiconductor, and method of fabricating circuit
EP1255295A4 (en) * 2000-01-12 2005-03-02 Toyo Kohan Co Ltd Semiconductor device, metal laminated plate for fabricating circuit on semiconductor, and method of fabricating circuit
CN113324202A (en) * 2021-06-07 2021-08-31 厦门天马微电子有限公司 Lamp strip, backlight unit and display device including lamp strip
CN113324202B (en) * 2021-06-07 2022-05-17 厦门天马微电子有限公司 Lamp strip, backlight unit and display device including lamp strip

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