JPH08124958A - Conductor for hybrid integrated circuit substrate - Google Patents
Conductor for hybrid integrated circuit substrateInfo
- Publication number
- JPH08124958A JPH08124958A JP6083669A JP8366994A JPH08124958A JP H08124958 A JPH08124958 A JP H08124958A JP 6083669 A JP6083669 A JP 6083669A JP 8366994 A JP8366994 A JP 8366994A JP H08124958 A JPH08124958 A JP H08124958A
- Authority
- JP
- Japan
- Prior art keywords
- foil
- circuit
- thickness
- hybrid integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Weting (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、Ａｌワイヤーボンデン
グおよび高密度実装性に優れた混成集積回路基板用導体
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductor for a hybrid integrated circuit board which is excellent in Al wire bonding and high-density mounting.
【０００２】[0002]
【従来技術】従来、ワイヤーボンデングの機能を有する
基板を製造するには、Ｃｕ箔を用いて回路形成を行い、
その回路上に貴金属めっきもしくはＮｉ等の卑金属めっ
きを施すか、またはＣｕ箔上にＡｌ片等のワイヤーボン
デイングが可能な金属片を接合する必要があった。2. Description of the Related Art Conventionally, in order to manufacture a substrate having a function of wire bonding, a circuit is formed using Cu foil,
It has been necessary to apply noble metal plating or base metal plating such as Ni on the circuit, or to bond a wire bondable metal piece such as an Al piece on the Cu foil.
【０００３】しかしながら、貴金属めっきやＮｉめっき
は高価であるだけでなく、均一なめっき面を得ることが
難しく、ワイヤーボンデイング性能は不安定である。ま
た、金属片の接合では数が多いと、回路形成作業が煩雑
になるという問題があった。However, precious metal plating and Ni plating are not only expensive, it is difficult to obtain a uniform plated surface, and the wire bonding performance is unstable. In addition, if the number of metal pieces joined is large, there is a problem that the circuit forming work becomes complicated.
【０００４】一方、新しい方法として、特開昭５８−４
８４３２号にみられるように、ＡｌとＣｕとの複層箔を
張り合わせた基板を用い、エッチングによりＡｌの回路
を形成する方法が用いられてきている。このＡｌのボン
デイングパットの特徴は、 （１）工程の途中で、めっきの必要がないこと。 （２）めっきによるボンデイングパットのように、めっ
き表面の精度や厚みを管理する必要がないこと。 （３）エッチングにより、再現性良く、一度に多数のＡ
ｌ回路を形成できること。 （４）Ａｌ線による超音波ボンデイングでは、ＡｌとＡ
ｌとの結合となるため、ボンデイングの作業範囲が広
く、信頼性が高い。 等が挙げられる。On the other hand, as a new method, JP-A-58-4
As seen in No. 8432, there has been used a method of forming a circuit of Al by etching using a substrate obtained by laminating a multi-layer foil of Al and Cu. The characteristic of this Al bonding pad is that (1) there is no need for plating during the process. (2) It is not necessary to control the precision and thickness of the plating surface unlike the bonding pad by plating. (3) Due to etching, a large number of A
Being able to form an l-circuit. (4) In ultrasonic bonding with Al wire, Al and A
Since it is combined with l, the working range of bonding is wide and the reliability is high. Etc.
【０００５】[0005]
【発明が解決しようとする課題】ところが、前記回路形
成法にしたがってＡｌとＣｕとの複層箔で回路を形成し
た場合、Ｃｕ箔のエッチング時にＡｌ箔部もエッチング
液と接触することから、Ａｌ箔部に微小の欠陥部でも存
在すると、そこに局部腐食が発生し、Ａｌ箔をとおして
下層のＣｕ箔までエッチングされてしまう。その結果、
優れたＡｌワイヤーボンデイング性や平滑なＣｕ回路が
得られないという問題が生じる。このＡｌ箔部の欠陥を
Ａｌ箔の厚みで対応しようとすると、Ａｌ回路をアルカ
リエッチング液で形成する際に、サイドエッチングが激
しくなり高密度実装に適したＡｌ回路を形成することが
困難になる。However, when a circuit is formed by a multilayer foil of Al and Cu according to the above-mentioned circuit forming method, the Al foil portion also comes into contact with the etching solution when the Cu foil is etched. If minute defects are also present in the foil, local corrosion will occur there, and the lower Cu foil will be etched through the Al foil. as a result,
There arises a problem that excellent Al wire bondability and a smooth Cu circuit cannot be obtained. If the thickness of the Al foil is used to cope with the defects of the Al foil portion, side etching becomes severe when forming the Al circuit with an alkaline etching solution, and it becomes difficult to form the Al circuit suitable for high-density mounting. .
【０００６】将来的に、プリント配線基板はさらに、高
集積化、高密度実装が要求され、回路には、より小さな
導体幅、導体間隔が形成可能な導体箔が必要となる。そ
のため、Ａｌ箔はできる限り薄いものを用いてサイドエ
ッチングの発生を抑え、かつＣｕエッチング液の接触に
よるＡｌ箔部のエッチングも抑えられることが要求され
る。In the future, printed wiring boards will be required to have higher integration and higher density packaging, and circuits will require conductor foils capable of forming smaller conductor widths and conductor intervals. Therefore, it is required that the Al foil be as thin as possible to suppress the occurrence of side etching and also suppress the etching of the Al foil portion due to the contact with the Cu etching solution.
【０００７】本発明は、このような問題点を解決するた
め鋭意検討した結果、従来の回路形成方法でもＡｌワイ
ヤーボンデイング性に優れ、かつ高密度実装を可能とし
た混成集積回路基板用導体を提供するものである。As a result of extensive studies to solve the above problems, the present invention provides a conductor for a hybrid integrated circuit board, which is excellent in Al wire bondability even in the conventional circuit forming method and enables high-density mounting. To do.
【０００８】[0008]
【課題を解決するための手段】本発明によれば、金属基
板に絶縁物層、ＣｕとＡｌとの複層箔とからなる導体部
を順次積層して一体化してなる積層物の該箔を、エッチ
ングして配線回路を形成させ、露出したＡｌ回路やＣｕ
回路に半田を介してＣｕ回路と半導体や他部材とを積層
し、かつ半導体とＡｌ回路とをＡｌリード線を用いて固
着する混成集積回路において、ＣｕとＡｌとの複層箔が
Ａｌ／Ｃｕ／Ａｌの順に形成した導体部で、Ｃｕ箔の厚
みが９〜１０００μｍ，Ａｌ箔の厚みが０．５〜３０μ
ｍの範囲で、いずれか一方のＡｌ箔表面側にｐＨ８以上
のアルカリ性水溶液に対して容易に溶解する水可溶性樹
脂を乾燥膜厚で０．５〜１０μｍ形成したことを特徴と
するＡｌワイヤーボンデイング性に優れた混成集積回路
基板用導体が提供される。According to the present invention, there is provided a foil of a laminate obtained by sequentially laminating a conductor portion comprising an insulating layer and a multi-layer foil of Cu and Al on a metal substrate and integrating them. , Etching to form wiring circuit, exposed Al circuit and Cu
In a hybrid integrated circuit in which a Cu circuit and a semiconductor or other member are laminated on a circuit via solder, and the semiconductor and the Al circuit are fixed by using an Al lead wire, a multilayer foil of Cu and Al is Al / Cu. In the conductor portion formed in the order of / Al, the Cu foil has a thickness of 9 to 1000 μm, and the Al foil has a thickness of 0.5 to 30 μm.
In the range of m, the Al wire bondability is characterized in that a water-soluble resin that easily dissolves in an alkaline aqueous solution having a pH of 8 or more is formed in a dry film thickness of 0.5 to 10 μm on one of the Al foil surface sides. An excellent conductor for a hybrid integrated circuit board is provided.
【０００９】[0009]
【作用】以下、図面により本発明を詳細に説明する。図
１は本発明により、作製された混成集積回路基板におけ
る導体部の断面図を示す。Ｃｕ箔１の両面にＡｌ箔を有
した複層箔は導体部５であって、回路を形成する側のＡ
ｌ箔２の表面には、ｐＨ８以上のアルカリ性水溶液に対
して容易に溶解する水可溶性樹脂４を積層し、他方のＡ
ｌ箔３側を絶縁物層７上に積層して用いる。The present invention will be described in detail below with reference to the drawings. FIG. 1 shows a cross-sectional view of a conductor portion in a hybrid integrated circuit board manufactured according to the present invention. The multi-layered foil having the Al foils on both sides of the Cu foil 1 is the conductor portion 5 and is A on the side where the circuit is formed.
On the surface of the foil 1, a water-soluble resin 4 that is easily dissolved in an alkaline aqueous solution having a pH of 8 or more is laminated.
The 1 foil 3 side is used by being laminated on the insulator layer 7.
【００１０】図２は、図１記載の本発明の導体部５を用
いて、実際に回路形成用基板を作製したものの断面図で
ある。Ａｌ板をベース基板６に、絶縁物層７の樹脂を積
層し、その上に導体部５を積層する。このとき、回路形
成と反対側のＣｕ箔１の表面のＡｌ箔３は導体部５と絶
縁物層７との接合強度を向上させるためにあり、厚みは
０．５μｍ以上あれば十分である。そして、Ａｌ箔３表
面に陽極酸化処理によるＡｌ酸化層を付与すれば、さら
に効果がある。しかし、水可溶性樹脂４がＡｌ箔３表面
にあると、導体部５と絶縁物層７との接合強度が得られ
ないため、水可溶性樹脂４の形成は片面だけでよい。FIG. 2 is a cross-sectional view of a circuit-forming substrate actually manufactured by using the conductor portion 5 of the present invention shown in FIG. The resin of the insulating layer 7 is laminated on the Al plate on the base substrate 6, and the conductor portion 5 is laminated thereon. At this time, the Al foil 3 on the surface of the Cu foil 1 on the side opposite to the circuit formation is for improving the bonding strength between the conductor portion 5 and the insulating layer 7, and the thickness of 0.5 μm or more is sufficient. Further, if an Al oxide layer is applied to the surface of the Al foil 3 by anodizing treatment, the effect is further enhanced. However, if the water-soluble resin 4 is present on the surface of the Al foil 3, the bonding strength between the conductor portion 5 and the insulator layer 7 cannot be obtained, so that the water-soluble resin 4 may be formed on only one side.
【００１１】本発明に用いるＣｕ箔１とＡｌ箔２との複
層箔である導体部５の材質としては、Ａｌ、Ｃｕともに
高純度のものでも合金のものいずれでもよい。導体部５
の作製方法としては、ＡｌとＣｕの圧着クラッド法、Ｃ
ｕを被めっき体とした電気Ａｌめっき法、または蒸着Ａ
ｌめっき法等があり、どの方法で作成したものでもよ
い。As the material of the conductor portion 5 which is a multilayer foil of the Cu foil 1 and the Al foil 2 used in the present invention, both Al and Cu of high purity or alloys may be used. Conductor part 5
As a manufacturing method of C, a pressure bonding clad method of Al and Cu, C
Electric Al plating method using u as the object to be plated or vapor deposition A
There is a plating method, etc., and any method may be used.
【００１２】本発明の導体部５におけるＣｕ箔１の厚み
は、９〜１０００μｍが適用範囲であり、とくに大電流
用途には、３５〜１０００μｍが好ましく、制御用の小
電流用途には、９〜７０μｍの箔厚が好ましい。The thickness of the Cu foil 1 in the conductor portion 5 of the present invention is in the range of 9 to 1000 .mu.m, preferably 35 to 1000 .mu.m particularly for large current applications, and 9 to 1000 .mu.m for small current applications for control. A foil thickness of 70 μm is preferred.
【００１３】図３は、厚み３００μｍのＣｕ箔１の両面
に厚み５μｍのＡｌ箔を形成した導体部５を、ベース基
板６と絶縁物層７とに張り合わせた後、従来の回路形成
法に従って回路を形成したときのＡｌ箔２の表面に塗布
した水可溶性樹脂４の乾燥膜厚と、導体部のうちＡｌ箔
２のＣｕエッチング液に対する耐食性を調査したもので
ある。Ａｌ箔２表面の水可溶性樹脂４を乾燥膜厚として
０．５μｍ以上となるように塗布すると、Ｃｕエッチン
グ液に対するＡｌ箔２の耐食性が向上する。また、水可
溶性樹脂４の厚みが厚くなった場合には、Ａｌワイヤー
ボンデイング性の低下が考えられるが、このような回路
形成ではＡｌワイヤーボンデイングを施す前に、形成し
た回路上の洗浄を目的として、アルカリ脱脂またはバフ
研磨を施すため、塗布する樹脂厚による不都合もなく、
本来とくに上限は規定されない。しかしながら、経済的
効果を考えると水可溶性樹脂４の乾燥膜厚は０．５〜１
０μｍで十分である。FIG. 3 shows a circuit in which a conductor portion 5 having a thickness of 5 μm and an Al foil formed on both sides of a Cu foil 1 having a thickness of 300 μm is attached to a base substrate 6 and an insulating layer 7, and then a circuit is formed according to a conventional circuit forming method. The dry film thickness of the water-soluble resin 4 applied to the surface of the Al foil 2 when the film was formed and the corrosion resistance of the Al foil 2 in the conductor portion to the Cu etching solution were investigated. When the water-soluble resin 4 on the surface of the Al foil 2 is applied so as to have a dry film thickness of 0.5 μm or more, the corrosion resistance of the Al foil 2 against the Cu etching solution is improved. Further, when the water-soluble resin 4 becomes thicker, the Al wire bonding property may be deteriorated. However, in such circuit formation, the purpose is to clean the formed circuit before performing the Al wire bonding. Since alkali degreasing or buffing is applied, there is no inconvenience due to the thickness of the applied resin,
Originally, no upper limit is specified. However, considering the economic effect, the dry film thickness of the water-soluble resin 4 is 0.5 to 1
0 μm is sufficient.
【００１４】本発明に用いられる水可溶性樹脂として
は、酸性のＣｕエッチング液や雨水，水道水といった一
般生活水等の接触による溶解を避けることができ、かつ
アルカリ性のエッチング液でＡｌ回路を形成する際に、
速やかにＡｌとともに溶解することが要求されるため、
ｐＨが８以上のアルカリ水溶液だけに溶解する水可溶性
樹脂でなければならない。As the water-soluble resin used in the present invention, it is possible to avoid dissolution due to contact with acidic Cu etching solution, general domestic water such as rain water and tap water, and to form an Al circuit with an alkaline etching solution. When
Since it is required to dissolve with Al quickly,
It must be a water-soluble resin that can be dissolved only in an alkaline aqueous solution having a pH of 8 or higher.
【００１５】図４は、厚み３００μｍのＣｕ箔１両面
に、厚み０．１〜５０μｍの範囲でＡｌ箔を形成した導
体部５を、ベース基板６と絶縁物層７とに張り合わせた
後、従来の回路形成法に従って回路を形成したときのＡ
ｌ箔の厚みと、Ａｌ回路８の作製可能な最小回路パター
ン幅および最小回路パターン間隔の関係について、Ａｌ
箔２の表面に水可溶性樹脂４を乾燥膜厚として１μｍ形
成して調査した結果を示す。なお、最小回路パターン
幅，最小回路パターン間隔とは、プリント配線回路にお
ける高密度実装化の目安となるもので、従来のＡｌとＣ
ｕとの複層箔ではＡｌ回路８の作成可能な最小回路パタ
ーン幅ならびに最小回路パターン間隔は４００μｍより
も大きかった。また、ここでは最小回路パターン幅、最
小回路パターン間隔ともほぼ同等の値を示したことか
ら、最小回路パターン幅のみを示している。In FIG. 4, a conductor portion 5 in which an Al foil is formed in a thickness range of 0.1 to 50 μm on both surfaces of a Cu foil 1 having a thickness of 300 μm is bonded to a base substrate 6 and an insulating layer 7, and then the conventional structure is used. A when a circuit is formed according to the circuit forming method
Regarding the relationship between the thickness of the foil and the minimum circuit pattern width and the minimum circuit pattern interval that can be produced by the Al circuit 8,
The results of an investigation conducted by forming the water-soluble resin 4 as a dry film thickness of 1 μm on the surface of the foil 2 are shown. The minimum circuit pattern width and the minimum circuit pattern interval are used as a guideline for high-density mounting in a printed wiring circuit.
In the multi-layer foil with u, the minimum circuit pattern width and the minimum circuit pattern interval capable of forming the Al circuit 8 were larger than 400 μm. Further, here, since the minimum circuit pattern width and the minimum circuit pattern interval have almost the same values, only the minimum circuit pattern width is shown.
【００１６】図４からわかるように、Ａｌ箔２の厚みが
３０μｍを越えると、Ａｌ回路８の作製可能な最小回路
パターン幅を４００μｍ以下にすることができない。ま
た、水可溶性樹脂４を形成しても、Ａｌ箔２の厚みが
０．５μｍ未満であると、良好なＡｌワイヤーボンデイ
ング性を有するＡｌ回路８を得ることができない。した
がって、作製可能な最小回路パターン幅を４００μｍ以
下にして高密度実装化を実現するには、Ａｌ箔２の表面
にｐＨ８以上のアルカリ水溶液に溶解する水可溶性樹脂
を乾燥膜厚で０．５μｍ以上形成して、Ａｌ箔２の厚み
は０．５〜３０μｍにすることが好ましい。As can be seen from FIG. 4, if the thickness of the Al foil 2 exceeds 30 μm, the minimum circuit pattern width of the Al circuit 8 that can be manufactured cannot be 400 μm or less. Even if the water-soluble resin 4 is formed, if the thickness of the Al foil 2 is less than 0.5 μm, the Al circuit 8 having good Al wire bondability cannot be obtained. Therefore, in order to realize a high-density packaging with a minimum circuit pattern width of 400 μm or less, a water-soluble resin dissolved in an alkaline aqueous solution having a pH of 8 or more on the surface of the Al foil 2 has a dry film thickness of 0.5 μm or more. After being formed, the thickness of the Al foil 2 is preferably 0.5 to 30 μm.
【００１７】[0017]
【実施例１】以下、実施例により本発明を詳細に説明す
る。まず、厚み３００μｍの圧延Ｃｕ箔１の両面に電気
めっき法で厚み５μｍのＡｌめっきを施して、ＡｌとＣ
ｕとの複層箔を作製した。この複層箔の回路形成側に使
用するＡｌ箔２表面に、酸価が１００のアクリル系樹脂
（水可溶性樹脂４）を乾燥塗膜として１μｍとなるよう
に塗布、形成し、混成集積回路の導体部５を作製した。
ここで、酸価とは、有機樹脂中に含まれる遊離脂肪酸を
中和するのに要する水酸化カリウムのミリグラム数のこ
とである。EXAMPLE 1 The present invention will be described in detail below with reference to examples. First, both sides of the rolled Cu foil 1 having a thickness of 300 μm are plated with Al having a thickness of 5 μm by an electroplating method to form Al and C.
A multi-layer foil with u was produced. An acrylic resin (water-soluble resin 4) having an acid value of 100 was applied and formed as a dry coating film on the surface of the Al foil 2 used for the circuit forming side of this multilayer foil so as to have a thickness of 1 μm. The conductor part 5 was produced.
Here, the acid value is the number of milligrams of potassium hydroxide required to neutralize the free fatty acids contained in the organic resin.
【００１８】このようにして作製した、図１に示すよう
な本発明に係る混成集積回路の導体部５を、ベース基板
６の厚さ１．５ｍｍのＡｌ板に、厚み１００μｍのシリ
カ含有エポキシ樹脂層からなる絶縁物層７を介して積層
し、図２に示すような構成の回路形成用基板を作製し
た。The conductor portion 5 of the hybrid integrated circuit according to the present invention as shown in FIG. 1 produced in this manner is formed on an Al plate having a thickness of 1.5 mm of a base substrate 6 and a silica-containing epoxy resin having a thickness of 100 μm. The layers were laminated with the insulating layer 7 interposed therebetween to prepare a circuit-forming substrate having a structure as shown in FIG.
【００１９】この回路形成用基板を用いて図５に示すよ
うな混成集積回路基板を作製した。まず、導体部５の回
路形成側Ａｌ箔２上に形成した水可溶性樹脂４にスクリ
ーン印刷法でレジストを施し、ｐＨが１２の水酸化ナト
リウム水溶液で露出した樹脂４とＡｌ箔２をともに溶解
させ、Ｃｕ箔１を露出させた。レジスト剥離後、Ｃｕエ
ッチング液により、露出したＣｕ箔１を取り除き、Ａｌ
回路８を必要とする部分の水可溶性樹脂４上に再びレジ
ストを施して、水酸化ナトリウム水溶液で選択的に不必
要なＡｌ箔２，３を取り除き、Ａｌ回路８およびＣｕ回
路９を形成した。その後、レジストおよびＡｌ回路８上
の水可溶性樹脂４を除去し、Ｃｕ回路９上に半田１０を
介して半導体１１やチップ抵抗等を搭載し、半導体１１
とＡｌ回路８とを、Ａｌリード線１２により超音波振動
法で固着したものである。A hybrid integrated circuit board as shown in FIG. 5 was produced using this circuit-forming board. First, a resist is applied to the water-soluble resin 4 formed on the Al foil 2 on the circuit formation side of the conductor portion 5 by a screen printing method, and the exposed resin 4 and Al foil 2 are both dissolved with an aqueous sodium hydroxide solution having a pH of 12. , Cu foil 1 was exposed. After removing the resist, the exposed Cu foil 1 is removed with a Cu etching solution to remove Al.
A resist was applied again to the water-soluble resin 4 in the portion requiring the circuit 8, and the unnecessary Al foils 2 and 3 were selectively removed with an aqueous sodium hydroxide solution to form the Al circuit 8 and the Cu circuit 9. After that, the resist and the water-soluble resin 4 on the Al circuit 8 are removed, and the semiconductor 11, the chip resistor, etc. are mounted on the Cu circuit 9 via the solder 10.
And an Al circuit 8 are fixed to each other by an ultrasonic vibration method with an Al lead wire 12.
【００２０】[0020]
【実施例２】厚み５００μｍのＣｕ箔の両面に電気めっ
き法で、厚み５μｍのＡｌめっきを施した複層箔を圧延
して、厚み３００μｍのＣｕ箔１と厚み３μｍのＡｌ箔
２にしたもので、本発明の混成集積回路の導体部５を作
製した以外は、実施例１とまったく同様の方法で混成集
積回路基板を作製した。Example 2 A copper foil having a thickness of 500 μm and an aluminum foil having a thickness of 5 μm, which were subjected to electroplating on both sides, were rolled to obtain a Cu foil 1 having a thickness of 300 μm and an Al foil 2 having a thickness of 3 μm. Then, a hybrid integrated circuit substrate was produced by the same method as in Example 1 except that the conductor portion 5 of the hybrid integrated circuit of the present invention was produced.
【００２１】[0021]
【比較例１】混成集積回路の導体部５を形成する複層箔
のＡｌ箔２表面に、ｐＨ８以上のアルカリ水溶液に溶解
する水可溶性樹脂を形成しなかった以外は、実施例１と
まったく同様の方法で混成集積回路基板を作製した。こ
の混成集積回路基板は所望の部位にＡｌ回路がないた
め、Ａｌワイヤーボンデイング性が不良であった。Comparative Example 1 Exactly the same as Example 1 except that a water-soluble resin that dissolves in an alkaline aqueous solution having a pH of 8 or more was not formed on the surface of the Al foil 2 of the multilayer foil that forms the conductor portion 5 of the hybrid integrated circuit. A hybrid integrated circuit board was manufactured by the method described in 1. Since this hybrid integrated circuit substrate does not have an Al circuit at a desired portion, the Al wire bondability was poor.
【００２２】[0022]
【比較例２】混成集積回路の導体部５を形成する複層箔
のＡｌ箔２の厚みを５０μｍとした以外は、実施例１と
まったく同一の方法で混成集積回路基板を作製した。こ
の混成集積回路基板は、Ａｌ回路８の回路パターン幅が
３００μｍ必要な部位で、Ａｌワイヤーボンデイング性
が不良であった。[Comparative Example 2] A hybrid integrated circuit board was manufactured in exactly the same manner as in Example 1 except that the thickness of the Al foil 2 of the multilayer foil forming the conductor portion 5 of the hybrid integrated circuit was set to 50 µm. In this hybrid integrated circuit substrate, the Al wire bonding property was poor at the site where the circuit pattern width of the Al circuit 8 was required to be 300 μm.
【００２３】[0023]
【発明の効果】以上述べたとおり、本発明は、混成集積
回路の導体部５を形成するＣｕ箔１とＡｌ箔２との複層
箔のうち、Ａｌ箔２の厚みを制御し、かつＡｌ箔２の表
面にｐＨが８以上のアルカリ水溶液に溶解する水可溶性
樹脂４を形成することにより、Ａｌワイヤーボンデング
性に優れ、高密度実装に適した混成集積回路基板を作製
できる混成集積回路の導体を提供することが可能となっ
た。As described above, the present invention controls the thickness of the Al foil 2 among the multilayer foils of the Cu foil 1 and the Al foil 2 which form the conductor portion 5 of the hybrid integrated circuit, and By forming a water-soluble resin 4 that dissolves in an alkaline aqueous solution having a pH of 8 or more on the surface of the foil 2, a hybrid integrated circuit substrate that has excellent Al wire bondability and is suitable for high-density mounting can be manufactured. It has become possible to provide a conductor.
【図１】本発明の混成集積回路の導体部の断面図を示
す。FIG. 1 shows a cross-sectional view of a conductor portion of a hybrid integrated circuit of the present invention.
【図２】本発明の混成集積回路の導体部を用いた混成集
積回路基板の断面図を示す。FIG. 2 shows a cross-sectional view of a hybrid integrated circuit board using a conductor portion of the hybrid integrated circuit of the present invention.
【図３】厚み３００μｍのＣｕ箔１両面に厚み５μｍの
Ａｌ箔を形成した複層箔の導体部５を用いて、回路を形
成したときのＡｌ箔２の表面に塗布した水可溶性樹脂４
の塗膜厚とＡｌ回路８のＣｕエッチング液に対する耐食
性の関係を調査したものである。FIG. 3 is a water-soluble resin 4 applied to the surface of an Al foil 2 when a circuit is formed by using a conductor portion 5 of a multilayer foil in which a Cu foil 1 having a thickness of 300 μm and an Al foil having a thickness of 5 μm are formed on both surfaces.
The relationship between the thickness of the coating film and the corrosion resistance of the Al circuit 8 to the Cu etching solution was investigated.
【図４】厚み３００μｍのＣｕ箔１の両面に、Ａｌ箔を
形成した複層箔の導体部５を用いて、回路を形成したと
きのＡｌ箔の厚みと、Ａｌ回路８の作製可能な最小回路
パターン幅および最小回路パターン間隔の関係を、Ａｌ
箔２の表面に水可溶性樹脂４を１μｍ形成して調査した
ものである。FIG. 4 shows the thickness of an Al foil when a circuit is formed by using a conductor portion 5 of a multilayer foil in which an Al foil is formed on both surfaces of a Cu foil 1 having a thickness of 300 μm, and the minimum possible production of an Al circuit 8. The relationship between the circuit pattern width and the minimum circuit pattern interval is
The water-soluble resin 4 having a thickness of 1 μm was formed on the surface of the foil 2 and investigated.
【図５】本発明の導体部５を積層した回路基板で回路を
形成し、半導体を実装した混成集積回路基板の断面図で
ある。FIG. 5 is a cross-sectional view of a hybrid integrated circuit board in which a circuit is formed by stacking conductor portions 5 of the present invention and a semiconductor is mounted.
１ Ｃｕ箔 ２ Ａｌ箔（回路形成側） ３ Ａｌ箔（絶縁物層との張り合わせ側） ４ 水可溶性樹脂 ５ 導体部（ＡｌとＣｕとの複層箔） ６ ベース基板 ７ 絶縁物層 ８ Ａｌ回路 ９ Ｃｕ回路 １０ 半田 １１ 半導体 １２ Ａｌリード線（ワイヤー） 1 Cu Foil 2 Al Foil (Circuit Forming Side) 3 Al Foil (Laminating Side with Insulator Layer) 4 Water-Soluble Resin 5 Conductor Part (Multilayer Foil of Al and Cu) 6 Base Substrate 7 Insulator Layer 8 Al Circuit 9 Cu circuit 10 Solder 11 Semiconductor 12 Al lead wire (wire)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/38 Ｅ 7511−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical indication H05K 3/38 E 7511-4E
Claims (1)
箔とからなる導体部を順次積層して一体化してなる積層
物の該箔を、エッチングして配線回路を形成させ、露出
したＡｌ回路やＣｕ回路に半田を介してＣｕ回路と半導
体や他部材とを積層し、かつ半導体とＡｌ回路とをＡｌ
リード線を用いて固着する混成集積回路において、Ｃｕ
とＡｌとの複層箔がＡｌ／Ｃｕ／Ａｌの順に形成した導
体部で、Ｃｕ箔の厚みが９〜１０００μｍ，Ａｌ箔の厚
みが０．５〜３０μｍの範囲で、いずれか一方のＡｌ箔
表面側にｐＨ８以上のアルカリ性水溶液に対して容易に
溶解する水可溶性樹脂を乾燥膜厚で０．５〜１０μｍ形
成したことを特徴とするＡｌワイヤーボンデイング性に
優れた混成集積回路基板用導体。1. A foil of a laminate obtained by sequentially stacking and integrating a conductor portion composed of an insulating layer and a multilayer foil of Cu and Al on a metal substrate to form a wiring circuit, The Cu circuit and the semiconductor or other member are laminated on the exposed Al circuit or Cu circuit via solder, and the semiconductor and the Al circuit are formed by Al.
In a hybrid integrated circuit that is fixed using lead wires, Cu
A multilayer foil of Al and Cu is a conductor portion formed in the order of Al / Cu / Al, and the Cu foil has a thickness of 9 to 1000 μm and the Al foil has a thickness of 0.5 to 30 μm. A conductor for a hybrid integrated circuit board excellent in Al wire bondability, characterized in that a water-soluble resin that is easily dissolved in an alkaline aqueous solution having a pH of 8 or more is formed on the surface side to have a dry film thickness of 0.5 to 10 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6083669A JPH08124958A (en) | 1994-03-31 | 1994-03-31 | Conductor for hybrid integrated circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6083669A JPH08124958A (en) | 1994-03-31 | 1994-03-31 | Conductor for hybrid integrated circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08124958A true JPH08124958A (en) | 1996-05-17 |
Family
ID=13808887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6083669A Pending JPH08124958A (en) | 1994-03-31 | 1994-03-31 | Conductor for hybrid integrated circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08124958A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923910A (en) * | 2010-09-10 | 2010-12-22 | 中南大学 | High-temperature anticorrosive conducting composite material |
-
1994
- 1994-03-31 JP JP6083669A patent/JPH08124958A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923910A (en) * | 2010-09-10 | 2010-12-22 | 中南大学 | High-temperature anticorrosive conducting composite material |
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