WO2000077846A1 - Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie - Google Patents
Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie Download PDFInfo
- Publication number
- WO2000077846A1 WO2000077846A1 PCT/FR2000/001570 FR0001570W WO0077846A1 WO 2000077846 A1 WO2000077846 A1 WO 2000077846A1 FR 0001570 W FR0001570 W FR 0001570W WO 0077846 A1 WO0077846 A1 WO 0077846A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- silicon
- thin layer
- silicon oxide
- layer
- germanium
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Definitions
- the present invention relates generally to a method of manufacturing a silicon substrate comprising a thin layer of buried silicon oxide (SOI substrate) and in particular such a method which makes it possible to obtain an SOI substrate comprising an extremely thin buried silicon oxide layer with excellent uniformity.
- SOI substrate buried silicon oxide
- the known SOI substrate manufacturing techniques all have a certain number of drawbacks, in particular a low production yield, a still insufficient quality of the substrate and the obtaining of thin layers of Si and of thick buried silicon oxide. relatively large and of poor uniformity.
- a first SOI substrate manufacturing process known as "SIMOX technology" consists in forming the Si0 layer buried in a silicon substrate by a step of implantation of oxygen at high dose followed by annealing at a temperature above
- a second process known as the "BESOI technique” consists in forming a thin film of Si0 2 on a surface of a first silicon body, then joining this first body, by the thin film of Si0 2 , to a second silicon body and finally to remove by grinding and mechanical polishing part of one of the silicon bodies to form the thin layer of silicon above the layer of buried silicon oxide.
- the silicon oxide layer on the first silicon body is formed by successively oxidizing the surface of this first body, then attacking the oxide layer formed to obtain the desired thickness.
- This process only allows layers of silicon oxide buried and layers of silicon on the silicon oxide buried relatively thick due to poor control of the etching process. In addition, the thin layers obtained by this process have poor uniformity.
- SMART CUT "consists of forming a thin layer of silicon oxide by oxidation on a first silicon body and then implanting ions
- This process requires the implantation of a high dose of hydrogen atoms. Despite the use of smaller atoms for implantation, the surface of the thin layer of silicon obtained is also damaged. In addition, since the thickness of the thin layer of silicon is defined by the implantation energy of the hydrogen atoms, this thickness can hardly be less than about 50 nm.
- the present invention therefore aims to provide a method of manufacturing an SOI substrate, which overcomes the drawbacks of the methods of the prior art.
- the subject of the present invention is a process for manufacturing an SOI substrate which makes it possible to obtain very thin and very uniform layers of silicon oxide and layers of silicon on the buried oxide layer.
- the invention also aims to provide a method of manufacturing an SOI substrate which can be implemented in standard equipment.
- the method of manufacturing a silicon substrate comprising a thin layer of buried silicon oxide comprises: a) the production of a first element comprising a silicon body including a main surface is coated, in order, with a buffer layer of germanium or a germanium-silium alloy and a thin layer of silicon; b) the production of a second element, distinct from the first element, comprising a silicon body of which a main surface is coated with a thin layer of silicon oxide; c) bonding the first element to the second element so that the thin layer of silicon of the first element is in contact with the thin layer of silicon oxide of the second element; and d) the elimination of the germanium or germanium-silicon alloy buffer layer, to recover the silicon substrate comprising a thin layer of buried silicon oxide, on the one hand, and a reusable silicon substrate, on the other hand.
- the method of manufacturing a silicon substrate comprising a thin layer of buried silicon oxide comprises: a) the production of a first element comprising a silicon body having a main surface coated, in order, with a buffer layer of germanium or an alloy of germanium and silicon, of a thin layer of silicon and a thin layer of silicon oxide; b) producing a second element comprising a silicon body, a main surface of which is coated with a thin layer of silicon oxide; c) bonding the first element to the second element, so that the thin layer of silicon oxide of the first element is in contact with the thin layer of silicon oxide of the second element; and d) eliminating the buffer layer to recover the silicon substrate comprising a thin layer of buried silicon oxide, on the one hand, and a reusable silicon substrate, on the other hand.
- the method of manufacturing a silicon substrate comprising a thin layer of buried silicon oxide comprises: a) the production of a first element comprising a silicon body having a main surface coated, in order, with a buffer layer of germanium or an alloy of germanium and silicon, a thin layer of silicon and a thin layer of silicon oxide; b) making a second element consisting of a silicon body; c) bonding the first element to the second element so that the thin layer of silicon oxide of the first element is in contact with the silicon body of the second element; and d) eliminating the buffer layer to recover the silicon substrate comprising a thin layer of buried silicon oxide, on the one hand, and a reusable silicon substrate, on the other hand.
- the thin buffer layers of Ge and germanium and silicon alloys of the first element are preferably produced by epitaxial deposition, for example by well-known vapor deposition or molecular beam epitaxy methods, so that, in in particular, the thin layer of silicon can have a very thin thickness of a few nanometers while having a suitable uniformity, typically from 1 to 50 nm.
- the thin buried oxide layer is preferably produced by a known thermal oxidation process, so that a very high quality oxide layer can be obtained with a thickness which is practically arbitrary ranging from 2 nm to 400 nm.
- connection of the first and second elements can be carried out using the forces of Nan der Walls.
- the assembly may be subjected to annealing.
- the buffer layer of the first element may consist of pure germanium, a silicon-germanium alloy or a silicon-germanium alloy containing carbon. More particularly, it is possible to use alloys Si 1 _ ⁇ Ge ⁇ (0 ⁇ x ⁇ l) or alloys Si j. Ge ⁇ C (0 ⁇ x ⁇ 0.95 and 0 ⁇ y ⁇ 0.05).
- germanium and the Si [ _ ⁇ Ge ⁇ and Si, _ Ge ⁇ C alloys exhibit very high selectivity to chemical attack by solutions or to anisotropic attack by plasma.
- the proportion of germanium in the alloy is at least equal to 10% by weight, preferably equal to or greater than 30% weight.
- silicon-germanium alloy containing a small fraction of carbon makes it possible to reduce the high stresses between the layers of silicon and the buffer layer.
- alloys at higher germanium concentrations and therefore with better attack selectivity, while obtaining a relaxation of the stresses It is also possible to form a buffer layer of silicon-germanium alloy having a germanium concentration gradient (relaxed SiGe buffer layer). In this type of buffer layer, the germanium concentration increases from the silicon body of the first element.
- the concentration profile of the germanium may be non-uniform.
- the Ge concentration can be 0% then increase up to 50% (or 70% and even 100%) and then decrease up to 0%. This solution avoids deformations in the upper silicon layer and eliminates thickness limitations.
- a high molar fraction of Ge in the SiGe alloy (in particular in the middle of the layer) provides, on the one hand, a very high selectivity of the etching process and an absence of risk of relaxation of the Si film, on the other hand .
- Figures 2a to 2e - the main steps of a second embodiment of the method of the invention.
- the first embodiment of the process of the invention begins, as shown in Figure 1a, by the successive deposition by epitaxy (for example by chemical vapor deposition or by molecular beam epitaxy ) a layer 2a of germanium, a silicon-germanium alloy optionally including a low proportion of carbon, then a thin layer of silicon 3a.
- epitaxy for example by chemical vapor deposition or by molecular beam epitaxy
- a layer 2a of germanium for example by chemical vapor deposition or by molecular beam epitaxy
- a silicon-germanium alloy optionally including a low proportion of carbon
- the buffer 2a and silicon 3a layers have a thickness of 1 to 50 nm.
- a first element A is thus produced comprising a silicon body 1a having a main surface coated, in order, with a buffer layer of germanium or of an alloy of germanium and of silicon 2a and of a thin layer of silicon 3a .
- a thin silicon oxide layer 2b is formed on a silicon body 1b, distinct from the preceding silicon body, by a conventional thermal oxidation process, so as to obtain a second element B comprising a silicon body 1b of which a main surface is coated with a thin layer of silicon oxide 2b.
- the first element A and the second element B are brought together, as shown in FIG. 1 a, so that the thin layer 3a of silicon of the first element A is in contact with the layer of silicon oxide 2b of the second element B and the first and second elements A and B are linked to each other, in a known manner, using the Van forces der Walls.
- the selective removal of the buffer layer 2a is then carried out, for example by means of a well-known oxidative chemistry, such as a 40 ml HNO3 70% + 20 ml solution.
- the silicon body 1a is not lost and can be recycled for use, for example as a silicon body for the manufacture of elements A or B.
- FIGS. 2a to 2e show the main steps of a variant of the method described above.
- the method of this variant differs from the method described in connection with FIGS. 1a to 1c in that, by thermal oxidation, a thin layer of oxide has been grown on the thin layer of silicon 3a 0 of the first element A above. of silicon 4a so as to obtain a first element A comprising a silicon substrate la of which a main surface is coated, in order, with a buffer layer of germanium or silicon and germanium alloy 2a, a thin layer of silicon 3 a and finally a thin layer of silicon oxide 4a.
- the second element B shown in FIG. 2b, is identical to that of the previous method.
- the first element A and the second element B are then joined as above, so that the layer 4a of silicon oxide 30. of the first element A is in contact with the layer 2b of silicon of the second element B.
- 35 subject the assembly to a heat treatment.
- a heat treatment For example, we can heat the assembly to a temperature of 1000 ° C for a period of approximately 30 minutes (as in BESOI technology).
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/208,132 USRE41841E1 (en) | 1999-06-14 | 2000-06-08 | Method for making a silicon substrate comprising a buried thin silicon oxide film |
EP00940457A EP1186024B1 (fr) | 1999-06-14 | 2000-06-08 | Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie |
US10/018,680 US6607968B1 (en) | 1999-06-14 | 2000-06-08 | Method for making a silicon substrate comprising a buried thin silicon oxide film |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9907496A FR2794893B1 (fr) | 1999-06-14 | 1999-06-14 | Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie |
FR99/07496 | 1999-06-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000077846A1 true WO2000077846A1 (fr) | 2000-12-21 |
Family
ID=9546748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2000/001570 WO2000077846A1 (fr) | 1999-06-14 | 2000-06-08 | Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie |
Country Status (4)
Country | Link |
---|---|
US (2) | USRE41841E1 (fr) |
EP (1) | EP1186024B1 (fr) |
FR (1) | FR2794893B1 (fr) |
WO (1) | WO2000077846A1 (fr) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2849715A1 (fr) * | 2003-01-07 | 2004-07-09 | Soitec Silicon On Insulator | Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince |
FR2849714A1 (fr) * | 2003-01-07 | 2004-07-09 | Soitec Silicon On Insulator | Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince |
WO2004061944A1 (fr) * | 2003-01-07 | 2004-07-22 | S.O.I.Tec Silicon On Insulator Technologies | Recyclage d'une tranche comprenant une structure multicouches apres l'enlevement d'une couche mince |
WO2004061943A1 (fr) * | 2003-01-07 | 2004-07-22 | S.O.I.Tec Silicon On Insulator Technologies | Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouche apres separation d'une couche mince de celle-ci |
US8951809B2 (en) | 2008-04-07 | 2015-02-10 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of transfer by means of a ferroelectric substrate |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7060592B2 (en) * | 2004-09-15 | 2006-06-13 | United Microelectronics Corp. | Image sensor and fabricating method thereof |
US7361574B1 (en) * | 2006-11-17 | 2008-04-22 | Sharp Laboratories Of America, Inc | Single-crystal silicon-on-glass from film transfer |
CN101615590B (zh) * | 2009-07-31 | 2011-07-20 | 上海新傲科技股份有限公司 | 采用选择腐蚀工艺制备绝缘体上硅材料的方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0371862A2 (fr) * | 1988-11-29 | 1990-06-06 | The University Of North Carolina At Chapel Hill | Méthode pour fabriquer une structure de semi-conducteur non-silicium sur isolant |
WO1996015550A1 (fr) * | 1994-11-10 | 1996-05-23 | Lawrence Semiconductor Research Laboratory, Inc. | Compositions silicium-germanium-carbone et processus associes |
EP0779649A2 (fr) * | 1995-12-12 | 1997-06-18 | Canon Kabushiki Kaisha | Procédé et dispositif pour la fabrication d'un substrat SOI |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5218213A (en) | 1991-02-22 | 1993-06-08 | Harris Corporation | SOI wafer with sige |
JP2980497B2 (ja) * | 1993-11-15 | 1999-11-22 | 株式会社東芝 | 誘電体分離型バイポーラトランジスタの製造方法 |
JP3293736B2 (ja) * | 1996-02-28 | 2002-06-17 | キヤノン株式会社 | 半導体基板の作製方法および貼り合わせ基体 |
KR100304161B1 (ko) | 1996-12-18 | 2001-11-30 | 미다라이 후지오 | 반도체부재의제조방법 |
CA2233115C (fr) | 1997-03-27 | 2002-03-12 | Canon Kabushiki Kaisha | Substrat de semiconducteur et methode de fabrication |
-
1999
- 1999-06-14 FR FR9907496A patent/FR2794893B1/fr not_active Expired - Fee Related
-
2000
- 2000-06-08 US US11/208,132 patent/USRE41841E1/en not_active Expired - Lifetime
- 2000-06-08 EP EP00940457A patent/EP1186024B1/fr not_active Expired - Lifetime
- 2000-06-08 WO PCT/FR2000/001570 patent/WO2000077846A1/fr active IP Right Grant
- 2000-06-08 US US10/018,680 patent/US6607968B1/en not_active Ceased
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0371862A2 (fr) * | 1988-11-29 | 1990-06-06 | The University Of North Carolina At Chapel Hill | Méthode pour fabriquer une structure de semi-conducteur non-silicium sur isolant |
WO1996015550A1 (fr) * | 1994-11-10 | 1996-05-23 | Lawrence Semiconductor Research Laboratory, Inc. | Compositions silicium-germanium-carbone et processus associes |
EP0779649A2 (fr) * | 1995-12-12 | 1997-06-18 | Canon Kabushiki Kaisha | Procédé et dispositif pour la fabrication d'un substrat SOI |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2849715A1 (fr) * | 2003-01-07 | 2004-07-09 | Soitec Silicon On Insulator | Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince |
FR2849714A1 (fr) * | 2003-01-07 | 2004-07-09 | Soitec Silicon On Insulator | Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince |
WO2004061944A1 (fr) * | 2003-01-07 | 2004-07-22 | S.O.I.Tec Silicon On Insulator Technologies | Recyclage d'une tranche comprenant une structure multicouches apres l'enlevement d'une couche mince |
WO2004061943A1 (fr) * | 2003-01-07 | 2004-07-22 | S.O.I.Tec Silicon On Insulator Technologies | Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouche apres separation d'une couche mince de celle-ci |
US8951809B2 (en) | 2008-04-07 | 2015-02-10 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of transfer by means of a ferroelectric substrate |
Also Published As
Publication number | Publication date |
---|---|
EP1186024A1 (fr) | 2002-03-13 |
EP1186024B1 (fr) | 2006-11-15 |
US6607968B1 (en) | 2003-08-19 |
FR2794893A1 (fr) | 2000-12-15 |
FR2794893B1 (fr) | 2001-09-14 |
USRE41841E1 (en) | 2010-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1344246B1 (fr) | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede | |
EP1902463B1 (fr) | Procede de diminution de la rugosite d'une couche epaisse d'isolant | |
EP1697975B1 (fr) | Procede de scellement de deux plaques avec formation d un co ntact ohmique entre celles-ci | |
EP1115920B1 (fr) | Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin, et produits obtenus | |
WO1999052145A1 (fr) | Procede de traitement thermique de substrats semi-conducteurs | |
FR2845523A1 (fr) | Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee | |
EP1811561A1 (fr) | Procédé de fabrication d'un substrat composite | |
EP0780889B1 (fr) | Procédé de depôt sélectif d'un siliciure de métal réfractaire sur du silicium | |
EP1811560A1 (fr) | Procédé de fabrication d'un substrat composite à propriétés électriques améliorées | |
FR3033933A1 (fr) | Couche thermiquement stable de piegeage de charges pour une utilisation dans la fabrication de structures de semi-conducteur sur isolant | |
FR2881573A1 (fr) | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes | |
FR2938975A1 (fr) | Procede de realisation d'une heterostructure de type silicium sur saphir | |
FR2907966A1 (fr) | Procede de fabrication d'un substrat. | |
EP4128328B1 (fr) | Procede de fabrication d'une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic | |
FR2938119A1 (fr) | Procede de detachement de couches semi-conductrices a basse temperature | |
FR2926674A1 (fr) | Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable | |
EP1332517B1 (fr) | Procede de revelation de defauts cristallins et/ou de champs de contraintes a l'interface d'adhesion moleculaire de deux materiaux solides | |
FR2938118A1 (fr) | Procede de fabrication d'un empilement de couches minces semi-conductrices | |
FR2913528A1 (fr) | Procede de fabrication d'un substrat comportant une couche d'oxyde enterree pour la realisation de composants electroniques ou analogues. | |
EP1186024B1 (fr) | Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie | |
EP1936667B1 (fr) | Traitement double plasma pour l'obtention d'une structure disposant d'un oxyde enterré ultra-fin | |
FR2928031A1 (fr) | Procede de transfert d'une couche mince sur un substrat support. | |
WO2006100301A1 (fr) | Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur | |
EP3503174B1 (fr) | Procede de transfert d'une couche utile | |
FR2849714A1 (fr) | Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2000940457 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 2000940457 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11208132 Country of ref document: US Ref document number: 10018680 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: JP |
|
WWG | Wipo information: grant in national office |
Ref document number: 2000940457 Country of ref document: EP |