WO2000059115A1

WO2000059115A1 - Electric current divider

Info

Publication number: WO2000059115A1
Application number: PCT/JP2000/002000
Authority: WO
Inventors: Hiroyuki Kimura
Original assignee: Lucent Technologies Inc.
Priority date: 1999-03-30
Filing date: 2000-03-30
Publication date: 2000-10-05
Also published as: JP2001111402A

Abstract

An electric current divider having three or more arbitrary numbers of output terminals the outputs of which smoothly vary with the control voltages. The current divider is characterized by having a control circuit (A) which generates N outputs (3) where N is an integer of three or more from a pair of control inputs (VIP, VIN), and a differential amplifier (B) which divides a current input (5) into N current outputs (4). With this constitution, outputs S1-SN constituting the output group (3) are generated from the control inputs (VIP, VIN) to the control circuit (A). The outputs S1-SN then function as control signals for the differential amplifier (B), resulting in an advantage of smoothly and continuously varying the current outputs of the differential amplifier (B).

Description

Akitoda Current Divider Technical Field

The present invention relates to an electronic device, and more particularly, to a current distributor that generates a smooth output according to a control input. Background art

It is preferable that the current distributor has characteristics such that the output smoothly changes in accordance with the control voltage. As the voltage of the power supply decreases, the degree of freedom in designing the gain and operating range of the circuit constituting the current divider decreases. When the number of output terminals to which current is distributed in a circuit operating at a low voltage increases, the circuit configuration becomes exponentially complicated. Also, as the circuit size increases, it becomes difficult to adjust the circuit at the design stage. In addition, the configuration of a current distributor having output terminals other than the power of 2 is complicated. In this regard, see FIG. 3 of the literature (1991 IEEE International Solid-State Circuits Conference, ISSCC91 / Session 17 / Analog Techniques / paper 17.5, ISSCC digest of technical papers p. 281). FIG. 3 in this specification corresponds to FIG. 3 in the same document. Disclosure of the invention

An object of the present invention is to provide a current divider whose output changes smoothly according to a control voltage. Still another object of the present invention is to provide a current distributor having an arbitrary number of output terminals of three or more.

The current distributor of the present invention includes a control circuit A that generates N output groups that are integers of 3 or more from a pair of control inputs V _IP and V _IN , and a current input based on an output of the control circuit A. And a differential amplifier B that distributes this current to N output groups. With such a configuration, an output S! S 'constituting an output group of the control circuit A is generated by the pair of control inputs _VIP and _VIN . This output SSN is then differentially amplified. It functions as a control signal for the amplifier B and changes the current outputs of the differential amplifier B smoothly and continuously.

Further, the present invention includes a second differential amplifier C between the control circuit A and the differential amplifier B. With such a configuration, the adjustment range of the amplification degree is widened. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a current distributor showing a first embodiment of the present invention,

Figure 2

FIG. 4 is a circuit diagram of a current distributor showing a second embodiment of the present invention,

Fig. 3

It is a circuit diagram of the conventional current distributor.

Explanation of reference numerals

1 Positive control input, V _IP

2 Negative control input, V _1N

3 Output terminal group, control input terminal group S SN

4 Current output terminals, I _{01 to} I. _N

5 Current input terminal, I _TN

6 Current source group, ~

7 Common terminal, COM

8 resistor group, 1 ^ ~ 1 ^-

9 Transistor group, Mi to M _N

101 Positive control input, V _IP

102 Negative control input, V _IN

103 Output terminal group, control input terminal group S SN

104 Current output terminal group, ICH ION

105 Current input terminal, I _IN

106 current source group, I to

107 Common terminal, COM 108 resistor group, 1 ^ ~ 1 ^-

109 transistor group, M] to M _N

1 13 Output terminal group, control input terminal group P! PN

1 14 Common terminal, VS

1 15 resistor group, Ι 1 ^ ~ Ι Ι ^

1 1 6 Transistor group, Q! ~ Q _N

1 17 Current source, best mode for carrying out the _IS invention

Next, an embodiment of the present invention will be described with reference to FIGS. In FIG. 1 showing the first embodiment, the left side of the broken line represents the control circuit A, and the right side represents the differential amplifier B.

The control circuit A has a pair of control inputs _V1P and _VIN, and a voltage output group 3 including N (SSN) output terminals. Further, the control circuit A has a current source group 6 composed of _N (I to IN) current sources and a resistance group 8 composed of (N-1) (1 ^ to 1 ^-) resistors.

Control input _VIP is current source I! Is connected to the positive terminal, the control input V _IN is connected to the positive terminal of the current source I _N. Output terminals of the output terminal group 3 is connected to the positive terminal of the current source I, the output terminal S ₂ is connected to the positive terminal of the current source 1 _2. Generally, the output terminal S i is connected to the positive terminal of the current source I i. The negative terminal of the current source I ~I _N is connected to the common terminal 7 (COM). Each resistance! ^ ~! ^ Is arranged between the output lines constituting the output terminal group 3. Specifically, the output resistance between the terminals Si and S ₂ are connected, the resistance R ₂ is connected between the output terminals S ₂ and S _3. Generally, a resistor Ri is connected between the voltage output terminals S i and S _{i +1} .

Differential amplifier B has N number of input terminals S to S _N, which is also the output terminal of the N control circuit A (S SN), the transistor group 9 of N (Μ ΜΝ). Input terminal Si is the gate of the transistor M 1, the input terminal S ₂ is connected to the gate of the transistor M _2. Generally, the input terminal Si is connected to the gate of the transistor Mi. The sources of the transistors M! To _MN are connected to the common terminal 5 (I IN) to which current is input from outside. On the other hand, the drain of each transistor IVh MN It is connected to each of the current output terminals I ₀₁ to I _0N constituting the group 4.

In this embodiment, a MOS FET is used. However, bipolar transistors can also be used. In this case, the gate of the MOS FET corresponds to the base of the bipolar transistor, the source corresponds to the emitter, and the drain corresponds to the collector. By changing the polarity of the current, it is possible to change the transistor polarity from P-type to N-type for MOS FETs and from PNP-type to NPN-type for bipolar 'transistors. Therefore, a modification using a transistor having a different type and polarity from the above-described embodiment is also included in the technical scope of the present invention.

In the configuration as described above, the current input from the current input terminal 5 (I.N) is applied to each of the current output terminals I _{01 of the} current output terminal group 4 according to the signals of the input terminals Si to _SN functioning as the control inputs. ~ I ON current output is controlled. Next, the operation of the current distributor having the above configuration will be described in detail.

The voltage output terminal of the output terminal group 3 from the control circuit A is also a control input terminal group of the differential amplifier B. In the following description, output terminal group 3 is also referred to as control input terminal group 3. Accordingly, the voltage output S to S _N from the control circuit A is also controlled input S! ~ S _N of the differential amplifier B. In the following description, both are used interchangeably as appropriate from the context.

If the difference between the voltages V _IP and V _IN of the pair of control inputs (ie, V _IP — V _IN ) is 0, the middle of the N voltage input terminals S i to SN of the control input terminal group 3 The voltage of the control input terminal SN / 2 is the lowest, the voltage of the control input increases toward the outside, and the voltages of the two control input terminals Si and _SN at both ends are the same and higher than the other outputs. That is, in this case, the relationship between the control input 3 and the output voltage of _SN is expressed by the following equation.

Si> S ₂ >……> SN / 2 <SN / 2 + 1 <…… <SN (1)

O 1 ⁼ SN

The above explanation is for N even, but when N is odd, the center control input terminal

The same applies in that the voltage forces of S _{N +} _1/2 and S _N _-1/2 are the lowest and the voltage of the control input S _N becomes higher toward the outside.

When the control input voltage V _IP is sufficiently lower than V, the output Si has the lowest voltage and the output _SN has the highest voltage. The other output voltages are decreasing in order from _SN to Si. You. In this case, the relationship between the voltages from Si to SN of the control input group 3 is expressed by the following equation.

Si <S ₂ <…… <SN / 2 <SN / 2 + 1 ゝ SN (2

Conversely, the converse is true when the control input voltage V _IP is sufficiently higher than V _IN . That is, the relationship between the voltages of the control inputs S to SN of the control input group 3 is expressed by the following equation.

Si> S ₂ >……> SN / 2> SN / 2 + 1>-…> SN (3)

Generally speaking, the control input voltage v _IP is sufficiently lower than v _IN (ν _ΙΡ <ν!

Ν) In the first state, the relationship between the 電圧 voltage input terminals S! To _SN that constitute the voltage input terminal group 3 satisfies the expression (2), and the control input voltage V _IP rises and V _In the second state, which is equal to _IN (VIP = VIN), equation (1) is satisfied. Conversely, when the control input voltage _P is sufficiently higher than V _IN (V _IP > V _IN ), in the third state, And satisfies equation (3). The transition period from the first state to the second state and the transition period from the second state to the third state are respectively an intermediate relation between equations (2) and (1), and equations (1) and (1). The intermediate relationship between (3) is shown.

The differential amplifier B of the present invention is a differential circuit having a plurality of control input terminal groups 3 and the same number of current output terminal groups 4. When the number of control input terminals included in control input terminal group 3 is two, there is no difference in operation from a normal differential amplifier circuit. Next, a case where the number of control input terminals included in the control input terminal 3 is three or more will be described.

When the potentials of the control input terminals S i to SN of all the control input terminal groups 3 are equal, the inflow current from the current input terminal 5 (I IN) is applied to each current output terminal I ₀₁ included in the current output terminal group 4 ~ Equal to ION. The sum of the currents output from each of the current output terminals I ₀₁ to ION included in the current output terminal group 4 is equal to the injection current from the current input terminal 5 (I IN). That is, it is expressed by the following equation.

I 01+ I 02+ I 03 + …… + I ON = I IN (4)

If the potential difference between the control input terminals S! SN included in the control input terminal group 3 is large, the current from one current output terminal (eg, I.i) corresponding to the control input terminal with the lowest voltage (eg, Si) Most of the current from the input current from input terminal 5 (I IN) flows, and almost no current is output from other output terminals (eg, output terminals other than Ioi).

Specifically, two control input terminals of the control input terminals Si SN included in the control input terminal group 3 (eg, the potentials of Si and S are equal, and the remaining control input terminals are the other control input terminals). When the potential is sufficiently lower than the potential of the current input terminal, the current input terminal (for example, I _0i , Ioi) included in the current output terminal group 4 corresponding to this low-potential control input terminal (for example, S s) Most of the injected current from input terminal 5 (I, Ν) is distributed, and almost no current flows to the other current output terminals.

To explain the above in terms of the control input voltage (V _IP , VIN),

V! P is V! When the voltage is sufficiently lower than N, the control input S1 has the lowest voltage and the control input _SN has the highest voltage as described above. The voltages of the other outputs gradually decrease from _SN to. Then, the relationship between the output currents of the current output terminals I ₀₁ to I ON of the current output terminal group 4 corresponding to the respective control input terminals Si to _SN is expressed by the following equation.

I 01 I 02 / No Ιθ N / 2 No I 0 N / 2 + 1>> I ON (5)

Conversely, the converse is true when the control input voltage V _IP is sufficiently higher than V _IN . That is, the relationship between the output currents of the current output terminals I ₀₁ to I ON is expressed by the following equation.

Ιθ1 <I 02 <…… <I 0 N / 2 <I 0 N / 2 + 1 <…… <ION (6)

If the difference between the pair of control input voltages V _IP and V _IN (that is, V _IP — V _IN ) is 0, the relation between the output currents of the current output terminals I ₀₁ to ION can be inferred from the above description. Is expressed by the following equation.

Ιθ1 <Ιθ2 <…… I> I 0 N / 2 + 1> ……> Ι θΝ (7)

As described above, the output voltage from the control circuit A is also the control voltage of the differential amplifier B. Therefore, by changing the control inputs V _{! P} and V _IN to the control circuit A (as a result, the output voltage from the control input terminal S SN changes), the current output terminal group 4 of the differential amplifier B is changed. The current output from each current output terminal can be smoothly and continuously changed.

Next, FIG. 2 shows a second embodiment of the present invention. The current distributor of the present invention includes three blocks separated by broken lines, that is, a control circuit A, a differential amplifier C, and a differential amplifier B in order from the left. The configuration and operation of the control circuit A and the differential amplifier B shown here are the same as in the first embodiment described above. However, the second current distributor of the present invention includes the differential amplifier C between the control circuit A and the differential amplifier B. Since the differential amplifier C is an inverting circuit, the polarity of the control circuit A is opposite to that of FIG. That is, the control inputs V _IP and V _IN to the control circuit A are connected to the output terminals _PN and Pi, respectively. Have been.

Next, the configuration of the current distributor of FIG. 2 will be described in detail. The control circuit A has a V _IP and V _IN is a pair of control inputs 10 1, 102, N pieces voltage output terminals 1 13 and an output terminal of the (Ρι~Ρ _Ν). Further, the control circuit A has a current source group 106 composed of _N (I! To IN) current sources and a resistance group 108 composed of (Ν-1) (1 ^ to 1 ^-!) Resistors. .

The control input V _IP is connected to the negative terminal of the current source Ι _、, and the control input V _IN is connected to the negative terminal of the current source I. Voltage output terminal Pi of the voltage output terminal group 1 13 is connected to the negative pin of the current source I i, the voltage output terminal P ₂ is connected to the negative terminal of the current source 1 _2. Generally, the voltage output terminal Pi is connected to the negative terminal of the current source Ii. The positive terminals of the current sources Ii to IN are connected to a common terminal 107 (COM). Each resistance Ri ~ R _N —! Are arranged between the voltage output lines constituting the voltage output terminal group 113. Specifically, the resistance between the voltage output terminal and P ₂ are connected, resistor R ₂ force between the voltage output terminal P ₂ and P ₃ ^ is connected. Generally, a resistor Ri is connected between the voltage output terminals Pi and Pi _{+ 1} .

The differential amplifier B has N voltage input terminals SSN, which are also N (SSN) output terminal groups 103 of the differential amplifier C, and N (Μ! To ΜΝ) transistor groups 109. The control input terminal Si is the gate of the transistor Ml, the control input terminal S ₂ is connected to the gate of the tiger Njisu evening M _2. Generally, the control input terminal Si is connected to the gate of the transistor Mi. The sources of the transistors M! To MN are connected to a common terminal 105 (I IN) into which current is externally injected. On the other hand, each transistor MMN} drain is connected to each of the current output terminals I ₀₁ to ION of the current output terminal group 104.

The differential amplifier C has N (（) voltage input terminal groups. This is also the output terminal group of the control circuit A. Further, the differential amplifier C has N (Q QN) transistor groups 1 It has 16 and N (S! SN) voltage output terminal groups 103. These are also the input terminal groups for the differential amplifier B. The voltage control input terminal P is connected to the gate of the transistor, and the voltage control input terminal is used. P ₂ is connected to the gate of transistor Q _2. Generally, voltage control input terminal Pi is connected to the gate of transistor Qi. The source of the transistor G to Q _N are connected to the common terminal 117 (1 s) to external currents are inputted. On the other hand the drain of each transistor H～Q _N are respectively connected to the voltage output terminal Si～S _N of the voltage output terminal group 103. At the same time, the drains of the transistors Qi QN are connected to the common terminal 114 (VS) via the resistors RLi RLN constituting the resistor group 115, respectively.

As in the first embodiment, MOS FETs were used for the differential amplifiers B and C in the above embodiment. However, it is also possible to use a bipolar transistor. In this case, the gate of the MOSFET corresponds to the bipolar transistor base, the source corresponds to the emitter, and the drain corresponds to the collector. By changing the polarity of the current, it is possible to change the transistor polarity from P-type to N-type for MOS FETs and from PNP-type to NPN-type for bipolar transistors. Therefore, modifications using transistors of different types and polarities from the above-described embodiments are also included in the technical scope of the present invention.

Next, the operation of the second embodiment configured as described above is the same as the operation of the first embodiment, except that a power differential amplifier C is added. The amplification degree can be adjusted by adjusting the current and voltage of the common power supply terminal 114 and the current of the terminal 117.

It should be noted that reference numerals described in the claims are provided to facilitate understanding of the present invention, and should not be used to limit the present invention.

As described above, according to the present invention, the voltage V! P and V! By controlling N, it is possible to provide a current divider having an arbitrary number of outputs whose output current can be controlled continuously. Industrial applicability

As described above, the current divider according to the present invention is suitable for use in an electronic device, in particular, a current divider that generates a smooth output according to a control input.

Claims

Scope of word blue

1. A control circuit (A) that generates N outputs (3) that are integers of 3 or more from a pair of control inputs (V _{! P} , VIN);

A differential amplifier (B) that distributes an injection current (5) to N outputs (4) in accordance with the output of the control circuit (A);

A current distributor, comprising:

2. The control circuit (A) has N current sources (6), and is connected to each output line of one terminal of the current sources ^ the output (3).

The current distributor according to claim 1, wherein:

3. The current distributor according to claim 2, wherein the other terminal of each of the current sources (6) is connected to a common terminal (7).

4. The current distributor according to claim 2, wherein a resistor (8) is connected between each output line of the output group (3).

5. The differential amplifier (B) has N transistors (9), and one terminal of each transistor is connected to each output line of the output (3).

The current distributor according to claim 1, wherein:

6. The other terminal of each transistor (9) is commonly connected to the injection current (5)

The current distributor according to claim 5, wherein:

7. The current distributor according to claim 5, wherein an output of the control circuit (A) controls each of the transistors (9).

8. Each transistor (9) is a MOS FET

The current distributor according to claim 5, wherein:

9. A second differential amplifier (C) is further provided between the control circuit (A) and the differential amplifier (B).

The current distributor according to claim 1, wherein:

10. The second differential amplifier (C) receives N outputs (P) from the control circuit (A) and generates a control output (S) for controlling the differential amplifier (B). The current distributor according to claim 9, wherein:

11. The second differential amplifier (C) has N transistors (116), and one terminal of each transistor is connected to each output line of the output (113). Item 9. The current distributor according to Item 9.

12. One terminal of each of the transistors (116) is connected to a common terminal (114) via a resistor (115).

12. The current distributor according to claim 11, wherein:

13. The other terminal of each of the transistors (116) is commonly connected to a current source (117)

12. The current distributor according to claim 11, wherein:

14. The output of the control circuit (A) controls each of the transistors (116)

12. The current distributor according to claim 11, wherein:

15. Each of the transistors (116) is a MOS FET

12. The current distributor according to claim 11, wherein: