JPH07321660A - D/a converter circuit - Google Patents

Abstract

PURPOSE:To obtain a D/A converter circuit from which a conversion characteristic without distortion is obtained and in which the spread of the ratio of components in use is suppressed. CONSTITUTION:Switches S0-S3 are used to select to which of a 1st coefficient device 11 multiplying an input current by a multiple of K1 and providing the output of the result and a 2nd coefficient device 12 multiplying an input current by a multiple of K2 and providing the output of the result a current is given from current sources 8Io, 4Io, 2Io, Io. A switch control circuit 13 controls the switches S0-S3 by low-order 5-bits of digital data fed to an input terminal IN. A coefficient control circuit 14 controls the coefficients K1, K2 of the coefficient devices 11, 12 by high-order 3 bits of the digital data fed to the input terminal IN. A synthesized output of the 1st and 2nd coefficient devices 11, 12 is led from an output terminal Tout as analog converted current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA (digital / analog) conversion circuit, and more particularly, it is applied to an adjustment circuit for adjusting an analog circuit in a semiconductor integrated circuit with digital data.

[0002]

2. Description of the Related Art Recently, the number of analog integrated circuits that perform digital control has increased, and an analog / digital circuit having a bus control function by a digital circuit by incorporating an I ² L circuit or using a BiCMOS process has been developed. The number of mixed ICs is increasing. One of such purposes is to digitize the adjustment of the analog circuit to reduce the volume for the adjustment and to automate the adjustment by the control of the microcomputer. DA for this
A conversion circuit is essential.

A general circuit example will be described with reference to the 7-bit current output type DA conversion circuit shown in FIG. This is 64Io, 32Io, 16Io, 8Io, 4Io, 2 weighted by a power of 2 with 64Io as a reference current source.
Seven current sources, Io and Io, and seven switches S0 to switch whether or not to lead each current source to the output terminal.
Made of S6. These switches S0-S6 are
Switching is performed by 7-bit digital data b0 to b6. For each bit of digital data, the MSB (most significant bit) is assigned to the switch with the largest current of 64 Io,
The switches are sequentially assigned to switches having smaller currents toward the LSB (least significant bit). When the data is 1 in each bit, the current is controlled so as to be guided to the output terminal. By doing so, the output current Iout changes linearly from 0 to 127 Io according to the 7-bit data.

However, this circuit has a problem that the DA conversion characteristic is greatly distorted if the accuracy of the current source is low. For example, assume that the relative accuracy of the resistors is 3% and the accuracy of the current source is determined by the relative accuracy of the resistors. At this time, the most severe point is the center of adjustment when the resistance R0 corresponding to the MSB has a large error (data 0111111 to 100000).
It is the strain at the point where it changes to 0). As a worst case, if the value of the resistor R0 has an error of -3% and + 3%, the output current value before and after the center point of the adjustment is (1) ... -3%: 63 Io → 62. 1Io (2) ... + 3%: 63Io → 65.9Io. The DA conversion characteristic at this time is illustrated in FIG. 8, and in (1), there is a region in which the output characteristic has a reverse slope, which causes a large distortion. In the case of (2), the conversion characteristic largely fluctuates partially, resulting in a large distortion and the resolution of this part decreases.

Such distortion is not convenient when the DA conversion circuit is used as an adjustment circuit for an analog circuit.
In the case where there is a region where the adjustment characteristic is bent and the inclination is reversed as shown in (1) of FIG. 8, for example, the digital adjustment value is controlled by the microcomputer while observing the output of the analog circuit and the optimum value is automatically set. When used for the function, the inflection point formed at this position may be erroneously adjusted as the optimum point, or the adjustment loop may fall into a vibrating state, making normal adjustment impossible. In the case where a large discontinuity occurs in the adjustment characteristic as shown in (2) of FIG. 8, fine adjustment cannot be performed.

In the case of 7-bit DA conversion as shown in FIG. 8, the adjusted output current jumps by 3 data, and at this position, only 5 bits of adjustment accuracy can be obtained. In the case of the adjustment circuit, the resolution of the adjustment as the circuit performance is determined by such a worst value, so that the circuit performance is significantly impaired. Such (1) and (2) are in a contradictory relationship. For example, in order to avoid the occurrence of the state of (1), the resistance R0 of the 7th bit of the DA conversion circuit shown in FIG. When set to, the state of (1) disappears, but the discontinuity of (2) becomes worse.

Another problem with the conventional DA converter circuit is that the elements must have a large ratio. Resistors Ro to 64Ro used in the 7-bit circuit of FIG.
A maximum of 64 times the ratio is required between the transistors Q1 to
It is necessary to have a ratio of 64 times between Q7. Since all of these directly affect the accuracy of DA conversion, an accurate ratio is required, and a large element must be used to maintain conversion accuracy. Therefore, in order to achieve this element ratio, a large area is occupied on the semiconductor chip, which is economically problematic.

[0008]

In the conventional DA converter circuit, if the accuracy of the current source is poor, not only the DA conversion characteristics are greatly distorted, but also it is necessary to give a large ratio to the values of the elements to be used. However, this occupies a large area on the semiconductor chip, which is economically disadvantageous. The present invention provides a DA conversion circuit which can obtain a conversion characteristic without distortion and which can be configured to suppress the spread of the ratio of used elements.

[0009]

In order to solve the above-mentioned problems, the present invention provides a M-bit current source weighted by a power of 2 ratio and a first and a second output circuit which multiply an input current by a constant coefficient. A second coefficient unit, a switch group for switching which current source of the current sources is input to the first and second coefficient units, and means for controlling the switch group by lower M + 1 bits of input digital data Means for controlling the coefficient values of the first and second coefficient multipliers according to the upper N bits of the input digital data, and the first and second
And an output unit for taking out a combined output of the coefficient unit as an output current converted into an analog.

Further, M weighted by a ratio of powers of 2 is used.
A voltage source for bits, first and second coefficient units for multiplying an input voltage by a constant coefficient and outputting the voltage source, and which voltage source of the voltage source is input to the first and second coefficient units. A switch group for switching, and first and second adders for adding all the voltages obtained through the switch group to the first and second coefficient units to be input to the coefficient unit, A third summing outputs of the first and second coefficient multipliers
Adder, means for controlling the switch group by the lower M + 1 bits of the input digital data, means for controlling the coefficient value of the coefficient unit by the upper N bits of the input digital data, and the output of the third adder. And an output section for obtaining an output voltage converted into analog.

[0011]

With this circuit configuration, the lower bits are DA converted by weighting powers of 2,
Since the upper bits are decoded and subjected to addition control, there is no sudden change in the state in which all the switches are inverted, and the weight is not concentrated on specific elements to control the characteristics. In addition, as a control method of this circuit, when the lower data is saturated and the upper data is carried, the carry switch always switches the carry switch after the analog amount by the corresponding lower bit is set to zero. For this reason, the DA conversion characteristic is always horizontal for one data at the carry position to the upper bit, and in other portions, the linearity is determined only by the conversion characteristic for the lower bit.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an embodiment of the invention 7
It is a circuit block diagram for explaining a bit DA converter circuit as an example. In this embodiment, a current source for 4 bits of 8Io, 4Io, 2Io, and Io weighted by a ratio of powers of 2 and a first coefficient unit 1 for multiplying an input current by K1 and outputting it.
1 and the second coefficient unit 12 that multiplies the input current by K2 and outputs
And S0 for switching the input of the current sources 8Io, 4Io, 2Io, and Io to the coefficient units 11 and 12, respectively.
To S3, a switch control circuit 13 for controlling the switches S0 to S3 with the lower 5 bits of the digital data supplied to the input terminal IN, and a coefficient multiplier 11 with the upper 3 bits of the digital data supplied to the input terminal IN. , 12 and the coefficient value control circuit 14 for controlling the coefficient values K1 and K2, and the combined output of the coefficient units 11 and 12 is used as the output current converted into analog.

When the data of the fifth bit from the lower order is "1", the switch control circuit 13 performs bit inversion of the data of the lower four bits, and then switches the switches S0 to S3 of the current source by the lower four bits with a lighter weight. From the other side, the increment control is performed by incrementing one count in binary order. The coefficient value control circuit 14 is data of the upper 3 bits, and the coefficient value of the first and second coefficient units 11 and 12 is set to K 1 =
With 1 and K2 = 0, control is performed such that the value is alternately increased by 2 from K2.

Considering the operation of this circuit, first, when the upper 3 bits are all 0, the switches S0 to S3 are directly binary controlled by the lower 4 bits b0 to b3, and the first coefficient unit 11 is operated.
The input current to the side is increased by Io for each data. K
Since 2 = 0 and K1 = 1, the current at the output is also 0 to 15
Io will increase by Io.

When the upper 3 bits are 1 (001), the lower 4 bits are all 0, but the lower 5th bit is 1, that is, since the upper 3rd bit is 1, all the lower 4 bits are bit-inverted and all 1s are set. Becomes Since the switches S0 to S3 are controlled by this data, there is no difference from the state of the switch in the previous data. At the same time, only the coefficient of the second coefficient unit 12 is increased from 0 to 2, but at this time, all the switches S0 to S3 are "
The analog output does not change at all because there is no current flowing to the 2nd coefficient multiplier 12 side because it has fallen to the 1 "side. Subsequently, the lower 4 bits will increase by one, but all bits are inverted. Therefore, the switches S0 to S3 have the same function as the decrease control, that is, the current produced by the lower 4 bits is increased by 1o each time the original data increases by 1o from the first coefficient unit 11 to the second coefficient unit 12 It will be moved to the side.
Since K2 = 2 and K1 = 1, the current at the output also increases by Io. In this way, the output current increases from 15 Io to 30 Io, and the lower data is all 1
Then, the switches S0 to S3 all reach the state of 0 side.

Next, when the upper 3 bits become 2 (010), the lower 4 bits are all changed to 0, but the lower 5 bit is 0 (the upper 3 bit is 0), and this time the lower 4 bits are All bits remain 0 without bit inversion. This data controls the switches S0 to S3, which is no different from the state of the switch in the previous data. At the same time, only the first coefficient unit 11 is increased from 1 to 3, but at this time, the switches S0 to S3 are all collapsed to the second coefficient unit 12 side (the switch is "0" side), There is no current flowing to the coefficient unit 11 side, and the analog output does not change at all. Subsequently, the lower 4 bits are increased by one, and the switches S0 to S3 are controlled to increase. That is, each time the original data increases by one data, the current generated by the lower 4 bits is moved from the K2 side to the K1 side by Io. K
Since 2 = 2 and K1 = 3, the current at the output is also I
o It will increase gradually. In this way, the output current increases from 30 Io to 45 Io, and the switches for the lower data are all 1
Reach the side.

By repeating such an operation, an analog output characteristic for digital data as shown in FIG. 2 is created. The feature of this circuit is that, in principle, the analog output cannot change at all when the upper bits change. This is because even if the lower order is saturated, the change corresponding to the carry is changed only by changing the coefficient value of the coefficient unit on the side opposite to the current path corresponding to the lower order data.
Distortion can be suppressed by eliminating the change at the time of carry and making the increase / decrease amount in the conversion characteristic completely depend on only the lower 4 bits.

Referring to FIG. 3, the first and second coefficient units 11,
Another embodiment of the present invention will be described with reference to 12 specific circuit examples. The first coefficient unit 11 has two 1 /
8 distribution channels 11a and three 1/4 distribution channels 11b
Of the current distributor. One output of the two 1/8 distribution paths 11a is directly connected to the output terminal I out. The second coefficient multiplier 12 constitutes a second current distributor by four 1/4 distribution paths. The output of the 1/4 distribution path 11b is passed through the switches S5, S7 and S9, and the output of the 1/4 distribution path of the second coefficient unit 12 is switched to the switches S4, S6, S8 and S9.
Each of them is connected to the output terminal Iout via 10. Each current distributor has a transistor and a resistor whose one end is connected to its emitter as a unit element, and has four base elements having the same resistance value R connected at their base ends to a common reference potential Vb and connected to the emitter. It is based on the configuration that the resistance end on the non-existing side is connected in common to form a current input terminal.

The second coefficient unit 12 uses the current distributor of this basic structure as it is, and the collector current of each transistor is used as a 1/4 distribution output to the switches S4, S6, S8 and S10.
Is connected to the output terminal Iout via. The first coefficient unit 11 has only one of the unit elements as compared with the above-mentioned basic configuration, in which the emitter area of the transistor is half and the resistance value is double (2R).
, Which are connected in parallel to each other, and only one of them is used as the 1/8 distribution output, and the other 1/8 distribution output is directly connected to the power supply Vcc, and the collectors of the transistors of the remaining unit elements. The current is connected to the output terminal Iout via the switches S5, S7 and S9 as a 1/4 split output.

The switches S0 to S3 controlled by the lower 4 bits of the switches S0 to S10 are the same as in the first embodiment. When the lower 5th bit data is 1
The point that the lower 4 bits are inverted and controlled as shown in FIG. The switches S4 to S10 controlled by the upper 3 bits alternately turn on the output switches in the OFF state of the current distributor one by one each time the upper 3 bits of the input digital data increase by 1. The control is carried out. As shown in FIG. 4, the upper 3 bits are decoded and the number of switches to be turned from 0 to 1 is increased by 1 according to the decoded value. FIG. 5 shows changes in the states of the switches S4 to S10 depending on the upper 3 bits. FIG. 6 shows the control by the lower 4 bits and the change in the value of the output current 8I1 to the first coefficient unit 11 and the value of the output current 8I2 to the second coefficient unit 12 at that time. The description formula of Iout in FIG. 5 and I1 in FIG.
From the above described expression, it can be seen that the total analog current output characteristic becomes the DA conversion characteristic as shown in FIG.

As is clear from the circuit form, the control of the coefficient values corresponding to the upper bits by the control of the switches S4 to S10 is a sequential addition, and the accuracy of the transistors and resistors constituting the current distributor is low. Even if there is, it only accumulates in the output current and does not appear as distortion at any one point. In this way, the problem as described above for the adjustment circuit, which is likely to cause problems, is avoided.
The elements that make up this circuit have a maximum element ratio of 1: 8.
The ratio is 1/8 compared to 1:64 in the conventional case of FIG. 7 which is the same 7-bit DA converter.

As described above, since the spread of the element ratio can be suppressed to be small, it is easy to obtain accuracy, and it is economical because the element size does not have to be increased. The obtained DA conversion characteristic is that, as shown in FIG. 4, the lower 4 bits are saturated and the output does not change by one data at the position where the lower 4 bits are advanced. This does not pose any problem when it is used as a DA conversion circuit for adjustment as described above. But the bottom 4
The dead zone can be completely eliminated by using a data format in which one of all 0s and all 1s is removed from the ordinary binary data as bit data, and even if this data format is used, this embodiment is also used. The fact that the conversion characteristic, which is a feature of the above, has little distortion is not impaired.

Although the present invention is suitable for a DA conversion circuit for an adjusting circuit, the present invention is not limited to this, and a wide range of applications as a general DA conversion circuit can be expected. In this case, in order to eliminate the dead point, if the data format in which only the lower bit is all 0 or all 1 is omitted from the normal binary data is used, such a dead zone can be completely eliminated. Alternatively, it is effective in some cases to handle such a data format as the entire system on the premise of such DA conversion.

[0024]

As described above, in the DA converter circuit according to the present invention, the linearity is determined only by the lower bits, and the adjustment dynamic range is extended by increasing the number of upper bits while maintaining this linearity. The advantage is that In other words, it is possible to finely adjust the adjustment resolution with respect to the adjustment dynamic range without increasing the element accuracy of the circuit.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a DA converter for explaining an embodiment of the present invention.

FIG. 2 is a conversion characteristic diagram of a DA converter obtained according to the present invention.

FIG. 3 is a circuit configuration diagram for explaining another embodiment of the present invention.

4 is an explanatory diagram for explaining switch control of the DA converter of FIG.

5 is an explanatory diagram for explaining switch control of upper 3 bits of the DA converter of FIG. 3;

6 is an explanatory diagram for explaining switch control of lower 4 bits of the DA converter of FIG. 3;

FIG. 7 is a circuit configuration diagram for explaining a conventional 7-bit current output type DA conversion circuit.

8 is a conversion characteristic diagram of the DA converter of FIG. 7.

[Explanation of symbols]

IN: input terminal, current source: 8Io, 4Io, 2Io, I
o, S0 to S10 ... switch, 11 ... first coefficient unit, 12
... second coefficient unit, 13 ... switch control circuit, 14 ... coefficient value control circuit, Iout ... output terminal.

Claims (9)

[Claims] 1. A current source for M bits weighted by a power of 2 ratio, first and second coefficient multipliers for multiplying an input current by a constant coefficient, and outputting the multiplied currents, said first and second coefficients. A switch group for switching which current source of the current source is input to the controller, means for controlling the switch group by the lower M + 1 bits of the input digital data, and the first N bits by the upper N bits of the input digital data.
And a means for controlling the coefficient value of the second coefficient unit, and an output section for taking out a combined output of the first and second coefficient units as an output current converted into an analog signal. . 2. A voltage source for M bits weighted by a power of 2 ratio, first and second coefficient multipliers for multiplying an input voltage by a constant coefficient and outputting the multiplied voltage, and the first and second coefficients. Switch, which switches which voltage source of the voltage source is input to the voltage source, and the coefficient multiplier by adding all the voltages obtained by the first and second coefficient multipliers via the switch group. And a second adder to be inputs to the switch, a third adder to add outputs from the first and second coefficient multipliers, and the switch group is controlled by lower M + 1 bits of input digital data. Means for controlling the coefficient value of the coefficient unit by the upper N bits of the input digital data, and an output unit for obtaining an output voltage obtained by converting the output of the third adder into an analog signal. DA conversion circuit to do. 3. The control of the switch group by the data of the lower M + 1 bits is performed by increasing or decreasing by one count in binary order from the lighter weight of the lower M bits, and the data of the M + 1th bit from the lower side is used. The increase / decrease of the switch control is switched, and the control by the upper N-bit data is such that every time the data increases by 1, the coefficient values of the first and second coefficient units are alternated and the magnitude relationship between the coefficient values is reversed. The DA conversion circuit according to claim 1 or 2, which is controlled. 4. The control of the switch group by the data of the lower M + 1 bits is performed by switching whether to invert the data of the lower M bits by the data of the M + 1th bit from the lower, and by the lower M bits that have undergone the processing. Increment control or decrement control of 1 count is performed in binary order from the lighter weight, and the control by the data of the upper N bits is 1
3. The DA conversion circuit according to claim 1 or 2, wherein the coefficient values of the first and second coefficient units are controlled alternately so that the magnitude relationship between the coefficient values is inverted every time the value increases. . 5. The lower M-bit data has a data format in which one of all 0's and all 1's is removed from ordinary binary data.
Alternatively, the DA conversion circuit according to claim 2. 6. The first coefficient unit comprises two 2- ^N distribution paths and two
^(N-1) -1 single 2 ^{- (N-1)} and the first current distributor having a distribution channel, 2 as the second coefficient unit ^(N-1) pieces of 2 ^{- (N-1)} distribution A second current distributor having a path, only one 2 ^-N distribution output is directly connected to the output terminal, and the 2- ^(N-1) distribution output is output terminal via each output switch. , And each time the upper N bits of the input digital data increase by 1,
The output switches in the OFF state of the current distributors are alternately turned ON one by one between the current distributors, and the binary switch of the changeover switch for the current source of the M-bit current source for the lower M bits. Control increase / decrease from lower to M + 1
2. The DA conversion circuit according to claim 1, wherein an analog current output corresponding to the input digital data is obtained at the output terminal by switching the bit data. 7. As a current distributor, a transistor and a resistor whose one end is connected to its emitter are used as unit elements, and the base end is connected to a common reference potential for 2 ^(N-1) unit elements having the same resistance value. Then, two circuits are provided as current input terminals by commonly connecting the resistance ends on the side not connected to the emitters, one circuit of which serves as the first current distributor, and only one unit element has that transistor. Has a means to further divide the collector current of 2 into two, and only one of the two divided into 2 ^−N distribution output, and the collector current of the transistor of the remaining unit element is 2 ^(N−1) −1. 2- ^(N-1) distribution output and the other circuit as second current distributor, collector current of transistor of each unit element is 2 ^(N-1) 2- ^(N-1) distribution output 7. The DA conversion circuit according to claim 6, wherein: 8. Means for bisecting current into one unit element of the first current distributor comprises connecting the base end to a common reference potential and to the emitter instead of this unit element. It is characterized in that the resistance end on the non-use side is replaced with two unit elements having a resistance value twice the common value connected in common, and the collector output of one of the unit elements is divided into two equal parts. The DA conversion circuit according to claim 7. 9. A means for bisecting a current to one unit element of the first current distributor comprises a collector output terminal of the unit element composed of two unit elements having different resistance values. Connected to a common connection point of the resistor ends on the side not connected to the emitter of the third current distributor, and connecting the base end of the third current distributor to a reference potential different from the common reference potential, One collector output of the third current divider is set to 2
8. The DA conversion circuit according to claim 7, wherein the DA conversion circuit outputs the signals in equal parts.