WO2000049642A3 - Halbleiterstruktur mit einer programierbarer leitbahn - Google Patents

Halbleiterstruktur mit einer programierbarer leitbahn Download PDF

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Publication number
WO2000049642A3
WO2000049642A3 PCT/DE2000/000298 DE0000298W WO0049642A3 WO 2000049642 A3 WO2000049642 A3 WO 2000049642A3 DE 0000298 W DE0000298 W DE 0000298W WO 0049642 A3 WO0049642 A3 WO 0049642A3
Authority
WO
WIPO (PCT)
Prior art keywords
strip conductor
semiconductor structure
producing
layer
programmable strip
Prior art date
Application number
PCT/DE2000/000298
Other languages
English (en)
French (fr)
Other versions
WO2000049642A2 (de
Inventor
Gerd Lichter
Original Assignee
Infineon Technologies Ag
Gerd Lichter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Gerd Lichter filed Critical Infineon Technologies Ag
Priority to EP00908981A priority Critical patent/EP1155447A2/de
Priority to JP2000600292A priority patent/JP4027039B2/ja
Publication of WO2000049642A2 publication Critical patent/WO2000049642A2/de
Publication of WO2000049642A3 publication Critical patent/WO2000049642A3/de
Priority to US09/930,409 priority patent/US6724055B2/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/36—Gate programmed, e.g. different gate material or no gate

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Die Halbleiterstruktur weist eine Leitbahn auf, die durch einen Hohlraum von einer unterliegenden isolierenden Schicht auf einem Träger getrennt ist. Das Herstellverfahren sieht vor, die Leitbahn zunächst auf einer Doppelschicht zu strukturieren und mit einer isolierenden Abdeckung zu versehen, eine Öffnung in die isolierende Abdeckung zu ätzen und dann die untere leitende Schicht selektiv zu entfernen. Damit kann einerseits eine kapazitätsarme Verdrahtung hergestellt werden, andererseits ist damit die Programmierung von MOS-Transistoren in einfacher Weise möglich.
PCT/DE2000/000298 1999-02-15 2000-02-01 Halbleiterstruktur mit einer programierbarer leitbahn WO2000049642A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00908981A EP1155447A2 (de) 1999-02-15 2000-02-01 Halbleiterstruktur mit einer programierbaren leitbahn
JP2000600292A JP4027039B2 (ja) 1999-02-15 2000-02-01 導体路を有する半導体構造体
US09/930,409 US6724055B2 (en) 1999-02-15 2001-08-15 Semiconductor structure having an interconnect and method of producing the semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19906291A DE19906291A1 (de) 1999-02-15 1999-02-15 Halbleiterstruktur mit einer Leitbahn
DE19906291.9 1999-02-15

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/930,409 Continuation US6724055B2 (en) 1999-02-15 2001-08-15 Semiconductor structure having an interconnect and method of producing the semiconductor structure

Publications (2)

Publication Number Publication Date
WO2000049642A2 WO2000049642A2 (de) 2000-08-24
WO2000049642A3 true WO2000049642A3 (de) 2001-03-15

Family

ID=7897567

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/000298 WO2000049642A2 (de) 1999-02-15 2000-02-01 Halbleiterstruktur mit einer programierbarer leitbahn

Country Status (5)

Country Link
US (1) US6724055B2 (de)
EP (1) EP1155447A2 (de)
JP (1) JP4027039B2 (de)
DE (1) DE19906291A1 (de)
WO (1) WO2000049642A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10126294C1 (de) * 2001-05-30 2002-11-28 Infineon Technologies Ag Herstellungsverfahren für eine integrierte Schaltung
US8022489B2 (en) * 2005-05-20 2011-09-20 Macronix International Co., Ltd. Air tunnel floating gate memory cell

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0651433A1 (de) * 1993-11-02 1995-05-03 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
US5670404A (en) * 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
US5786253A (en) * 1997-04-18 1998-07-28 United Microelectronics Corporation Method of making a multi-level ROM device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3635462A1 (de) * 1985-10-21 1987-04-23 Sharp Kk Feldeffekt-drucksensor
US4933743A (en) * 1989-03-11 1990-06-12 Fairchild Semiconductor Corporation High performance interconnect system for an integrated circuit
US5185294A (en) 1991-11-22 1993-02-09 International Business Machines Corporation Boron out-diffused surface strap process
US5413962A (en) * 1994-07-15 1995-05-09 United Microelectronics Corporation Multi-level conductor process in VLSI fabrication utilizing an air bridge
US6057224A (en) * 1996-03-29 2000-05-02 Vlsi Technology, Inc. Methods for making semiconductor devices having air dielectric interconnect structures
US6204103B1 (en) * 1998-09-18 2001-03-20 Intel Corporation Process to make complementary silicide metal gates for CMOS technology
US6441418B1 (en) * 1999-11-01 2002-08-27 Advanced Micro Devices, Inc. Spacer narrowed, dual width contact for charge gain reduction

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0651433A1 (de) * 1993-11-02 1995-05-03 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
US5670404A (en) * 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
US5786253A (en) * 1997-04-18 1998-07-28 United Microelectronics Corporation Method of making a multi-level ROM device

Also Published As

Publication number Publication date
US6724055B2 (en) 2004-04-20
JP2002537649A (ja) 2002-11-05
JP4027039B2 (ja) 2007-12-26
US20020066932A1 (en) 2002-06-06
DE19906291A1 (de) 2000-08-24
WO2000049642A2 (de) 2000-08-24
EP1155447A2 (de) 2001-11-21

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