WO2000048070A1 - Systeme et procede de mise en oeuvre de commutateur crossbar de processeur large bande - Google Patents

Systeme et procede de mise en oeuvre de commutateur crossbar de processeur large bande Download PDF

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Publication number
WO2000048070A1
WO2000048070A1 PCT/US2000/003566 US0003566W WO0048070A1 WO 2000048070 A1 WO2000048070 A1 WO 2000048070A1 US 0003566 W US0003566 W US 0003566W WO 0048070 A1 WO0048070 A1 WO 0048070A1
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Prior art keywords
bit
input
circuit
index
disable
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PCT/US2000/003566
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English (en)
Inventor
Craig Hansen
Bruce Bateman
John Moussouris
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Microunity Systems Engineering, Inc.
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Priority claimed from US09/382,402 external-priority patent/US6295599B1/en
Application filed by Microunity Systems Engineering, Inc. filed Critical Microunity Systems Engineering, Inc.
Priority to EP00910150A priority Critical patent/EP1236090A4/fr
Publication of WO2000048070A1 publication Critical patent/WO2000048070A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions

Definitions

  • Provisional Application No. 60/119,841, filed February 12, 1999 is a continuation-in-part of U.S. Patent Application No. 09/382,402, filed on August 24, 1999, which is in turn related to U.S. Patent Application No. 09/169,963, filed October 13, 1998, now U.S. Patent No. 6,006,318, which is in turn related to U.S. Patent Application No. 08/516,036, filed August 16, 1995, now U.S. Patent No. 5,742,840.
  • the contents of Provisional Application No. 60/119,841, filed February 12, 1999 are hereby incorporated by reference.
  • the present invention relates to cross-bar circuits, and particularly relates to a crossbar circuit implementing a switch of a broadband processor.
  • one of the basic operations is rearranging or copying portions of an operand.
  • Prior art systems such as current general purpose microprocessors (Pentium, MIPS, ARM, SPARC, PowerPC, etc.), implement this basic operation in various special circuits, such as shifters, rotators, field extractors, or byte permuters.
  • Digital processing is now being extended to new applications such as broadband processing in which very general rearrangements of bits are required to accomplish various sophisticated mathematical algorithms needed for encryption and error correction.
  • Such digital processing requires switching circuits, cross-bar circuits, to help accomplish these algorithms.
  • General switching requires a cross-bar circuit, which conventionally contains more transistors than the specialized shifters, rotator, etc. used in the prior art.
  • the present invention provides a cross-bar circuit that implements a switch of a broadband processor.
  • the present invention describes a system and method for implementing switching operations that perform completely general permutations and copies at the individual bit level within large operands.
  • the present invention describes a system and method for reducing the transistor count, wire count, and area of a general cross-bar network down to levels comparable to what is achieved in more specialized circuits.
  • This invention involves a novel combination of circuit techniques, including precharged dynamic multiplexors, ground selection, and pseudo- differential sensing against dummy bit lines, which have individually been practiced in digital logic and memory devices.
  • the present invention implements the system and method for utilizing wide operands further described in commonly-assigned U.S. Patent Application No. 09/382,402 to provide these control bits from a small cache memory physically located close to the cross-bar circuit.
  • the present invention also describes a system and method for utilizing the cross-bar circuits to perform conventional specialized operations as well. These operations have a great deal of redundancy in their control state.
  • the present invention describes a system and method for generating the large number of control bits of the cross-bar circuit (e.g. typically more than 1,000 bits) from a much smaller number of control bits for conventional operations (e.g. typically fewer than 100 bits). This invention conserves the resources and delays that would otherwise be incurred in the use of the wide operand memory referred to in the previous paragraph.
  • the present invention describes a system and method to implement a cross-bar circuit, memory, and control of a switch of a broadband processor, that (1) requires (a) a small area of silicon, (b) very low power, (c) a small number of transistors, (d) a small number of wires, and (e) only two metal layers, (2) operates at a high speed, and (3) has high functionality.
  • the present invention provides a cross-bar circuit that, in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from a 2 n -bit (e.g. 256-bit) input source word to be switched into any bit position of a 2 m -bit (e.g. 128-bit) output destination word and (2) provides the ability to set-to-zero any bit in said 2 m -bit output destination word.
  • the cross-bar circuit includes: (1) a switch circuit which includes 2 m 2 n :l multiplexor circuits, where each of the 2 n :l multiplexor circuits (a) has a unique n-bit (e.g.
  • a control circuit that (a) has a plurality (e.g. 100) of control inputs, (b) receives the partially-decoded instruction information on the plurality of control inputs, (c) provides a second set of the n-bit indexes for the switch circuit, and (d) provides the disable bits for the switch circuit, where the control circuit is logically coupled to the switch circuit and to the cache memory.
  • the present invention provides a switch circuit that allows any bit from a 2 n -bit (e.g. 256-bit) input source word to be switched into any bit position of a 2 m -bit (e.g. 128-bit) output destination word and that provides the ability to set- to-zero any bit in the 2 m -bit output destination word.
  • the switch circuit includes 2 2 n : 1 multiplexor circuits, where each of the 2 n :l multiplexor circuits (a) has a unique n-bit (e.g.
  • each of the 2 n :l multiplexor circuits includes: (1) a 2 q :l pass gate selector (e.g.
  • each of the unit switch cells (a) is logically coupled to a wire-OR bitline input of the 2 q :l pass gate selector, (b) is logically coupled to one of 2 r (e.g. one of 8) active-LOW “SELA” select wires, and (c) is logically coupled to one of 2 n'q"r (e.g. one of 8) active-HIGH “SELC” select wires.
  • an exemplary implementation of the present invention provides a control circuit that provides indexes and disable bits.
  • the control circuit includes: (1) an arithmetic logic unit (ALU), where the ALU includes a plurality of ALU modules; (2) a plurality of multiplexors logically coupled to the ALU, where each of the multiplexors includes a plurality of multiplexor modules; and (3) a plurality of decoders logically coupled to the ALU and to the plurality of multiplexors, where each of the decoders includes a s-stage (e.g. 5 stage) chain of NAND/NOR gates.
  • ALU arithmetic logic unit
  • the switch circuit Since the switch circuit requires no more silicon area than a barrel shifter and since the switch circuit can perform the functions of a barrel shifter, the switch circuit can be used in place of a barrel shifter in a circuit design, thus saving space in the circuit design.
  • the control circuit generates a relatively large number of bits (e.g. 1024 bits), which comprise a pattern of bits. This pattern of bits is often repetitive. Taking advantage of the repetitiveness of this pattern of bits, the control circuit can use a relatively small number of bits (e.g. 64 bits) to generate a relatively large number of bits (e.g. 1024 bits).
  • the control circuit generates n* 2 m bits (e.g. 1024 bits) as a pattern of bits by using only 2 n"2 input bits (e.g. 64 input bits).
  • Figure 1 A is a first system level diagram showing the functional blocks of a cross-bar circuit according to an exemplary embodiment of the present invention.
  • Figure IB is a second system level diagram showing the functional blocks of a crossbar circuit according to an exemplary embodiment of the present invention.
  • Figure IC is a third system level diagram showing the functional blocks of a cross-bar circuit according to an exemplary embodiment of the present invention.
  • Figure 2A is a block diagram of the switch circuit according to an exemplary embodiment of the present invention.
  • Figure 2B is a block diagram of a typical 256:1 multiplexor circuit according to an exemplary embodiment of the present invention.
  • Figure 2C is a block diagram of a typical 1x256 switch module according to an exemplary embodiment of the present invention.
  • Figure 2D is a block diagram of a typical 1x128 switch module according to an exemplary embodiment of the present invention.
  • Figure 2E is a block diagram of a typical 1x32 switch module according to an exemplary embodiment of the present invention.
  • Figure 3 A is a block diagram of a typical 1x8 switch module according to an exemplary embodiment of the present invention.
  • Figure 3B is a diagram of a typical unit switch cell according to an exemplary embodiment of the present invention.
  • Figure 4 is a diagram of the cache memory according to an exemplary embodiment of the present invention.
  • Figure 5 A is a block diagram of the control circuit according to an exemplary embodiment of the present invention.
  • Figure 5B is a block diagram of a typical control slice according to an exemplary embodiment of the present invention.
  • Figure 5C depicts gate-level diagrams of a typical Arithmetic Logic Unit (ALU) bit when a physical address bit input to the ALU bit is "0" according to an exemplary embodiment of the present invention.
  • ALU Arithmetic Logic Unit
  • Figure 5D depicts gate-level diagrams of a typical Arithmetic Logic Unit (ALU) bit when a physical address bit input to the ALU bit is "1" according to an exemplary embodiment of the present invention.
  • ALU Arithmetic Logic Unit
  • Figure 5E depicts gate-level diagrams of a typical ALU bit when a physical address bit input to the ALU bit is "0" according to an exemplary embodiment of the present invention.
  • Figure 5F depicts gate-level diagrams of a typical ALU bit when a physical address bit input to the ALU bit is "I" according to an exemplary embodiment of the present invention.
  • Figure 5G is a circuit diagram of a prior art CMOS transfer-gate.
  • Figure 5H is a gate-level diagram of a MUX module according to an exemplary embodiment of the present invention.
  • Figure 51 depicts gate-level diagrams of two MUX modules according to an exemplary embodiment of the present invention.
  • Figure 6 is a gate-level diagram of an ALU, 8x 2: 1 MASK multiplexor, and SCALE multiplexor arrangement according to an exemplary embodiment of the present invention.
  • Figure 7 is a block diagram of a MSB/LSB decoder according to an exemplary embodiment of the present invention.
  • Cross-bar circuit 100 is organized as a 128-bit wide 256:1 multiplexor.
  • Cross-bar circuit 100 in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from either of two 128-bit input source words, SOURCE M and SOURCE L, to be switched into any bit position of a 128-bit output destination word, DESTINATION and (2) provides the ability to set-to-zero any bit in the 128-bit output destination word, DESTINATION.
  • this exemplary embodiment and others discussed thereafter refer to exemplary bit sizes for inputs, outputs, and circuit components, these bit sizes are merely examples and are not intended to limit the invention to the exemplary bit sizes.
  • cross-bar circuit 100 in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from a 256-bit input source word, comprised of a 128-bit input source word SOURCE M and a 128- bit input source word SOURCE L, to be switched into any bit position of a 128-bit output destination word DESTINATION and (2) provides the ability to set-to-zero any bit in the 128-bit output destination word DESTINATION.
  • cross-bar circuit 100 includes a control circuit 105, a cache memory 110, and a switch circuit 115.
  • control circuit 105 receives partially decoded instruction information on 128 control inputs and (ii) generates 128 8-bit indexes and 128 disable bits.
  • cache memory 110 (i) receives datapath information on 128 cache datapath inputs, (ii) receives 128 8-bit indexes from control circuit 105, (iii) can generate its own 128 8-bit indexes, and (iv) can store at least 128 8-bit indexes.
  • switch circuit 115 receives 128 8-bit indexes, generated by either control circuit 105 or cache memory 110, (2) receives 128 disable bits generated by control circuit 105, (3) receives a 128-bit input source word SOURCE M and a 128-bit input source word SOURCE L, and (4) generates a 128-bit output destination word DESTINATION in response to the received 128 8-bit indexes and the received 128 disable bits.
  • cross-bar circuit 100 includes a control top 120, a cache top 130, a switch circuit 140, a cache bottom 150, and a control bottom 160.
  • cross-bar circuit 100 is comprised of three basic building blocks: a switch circuit 140, a cache memory, and a control circuit.
  • the control circuit is physically divided into the following two blocks: (i) control top 120 which is physically located above switch circuit 140; and (ii) control bottom 160 which is physically located below switch circuit 140.
  • the cache memory is physically divided into the following two blocks: (i) cache top 130 which is physically located above switch circuit 140; and (ii) cache bottom 150 which is physically located below switch circuit 140.
  • switch circuit 140 includes decoders, drivers, sense amplifiers, and switch modules.
  • the decoders, drivers, and sense amplifiers are physically divided into the following two blocks: (i) a decoders, drivers, and sense amplifiers top 142 which is physically located above the switch modules; and (ii) a decoders and drivers bottom 148 which is physically located below the switch modules.
  • the switch modules are physically divided into the following two blocks: (1) a switch modules top 144; and (2) a switch modules bottom 146, which is physically located below switch modules top 144.
  • the circuit design and layout of the cross-bar circuit 100 can be completely implemented in a first metal layer, Ml, and a second metal layer, M2.
  • Ml first metal layer
  • M2 second metal layer
  • the cross-bar circuit to be placed under global bussing connecting other circuits in a datapath logically coupled to cross-bar circuit 100, where the global bussing for the datapath is implemented in metals layers located physically higher than Ml and M2, such as a third metal layer, M3, and a fourth metal layer, M4.
  • the global bussing is implemented vertically in M3 and M4.
  • the entire circuit layout of cross-bar circuit 100 can be implemented in only Ml and M2 so that cross-bar circuit 100 can fit under the M3 and M4 global bussing.
  • switch circuit 200 includes the following components, logically interconnected as shown:
  • Each of the 256:1 multiplexor circuits 202-204 (1) can also be referred to as a bit-slice of switch circuit 200 and (2) has (a) a unique 8-bit index input logically coupled to an 8-bit wide index input line and (b) a unique disable input logically coupled to a disable input line.
  • Each of the 256:1 multiplexor circuits 202-204 (1) receives a 256-bit input source word in the form of a 128-bit input source word SOURCE M on 128-bit wide SOURCE M input line 213 and a 128-bit input source word SOURCE L on 128-bit wide SOURCE L input line 214 and (2) receives an 8-bit index at its 8-bit index input and a disable bit at its disable input.
  • Each of the 256:1 multiplexor circuits 202-204 decodes the received 8-bit index to do the following: (1) either select and output as an output destination bit, DESTINATION[x], one bit from the 256-bit input source word if the disable bit has a logic low value (2) or output a logic low as the output destination bit, DESTINATION ⁇ ], if the disable bit has a logic high value.
  • 256: 1 multiplexor circuit 220 includes the following components, logically interconnected as shown: (1) 128-bit wide SOURCE M input line 213;
  • index input lines enter at the top of 256:1 multiplexor circuit 220, while the remaining four index input lines enter at the bottom of 256: 1 multiplexor circuit 220.
  • SELC l-of-8 decoder 235 is physically located at the top of 256:1 multiplexor circuit 220
  • SELA l-of-8 decoder 236 is physically located at the bottom of
  • l-of-4 decoder 234 is physically located at the top of
  • l-of-4 decoder 234 decodes one index bit, INDEX[3], bussed up from the bottom of multiplexor circuit 220 and another index bit, INDEX[4], from the top of multiplexor circuit 220 (a) to select one of the four wire-OR bitlines 240-243 and (b) to pass the value on the selected wire-OR bitline to 4:1 pass gate selector 247.
  • 4:1 pass gate selector 247 is physically located at the top of multiplexor circuit 220.
  • sense amplifier 248 is physically located at the top of multiplexor circuit 220,.
  • a signal on dummy-bitline 232 is passed into sense amplifier 248.
  • Sense amplifier 248 uses the signal on dummy-bitline 232 to perform differential sensing and to accurately sense the output of 4:1 pass gate selector 247, especially small signal swings.
  • 1x256 switch module 250 includes the following components, logically interconnected as shown: ( 1 ) a 128-bit wide SOURCE M input line 213, referred to as
  • an 8-bit wide SELC select line comprised of (a) a first 4-bit SELC select line 252, referred to as SELC_BM ⁇ 3..0>, and (b) a second 4-bit wide
  • SELC select line 253 referred to as SELC_BM ⁇ 7..4>;
  • an 8-bit wide SELA select line comprised of (a) a first 4-bit SELA select line 255, referred to as SELA_BNM ⁇ 3..0>, and (b) a second 4-bit wide SELA select line 256, referred to as SELA_BNM ⁇ 7..4>; (5) four wire-OR bitlines 240-243, referred to as BL_BNM ⁇ 0> -
  • 1x128 switch module 260 includes the following components, logically interconnected as shown:
  • second 4-bit wide SELA select line 256 referred to as SELA_BNM ⁇ 7..4>; and (8) four 1x32 switch modules 271-274.
  • 1x32 switch module 275 includes the following components, logically interconnected as shown:
  • SELCLF_BM a left SELC select line 285, referred to as SELCLF_BM
  • 1x8 switch module 300 includes the following components, logically interconnected as shown:
  • SRCRT_BM ⁇ 3> where the set SRCRT_BM ⁇ 0>-SRCRT_BM ⁇ 3> is exemplary of the four sets SRCRT_BM ⁇ 3..0>, SRCRT_BM ⁇ 7..4>, SRCRT_BM ⁇ 11..8>, and SRCRT_BM ⁇ 15..12> in Figure 2E;
  • Unit Switch Cell Referring next to Figure 3B an exemplary embodiment of a typical unit switch cell
  • unit switch cell 340 referred to as unit switch cells 322-329 in Figure 3A, is illustrated in block diagram form.
  • unit switch cell 340 includes the following components, logically interconnected as shown:
  • SELA_BNM a SELA select line 346, referred to as SELA_BNM, which is exemplary of one of the eight SELA select lines 313-320 in Figure 3 A;
  • SELC_BM a SELC select line 347, referred to as SELC_BM, which is exemplary of 10 one of the two SELC select lines 284 or 285 in Figure 3 A;
  • SRC_BM a SRC source line 350, referred to as SRC_BM, which is exemplary of one of the eight input source lines 304-311, referred to as SRCRT_BM ⁇ 0> - SRCRT_BM ⁇ 3> and SRCLF_BM ⁇ 0> - SRCLF_BM ⁇ 3 in Figure 2E; and 15 (6) wire-OR bitline 302, referred to as BL BNM, also in Figure 3 A.
  • SELA select line 346 has a logic low value and if SELC select line 347 has a logic high value, then the logic value on SRC source line 350 will be transferred to wire-OR bitline 302. In other words, if SELA select line 346 has a logic low value, if SELC select line 347 has a logic high value, and if SRC source line 350 has a logic high value, then wire-OR bitline 302 20 will have a logic high value. If SELA select line 346 has a logic low value, if SELC select line 347 has a logic high value, and if SRC source line 350 has a logic low value, then wire- OR bitline 302 will have a logic low value.
  • SELA select line 346 has a logic low value and if SELC select line 347 has a logic high value, then unit switch cell 340 is selected and the logic value on if SRC source line 350 will be transferred to then wire-OR bitline 302. 25 1x8 Switch Module
  • Objective #1 is driven by the desire to minimize the height of the XLU structure.
  • the driving limitation is the number of vertical wires needed to accomplish the l-of-256 wire-OR select plus any overhead needed for interconnection and data sensing.
  • the minimum number of select lines that could be used would be 16: 3 groups of l-of-4 hot busses and one group of 4 wire-OR bitlines. However, this would require the unit switch cell 340 to use three series connected NFETs which would require additional interconnection overhead and give lower read current for a given transistor width.
  • the preferred embodiment uses two l-of-8 hot busses for the SELA and SELC lines, and 4 separate wire-OR bitlines (plus one dummy bitline) which go through a 4:1 MUX for the final selection.
  • the 4:1 MUX is placed outside the switch and thus theoretically does not require any additional wire tracks within the array of switch cells to bus the select wires for the MUX. This gives a total of 21 vertical wires for data selection and sensing. Another 4 Ml tracks plus 2 spare tracks were needed for connection of the horizontal M2 "SRC" wires to the gates of the data-in transistors. Finally, 2 Ml Vss wires were needed to shield the small swing bitlines from the full swing select lines and to allow for P-well taps in the array.
  • Objective #3 attempts to maximize the "read" current of unit switch cell 340 by obtaining the largest possible transistor width.
  • the limiting factor here was the number of transistor that could be stacked in the height of the cell - 8 M2 pitches.
  • NFETs should be connected to which signal.
  • the choice of placing the SELC transistor 342next to wire-OR bitline 302 was made to both minimize the capacitance on the bitline 302 and to make the capacitance non- varying.
  • the problem was that any data combination can be present on the data-in wires, ranging from all high to all low. If the data-in transistors were placed next to bitline 302, then bitline 302 would see the channel and source terminal capacitance of every data-in transistors whose data-in signal was high. This would make the bitline capacitance higher and also variable as a function of the state of the data-in signals. Since the read current of unit switch cell 340 is limited by the transistor size, it was deemed better to put the variable capacitance on SELA line 346 where the signal drivers can be made large enough to handle the higher capacitance.
  • Each 1x8 switch module 300 has bits 0-3 of the 8 SELA wires connected on the left side of the cell to four SELA select lines 313-316, SELA_BNM ⁇ 0> - SELA_BNM ⁇ 3>, and bits 4-7 of the 8 SELA wires connected on the right side of the cell to four SELA select lines
  • 1x32 switch module 275 includes four 1x8 switch modules 286-289, with 1x8 switch module 286 connected to wire-OR bitline ⁇ 0> 240, 1x8 switch module 287 connected to wire-OR bitline ⁇ l> 241, 1x8 switch module 288 connected to bitline ⁇ 2> 242, and 1x8 switch module 289 connected to bitline ⁇ 3> 243.
  • 1x128 switch module 260 includes four 1x32 switch modules 271-274, with the 1x32 switch module 271 having the left SELC input connected to bit ⁇ 0> of the left group of 4 SELC wires 270 and the right SELC input connected to bit ⁇ 0> of the right group of 4 SELC wires 269.
  • 1x32 switch module 272 has the SELC inputs connected to bit ⁇ l> of the left and right groups of 4 SELC wires, and so forth for the third and fourth cells.
  • switch circuit 200 has decoded 128 inputs (32 inputs on each of 4 wire-OR bitlines) where the "left” 64 inputs (SRCLF) are selected by the intersection of the "left” 4 SELA bits and the “left” 4 SELC bits, and the "right” 64 inputs are selected by the intersections of the "right” 4 SELA bits and the “right” 4 SELC bits.
  • SRCLF "left" 64 inputs
  • SELA and SELC are both l-of-8 hot busses, this only covers half of the possible combinations because when the "hot” SELA wire is on the left side, the "hot” SELC wire could be on the right side and vice-versa.
  • 1x256 switch module includes two 1x128 switch modules, 258 and 259, where the left and right SELC groups of 4 bits are reversed (or twisted) between the two 1x128 switch modules.
  • the 1x128 switch module 259 decodes the 128 combinations missed by 1x128 switch module 258.
  • the hierarchy of this programming scheme is that the SELA bits have the least significance, then the l-of-4 wire-OR bitline select, and finally the SELC bits have the highest significance. This hierarchy is driven by the fact that the 8 index bits for each 256: 1 multiplexor circuit are physically divided with 4 index bits coming from the bottom of cross-bar circuit 100 and the other 4 coming from the top of the cross-bar circuit 100.
  • the SELCO wire is connected to the left side of the bottom 4 "1x8" cells in the bottom half of the column and is connected to the right side of the bottom 4 "1x8" cells in the top half of the column. Therefore, as the SELA address is incremented, first the 4 left data-inputs in the bottom 4 "1x8" cells of the bottom half of the column are sequentially selected as SELA bits 0-3 are toggled. Then after we jump from SELA ⁇ 3> to SELA ⁇ 4>, the 4 right data-inputs in the bottom 4 "1x8" cells of the top half are sequentially selected as SELA bits 4-7 are toggled.
  • bitline ⁇ 0> Since bitline ⁇ 0> is selected, this means that we sequentially select the first 4 left data-inputs from the bottom half of the column and then the first 4 right data-inputs from the top half of the column. If we then move from bitline ⁇ 0> to bitline ⁇ l> and wrap SELA back to bit ⁇ 0>, we next sequentially select the second 4 left data-inputs from the bottom half of the column and then the second 4 right data-inputs from the top half of the column.
  • wire-OR bitlines are relatively high in capacitance and the unit switch cell has limited read current, it is desirable to use small signal swing on the wire-OR bitlines 240-243 to improve the speed performance. This also implies that it is desirable to use differential sensing of some form, but the bitlines are only single- end. Thus a dummy bitline 232 for use in sensing is needed. Only one dummy bitline 232 is needed for all 4 wire-OR bitlines since only one wire-OR bitline is selected for evaluation by the sense amp.
  • the critical design/layout objective for the dummy bitline 232 is to have it match the wire-OR bitlines 240-243 as closely as possible for both capacitance and read current. Thus we must first evaluate the electrical properties of the wire-OR bitlines.
  • Each wire-OR bitline is connected to 64 unit switch cells - 8 unit cells per "1x8" cell and 8 "1x8" cells per bitline.
  • the SELC transistor in the switch cell is connected to the bitline. Therefore, since the SELC bus is l-of-8 hot, the bitline sees 8 unit cells where the SELC transistor is on, exposing the bitline to the capacitance of the intermediate node of the switch cell and to the gate edge capacitance of the data-in transistor. In the other 56 unit cells the SELC transistor is off and the bitline only sees the gate edge capacitance of the SELC transistor.
  • the 8 unit switch cells that are selected have 7 cells where the SELA input is high. In these cells, the state of the data-input is essentially irrelevant since there is no discharge path from the bitline. In the 8th cell, the SELA input is low and thus if the data- input is high, the transistor turns on and provides a discharge path from the "high" bitline to the "low” SELA line.
  • a "dummy 1x8" cell is added at the bottom of the column.
  • This dummy cell is similar to the standard "1x8" cell except for three details.
  • the unit cell has a stack of four transistors rather than the two transistors in the standard switch cell. This is done to have the dummy cell provide half the read current of the standard cell.
  • the output of the cell is connected to the dummy bitline instead of to one of the 4 wire-OR bitlines.
  • all the gates in the dummy cell are tied to Vdd rather than to the SELC and data wires.
  • the dummy "1x8" cell provides a discharge path from the dummy bitline to the "low" SELA line in the same manner as the standard "1x8" cell, but at half the current. Furthermore, the dummy cell nearly duplicates the capacitance of the 8 unit switch cells on the normal wire-OR bitline that are selected by the "high" SELC line.
  • the dummy bitline now matches the wire-OR bitlines in wire length and nearest neighbor coupling, discharge path, transistor overlap capacitance, and drain junction capacitance.
  • cache memory 110 is the first of two sources for the index inputs to the switch.
  • the cache memory is a small tightly coupled memory array that stores eight entries of 128 8-bit indexes for the switch (e.g. - 8 1024 bit words).
  • the cache can be used to store random switching patterns provided by a datapath logically coupled to cross-bar circuit 100 or to capture index patterns generated by the instruction decode logic logically coupled to cross-bar circuit 100. These patterns can then be used repetitively without the datapath having to incur the overhead of repeatedly generating these patterns.
  • the instruction decode logic is described in Appendix 2 - Instruction Decode Logic.
  • the "cache” includes 8 lines, 402-404, of 1024 bits - 8 columns per bit-slice of the MUX.
  • the each cache line 402-404 is divided into 128 cache slices 408-412, where each cache slice 408-412 has 8 bits - one column per index bit of the switch circuit 200.
  • the 1024 bits of the cache line are bundled into 128 cache slices of eight bits each corresponding to the eight index bits for each 256:1 multiplexor circuit 220.
  • cache memory 110 is physically divided into two SRAM arrays each having 8 rows of 512 columns - 128 slices" of 4 columns each.
  • the arrays are pitch-matched to the switch circuit 115 such that one 4 column slice in the cache matches up with one 256:1 multiplexor circuit 220 in the switch circuit 200.
  • One array is physically located immediately below the switch circuit 140 and one is physically located immediately above the switch circuit 140, as shown in Figure IC, thus providing a total of 8 index bits per
  • control circuit 105 is the second source for the index inputs to the switch circuit 115. It is also the source for the 128 disable inputs to the switch circuit 115.
  • the control circuit 105 takes partially decoded instruction information from datapath control logic logically coupled to cross-bar circuit 100 and completes the decoding into an appropriate 8-bit index and disable bit for each of the 128 256:1 multiplexor circuits 202-204 in the switch circuit 200.
  • This decoding implements the cross-bar operations provided in the ISA such as rotate, shift, swap, shuffle, deal, and extract.
  • the cross-bar operations provided in the ISA are included in Appendix 1 - Cross-bar
  • control circuit 105 Operations Provided in the ISA.
  • the output of this control circuit 105 is passed through the cache memory 110 on its way to the switch circuit 115, thus allowing the indexes to be captured by the cache memory 110 for subsequent cross-bar operations.
  • the control circuit 105 generates 128 8-bit indexes for the switch circuit 115 and the cache memory 110 and generates 128 disable bits for the switch circuit 115.
  • the control circuit 500 includes 128 nearly identical control slices 501-503.
  • the control slices 501-503 (i) receive partially-decoded instruction information and (ii) in response to the received partially-decoded instruction information, generate 128 8-bit indexes, INDEX 0 - INDEX 127 and 128 disable bits, DISABLE 0 - DISABLE 127.
  • each control slice 510 includes an arithmetic logic unit (ALU) 512, an 8x 2:1 MASK multiplexor 514, an 8x 2:1 INDEX multiplexor 516, a Most Significant Bit (MSB) decoder 518, a Least Significant Bit (LSB) decoder 519, and a SCALE decoder 521.
  • ALU arithmetic logic unit
  • MSB Most Significant Bit
  • LSB Least Significant Bit
  • SCALE decoder 521 SCALE decoder
  • a main index for each control slice 510 is calculated by an ALU 512 which adds the 8-bit input IAddO/IAddl amount to the physical location of the control slice to get the main index for the source bit.
  • This function thus supports ISA commands such as shift and rotate.
  • the output of the ALU 512 then flows through 8x 2:1 MASK multiplexor 514 which selects either the ALU 8-bit output or a "mask" value provided by the IConstO/IConstl 8-bit inputs.
  • the selection choice is set by the LSB and MSB decoders 518 and 519 and the two Select_IMask bits. Four cases are supported:
  • the MSB and LSB decoders 518 and 519 are used to identify leading edge and/or trailing edge bits in bit-groups of the cross-bar circuit output. These bit groups may be nibbles, bytes, doublets, quadlets, octlets, or the full hexlet.
  • the outputs of the MSB and LSB decoders 518 and 519 are used in each control slice 510 to do one or more of the following:
  • IAdd and IConst buses there are two copies of the IAdd and IConst buses.
  • the "0" or “V copy of each bit of these buses is connected to ALU 512 and the 8x 2:1 MASK multiplexor 514 depending on whether the corresponding bit of the physical address of the control slice is a "0" or a " 1 ".
  • IAddO and IConstO are connected to the ALU 512 and 8x 2:1 MASK multiplexor 514 inputs in the "even" control slices, while IAddl and IConstl are connected to the ALU 512 and 8x 2:1 MASK multiplexor 514 inputs in the "odd" control slices.
  • IAddO and IConstO are connected to the ALU 512 and 8x 2:1 MASK multiplexor 514 inputs in the even pairs of control slices (0&1, 4&5, 8&9, etc) while IAddl and IConstl are connected to the ALU 512 and 8x 2:1 MASK multiplexor 514 inputs in the odd pairs of control slices (2&3, 6&7, 10&11, etc).
  • IAddl and IConstl are set to the same values as IAddO and IConstO, thus supporting identical shift calculations for all 128 indexes outputted from control circuit 100.
  • some operations require the splitting of these values, usually with IAddl and IConstl being the inverse of IAddO and IConstO. 8x 2:1 INDEX Multiplexor
  • the output of the 8x 2:1 MASK multiplexor 514 then flows through the 8x 2:1 INDEX multiplexor 516 which selects either the calculated/masked index or the output of the SCALE decoder 521.
  • This selection is done on a bit-by-bit basis within the control slice 510 as determined by the corresponding bits of the ISize 8-bit input bus.
  • the value on the ISize 8-bit bus is a thermometer value which select the Mask output in the lower order bits and the IScale value in the higher order bits of the index.
  • the SCALE decoder 521 takes a 7-bit field from the IMux_Select bus for each bit of the index and examines selected bits from that field. The bits that are examined are determined by the physical address of the control slice 510. If the physical address of the control slice 510 has a minority of "ones", then the bit positions of the 7-bit IMux_Select field that correspond to the "ones" in the 7-bit physical address are ANDed in the scale decoder.
  • bits 0-5 outputted by 8x 2:1 INDEX multiplexor 514 in each control slice 510 are output directly to the cache memory 1 i ⁇ but bits 6 and 7 go through some additional processing. Both bits 6 and 7 can be overridden by the Kill_Bit6 and Kill_Bit7 inputs, which globally force their respective index bits to "zero".
  • bit 7 sees one final level of processing. This level of processing forces bit 7 of the index to a "one" depending on the state of the two Select_Merge bits and the outputs of MSB decoder 518 and LSB decoder 519. Four cases are supported:
  • LSB Mask decoder 519 decode break point and at or above the MSB Mask decoder 518 decode break point are selected from SOURCE M. All bits between the LSB decoder 519 decode break points and the MSB decoder 518 decode break points are selected from SOURCE L. Force Off
  • the final function in the control slice 510 is the "Force Off logic which determines the state of the "Off output bit. This "Off output bit passes over the cache memory 110 and sets the state of the disable bit in the 256:1 multiplexor circuit 220. The state of the "Off bit is determined by the state of the Select_Enable bits and the
  • control circuit 105 is divided into two blocks of 128 control slices 502-504, each in a manner similar to the cache memory 110.
  • One block, control bottom 160 is placed immediately below the cache bottom 150 and generates the lower four index bit, INDEX[0] - INDEX[3].
  • the other block, control top 120 is placed immediately above the cache top 130 and generates the upper four index bits, DSfDEX[4] - INDEX[7] plus the "off bit.
  • control bottom 160 contains the following logic for just the lower four index bit, INDEX[0] - INDEX[3]: the ALU 512; the 8x 2:1 MASK multiplexor 514; the 8x 2:1 INDEX multiplexor 516; and the SCALE decoder 521.
  • the select input for the 8x 2:1 MASK multiplexor 514 is bussed down from the control top 120.
  • control top 120 contains the same logic as control bottom except for the upper four index bits, INDEX[4] - INDEX[7] plus the "off bit. Control top 120 also duplicates the carry chain for just the lower four index bit, INDEX[0] - INDEX[3]. Control top 120 also contains the LSB and MSB decoders 519 and 518 and the Kill_Bit, Select_Merge, and Force_Off logic.
  • the major task in the circuit implementation of the control circuit 500 was to reduce the logic to a form that would minimize global wire count and to minimize the transistor count that had to fit under the global wires in M3 and M4. Wire count reduction required that differential global signals be avoided (such as multiplexor select lines) and that global wires be shared if possible.
  • the traditional ALU "bit" 532 or 542 includes a 3-in ⁇ ut XOR 533 or 543 to do the ADD and a 3-input MAJORITY gate 534 or 544 to generate the CARRY.
  • one input to the ALU 512 is hardwired to the physical address of the control slice 510.
  • the hardwired input to the ALU bit is eliminated through logic reduction, as shown in typical ALU bits 536 and 546 in Figure 5C and Figure 5D, respectively.
  • the "tradeoff here is that the programming of the physical address then has to be done by programming which reduced circuits are placed in the control slice 510 rather than by having a contact/metal wiring option to tie the physical address inputs to the appropriate rail. There are two cases to consider:
  • the physical address bit input to the ALU “bit” is “0", traditional ALU bit 532 and an exemplary embodiment of an ALU bit 536, as depicted in Figure 5C; and 2.
  • the physical address bit input to the ALU “bit” is " 1 ", traditional ALU bit 542 and an exemplary embodiment of an ALU bit 546, as depicted in Figure 5D.
  • the physical address bit input to the ALU "bit” is "I”, represented by ALU modules 552 and 556, as depicted in Figure 5F.
  • ALU module 552 including an XOR 557 and a NOR 558 logically coupled as shown in Figure 5E and Figure 5F and (ii) ALU module 552 including an XNOR 553 and a NAND 554 logically coupled as shown in Figure 5E and Figure 5F, cover the four permutations of physical address bit value and input/output inversions required for a typical ALU 512.
  • each 256:1 multiplexor circuit 220 there is a corresponding control slice 502-506.
  • Each 256:1 multiplexor circuit 220 has a physical address bit.
  • Each control slice 510 includes an ALU 512.
  • the ALU 512 is an 8-bit ALU. As an example of the ALU programming, if the physical address of 256:1 multiplexor circuit is 00000000 2 , then for bit 0 of ALU 512, the following is true:
  • ALU bit 0 is an Even bit (i.e. ALU "Bit” is "Even”.);
  • each control slice 510 contains 16 multiplexors (8 in control top 120 and 8 in the control bottom 160, one of the primary objectives in the crossbar circuit design is to minimize the layout area of cross-bar circuit 100 by using the minimum number of transistors and wires per multiplexor.
  • the number of wires is of particular concern since the height of the control slice 510 is primarily determined by the number of horizontal input wires that feed the control slice 510.
  • CMOS transfer-gate multiplexor 560 was not used for the multiplexors in control slice 510 for following reason: since the multiplexors have a mixture of local and global inputs, the use of a transfer-gate multiplexor is problematic unless both the data inputs and the select inputs are buffered locally to prevent unwanted pass gate activation due to either mismatches between local and distance supply levels or to noise on the input lines. In a worst case scenario, a CMOS transfer-gate multiplexor 560 would add 4 inverters, 562-565, to each multiplexor with an additional 4 local wires.
  • a 22-AOI 580 is used, as shown in Figure 5H.
  • This approach solves the problem of needing to buffer global signals and has a minimal number of internal wires. It does have the drawback of requiring an additional inverter 582 to eliminate the need for a differential select line.
  • the select inverter 582 and the AND gate 584 can be combined into a NOR gate and the 22-AOI reduced to a 21-AOI, as depicted in Figure 51.
  • the resulting circuit, 591 is attractive because it has the same number of transistors and internal wires as the 22-AOI implementation 580 and it offers one "true” data input and one "inverted” data input.
  • The is particularly useful given that the ALU design discussed above outputs alternating "true” and “complement” index bits which then are fed to the 8x 2:1 MASK multiplexor 514.
  • This multiplexor design allows the use of either the "true” or “complement” multiplexor input to convert all the index bits to the same polarity.
  • this circuit can now also be used to implement the XOR-NOR module, ALU module 556, required for the ALU implementation as discussed above.
  • ALU module 556 required for the ALU implementation as discussed above.
  • NAND-21-OAI NAND-21-OAI
  • NOR-21-AOI module, MUX module 591 implementation of the multiplexor selects the non-inverting path when the select input is low and the inverting path when the select input is high. It is also desirable to have a multiplexor implementation that reverses this select sequence. This allows two multiplexors sharing the same select input to simultaneously invert the input data in one multiplexor and to retain the data polarity in the other multiplexor. This may be accomplished by transforming the design 591 to a NAND-21- OAI module, MUX module 596, as shown in Figure 51.
  • the resulting circuit 596 reverses the selection of the inverting and non-inverting inputs. Furthermore, if the two data inputs to this multiplexor circuit are tied together and the NAND output is pulled out, this circuit can now also be used to implement the XNOR- NAND module, ALU module 552, required for the ALU implementation as discussed above. Now two primitives can satisfy the requirements for both the ALU and the IMask/IScale MUXes.
  • the design of the ALU/MUX portion of the control slice is complete as shown in Figure 6.
  • the ALU 602 and 604 for even and odd index bits of the control slice is chosen per the rules given above with respect to the ALU Programming in the Table - ALU "Bit” Programming.
  • the "even” ALU bit outputs are "true” while the “odd” ALU bit outputs are "inverted”. This prompts the use of the NOR-21-AOI module, MUX module 591, for the 8x 2:1 MASK multiplexor 514 in the even index bits and the NAND-21-OAI module, MUX module 596, for the 8x 2:1 MASK multiplexor 514 in the odd index bits.
  • the SCALE decoder 521 takes a 7-bit input for each index bit position, decodes it to determine a scale value, and if selected, passes it to the index bit. This selection is determined by the ISize bus which always uses a thermometer value, selecting 8x 2:1 MASK multiplexor 514 output in the lower bit positions and the SCALE decoder 521 output in the upper bit positions. A convenient consequence of this is that in these lower order bit positions, the value of the SCALE decoder 521 outputs and thus their inputs are irrelevant.
  • each of the MSB and LSB decoders 518 and 519, a MSB/LSB decoder include a 5-stage chain of NAND/NOR gates where the connections to the MaskSel bus and the gate types are determined by the physical address of the control slice.
  • the programming for the MSB decoder 518 is determined by the following rules: Table 2A - MSB Mask Decode Programming
  • the rules for the LSB decoder 519 are identical except that the NAND/NOR selections are reversed.
  • the nibble is the smallest unit that can be selected for masking. Individual bits in the nibble are selected for masking by bits 0, 1, 2, and 3 of the MaskSel bus. These bits are "inverted", so setting any combination of these bits "low” activates masking in the corresponding bits of the nibble of "slices".
  • the remaining bits of the MaskSelect bus are used to determine the "grouping" in which this nibble is repeated/expanded (byte, doublet, etc) and to enforce masking on one side of this "group” and to prevent masking on the other side of this "group”.
  • Masking is forced on the MSB (Most Significant Bit) side of the "group” in the MSB decoder 518 and on the LSB (Least Significant Bit) side of the "group” in the LSB decoder 519.
  • the rules for programming this grouping are as follows:
  • bits 6,7,10, and 11 of the MaskSel bus are "true” while the remaining bits are “inverted”.
  • the schematics use two separate busses, one "true” and one "inverted", to carry these bits. This is done only as a convenience in the schematics since the schematic editor does not allow mixing of signal names in a bus.
  • the layout combines the used signals in one single bus.
  • the outputs of the MSB/LSB decoders 518 and 519 go to three sets of multiplexors IMsk 522, IOff 523, & ISet 524 which in turn feed the 8x 2:1 MASK multiplexor 514, the Force_Off logic 525, and the Kill_Bit7 logic 526.
  • These multiplexors 522-524 are simple AND-OR multiplexors built with AOIs and inverters and or NAND gates.
  • the Kill Bit logic 526 combines the Kill Bit signals and the output of the ISet multiplexor 524 to override the state of index bits 6 and 7.
  • the logic 526 is implemented with AOI, inverter, and NAND gates.

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Abstract

La présente invention concerne un circuit crossbar (100) mettant en oeuvre un commutateur (115) équipant un processeur large bande. Le circuit crossbar (100) comprend notamment un circuit de commutation (115) incluant des circuits multiplexeurs en 2m.2n:1 (202-204). Chacun des circuits multiplexeurs en 2n:1 comporte une entrée d'indice de bit n unique, et une entrée d'invalidation. Une entrée source de 2n bits de large reçoit un indice de bit n sur l'entrée d'indice de bit n, un bit d'invalidation sur l'entrée d'invalidation, et le mot source d'entrée de 2n bits sur l'entrée source de 2n bits de large. Cette entrée source décode ensuite l'indice de bit n pour sélectionner et donner en sortie, comme bit de destination de sortie, un unique bit provenant du mot source d'entrée de 2n bits si la valeur logique du bit d'invalidation est basse. Le circuit crossbar (100) comprend également une antémémoire (110), une entrée d'indice antémémoire en 2m et un circuit de commande (105). L'antémémoire (110) comporte des entrées à chemin de données d'antémémoire en 2m. Pourvu d'une pluralité d'entrées de commande, le circuit de commande (105) y reçoit des informations se rapportant aux instructions partiellement décodées, puis, après avoir fourni un second jeu d'indices de bit n destinés au circuit de commutation (115), il fournit les bits d'invalidation destinés au circuit de commutation (115) du point de couplage logique du circuit de commande (105) avec le circuit de commutation (115) et l'antémémoire (110).
PCT/US2000/003566 1999-02-12 2000-02-11 Systeme et procede de mise en oeuvre de commutateur crossbar de processeur large bande WO2000048070A1 (fr)

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US09/382,402 US6295599B1 (en) 1995-08-16 1999-08-24 System and method for providing a wide operand architecture

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5794003A (en) * 1993-11-05 1998-08-11 Intergraph Corporation Instruction cache associative crossbar switch system
US5931944A (en) * 1997-12-23 1999-08-03 Intel Corporation Branch instruction handling in a self-timed marking system

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JPH04111127A (ja) * 1990-08-31 1992-04-13 Toshiba Corp 演算処理装置
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5794003A (en) * 1993-11-05 1998-08-11 Intergraph Corporation Instruction cache associative crossbar switch system
US5931944A (en) * 1997-12-23 1999-08-03 Intel Corporation Branch instruction handling in a self-timed marking system

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Title
See also references of EP1236090A4 *

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