WO2000028595A1 - Circuit integre a haute densite - Google Patents

Circuit integre a haute densite Download PDF

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Publication number
WO2000028595A1
WO2000028595A1 PCT/CN1999/000171 CN9900171W WO0028595A1 WO 2000028595 A1 WO2000028595 A1 WO 2000028595A1 CN 9900171 W CN9900171 W CN 9900171W WO 0028595 A1 WO0028595 A1 WO 0028595A1
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
layer
memory
density
density integrated
Prior art date
Application number
PCT/CN1999/000171
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English (en)
Chinese (zh)
Inventor
Shixi Zhang
Original Assignee
Shixi Zhang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shixi Zhang filed Critical Shixi Zhang
Priority to AU64589/99A priority Critical patent/AU6458999A/en
Publication of WO2000028595A1 publication Critical patent/WO2000028595A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout

Definitions

  • the present invention relates to the field of integrated circuits, and more particularly, to high-density integrated circuits. Background technique
  • VLSI has made brilliant achievements so far.
  • transistors with certain logic / memory / analog functions are fabricated on a semiconductor substrate. This means that these transistors are arranged in a two-dimensional space, namely on the plane of the semiconductor substrate. Therefore, for a certain chip area, the number of transistors is limited. Accordingly, the functions of the chip are also limited.
  • the functions of a system such as a PC (personal computer) can only be distributed on several chips.
  • / 0 (input / output) pins greatly limit the speed of data transmission between these chips (because the number of pins of a chip is limited). This brings many difficulties to the further development of the computer. For example, the increasing speed difference between the microprocessor and the memory makes it very difficult to further increase the speed of the computer.
  • a system-on-a-chip with system functions is proposed as a solution to these problems.
  • a good example is the integration of DRAM (Dynamic Random Access Memory) and a microprocessor on a single chip.
  • DRAM Dynamic Random Access Memory
  • microprocessor a microprocessor
  • the width of the internal bus is not as limited as the I I 0 pins, and its number can be unlimited. Therefore, in theory, the data transfer speed between DRAM and microprocessor can be fast. This is a good idea, but if the DRAM and microprocessor are still implemented according to the conventional integrated circuit manufacturing method, that is, if it is manufactured on a two-dimensional semiconductor substrate, it has several potential problems.
  • DRAM and microprocessor are distributed in two dimensions, DRAM can only be placed next to the microprocessor. In this way, the data transfer between the opposite sides of the DRAM and the microprocessor will be slow due to the distance.
  • the transistor density the number of transistors per unit area
  • DRAM and microprocessors are limited. Therefore, their functions are also limited.
  • a third potential problem is that this concept has not yet included non-volatile memory. Therefore, it needs to extract information from an external non-volatile memory chip or hard disk, which is not good for the performance of the chip. Disclosure of invention
  • An object of the present invention is to provide a high-density integrated circuit that is fast in operation, powerful in function, convenient in application, and can be manufactured through the existing technology.
  • the object of the present invention is achieved by a technical solution of distributing circuit elements in a three-dimensional space.
  • the high-density integrated circuit includes: a first integrated circuit layer including at least one first circuit element, the first circuit element being coupled to another circuit element on the first integrated circuit layer; including at least one second circuit A second integrated circuit layer of the element, the second circuit element being coupled to another circuit element on the second integrated circuit layer; a layer interposed between the first integrated circuit layer and the second integrated circuit layer An interlayer dielectric layer; at least one interlayer connection channel opening that passes through the interlayer dielectric layer and couples the first integrated circuit layer and the second integrated circuit layer.
  • the integrated circuit layers of the present invention overlap each other and are stacked on top of each other.
  • Each integrated circuit layer has certain independent logic, memory, and / or analog functions, that is, each integrated circuit layer contains circuit function blocks such as logic blocks, memory blocks, and / or analog blocks.
  • interlayer connection channel holes function as data transmission lines. Because the interlayer connection channel holes are inside the chip, its number is not limited. Therefore, the bandwidth of data transmission is not limited.
  • the transistors are arranged in a three-dimensional space, the functions of the chip can be greatly improved.
  • one integrated circuit layer can provide a microprocessor and some non-volatile memory functions, and another integrated circuit layer can be used as a RAM function.
  • Thin-film transistor technology was originally developed in the liquid crystal display industry. The transistor is fabricated on a glass substrate. There is no substantial difference between the fabrication of a transistor on a glass substrate and a semiconductor substrate. Thin film transistors in the liquid crystal display industry can be similarly applied to the semiconductor industry. Unlike ordinary integrated circuits, a thin film transistor manufactures a transistor on a semiconductor thin film, and does not need to be on a semiconductor substrate. Therefore, different thin film transistor integrated circuit layers can be overlapped with each other to form a high-density integrated circuit. A thin film transistor integrated circuit layer can independently perform certain logic, memory, and / or simulation functions.
  • the lower thin film transistor integrated circuit layer must provide a good foundation for the upper integrated circuit layer.
  • chemical mechanical polishing this task can be easily accomplished.
  • An insulating medium is deposited on the integrated circuit layer of the thin film transistor and fills the gaps therein, and then the surface is flattened using a chemical mechanical polishing process. Therefore, another thin film transistor integrated circuit layer can be easily formed thereon. Repeat these steps to make a high-density integrated circuit.
  • the invention has the advantages of small size, strong function, good performance, fast calculation, convenient application, and can be manufactured by using the existing technology. With the present invention, the realization of a single-chip system (System-on-a-chip) is possible.
  • the present invention further improves the high-density integrated circuit containing a memory.
  • FIG. 1 is a schematic sectional view of a structure of Embodiment 1.
  • FIG. 1 is a schematic sectional view of a structure of Embodiment 1.
  • Fig. 2 is a schematic sectional view of a structure of the second embodiment.
  • Figure 3 is a perspective view of a high-density integrated circuit containing a three-dimensional memory. It contains one substrate integrated circuit layer (SUIC) and two layers above the substrate integrated circuit layer (ASIL). Both ASIL layers contain memory.
  • SUIC substrate integrated circuit layer
  • ASIL substrate integrated circuit layer
  • Figure 4 is a perspective view of a high-density integrated circuit with wiring channels.
  • Figures 5A, 5B, 5C, and 5D are plan views of metal wiring on different ASIL layers.
  • FIG. 6 is a perspective block diagram of a high density integrated circuit.
  • the ASIL 100 contains a read memory (ROM), and the SUIC 000 contains a cache memory associated with the ROM.
  • ROM read memory
  • SUIC 000 contains a cache memory associated with the ROM.
  • FIG. 7 is a perspective block diagram of a high density integrated circuit.
  • the ASIL 100 contains a thin-film transistor memory, and the SUIC 000 contains a cache memory associated with the memory.
  • FIG 8 is a block diagram of another high-density integrated circuit.
  • the ASIL 100 contains a mask programmable read-only memory (MPR0M), and the SUIC 000 contains an array of redundant electrically-programmable read-only memory (EPR0M) associated with the MPR0M.
  • MPR0M mask programmable read-only memory
  • EPR0M redundant electrically-programmable read-only memory
  • Figure 1 shows a cross-sectional view of a high-density integrated circuit with one substrate integrated circuit layer (SUIC 000) and two higher than the substrate integrated circuit layers (ASIL 100 and 200).
  • SUIC 000 substrate integrated circuit layer
  • ASIL 100 and 200 substrate integrated circuit layers
  • the structure of SUIC 000 is the same as that of a standard integrated circuit. It includes active components, such as MOSFETs 99a, 99b, and so on. These FETs 99a, 99b ... are built on a semiconductor substrate 10 and include a gate electrode 1, a gate insulating layer 2, and a drain / source 3.
  • a field effect tube (MOS) is used as an example. Triodes and other forms of active components can also be used.
  • the substrate field 4 isolates the transistors from each other on the substrate 10.
  • the transistors are connected together through a channel hole 6 and a metal wiring 7.
  • metal wiring 7 For clarity, only one layer of metal wiring 7 is drawn here.
  • the metal wire 7 on SUIC 000 can be multilayered like a standard integrated circuit.
  • SUIC 000 can also contain passive components such as resistors, Inductance, etc. Therefore SUIC 000 can have logic, memory and / or simulation functions.
  • SUIC 000 is covered by an interlayer dielectric film 20, which fills the gaps between the metal wirings on SUIC 000.
  • a subsequent dielectric planarization process step planarizes the interlayer dielectric film 20. In this way, a flat dielectric surface is prepared for ASIL 100.
  • ASIC 100 contains active components, such as thin film transistors 199a, 19%, and so on.
  • the thin film transistors 199a and 199b are fabricated on a thin semiconductor film 110, which has a gate electrode 101, a gate insulating layer 102, and a drain / source 103.
  • the semiconductor film 110 may use a semiconductor material such as silicon, germanium, and gallium arsenide. This semiconductor film 110 may be amorphous, polycrystalline, or single crystal.
  • the thin film transistors are isolated from each other by a field 104. In this embodiment, the semiconductor film 110 and the field 104 have the same thickness. In practice, the thickness of the semiconductor film 110 may be greater than the thickness of the field 104.
  • the structures of the thin film transistors 199a, 199b and the transistors 99a, 99b, ... on the substrate are similar.
  • the specific process of manufacturing thin film transistors can be found in many references, such as the invention "Transistor and Manufacturing Method” with publication number CN 1108004A and publication date September 6, 1995.
  • active components such as transistors and / or passive components such as resistors and inductors on this layer of ASIL 100.
  • ASIL 100 thin film transistors are coupled to each other through a via hole 106 and a metal wiring 107.
  • metal wiring in ASIL 100 can have several layers. These mutually coupled thin film transistors can have some independent logic, memory, and I or analog functions. That is to say, even a layer of ASIL can have many functions. By extension, high-density integrated circuits composed of multilayer ASIL overlays have more functions.
  • Interlayer connection channel holes 190a0, 290a0, ... are formed in the interlayer dielectric 20.
  • Interlayer connection channel holes 190a0 provide coupling between ASIL 100 and SUIC 000. Therefore, integrated circuits on different layers can transfer data / instructions to each other. Because the inter-layer connection channel holes 190a0 and 290a0 are inside the high-density integrated circuit, they can be small in size and can be close together. Therefore, the bandwidth of data transmission between layers is large. In other words, high-density integrated circuits have very high operating speeds.
  • an interlayer insulating dielectric film 120 is formed thereon and planarized.
  • another ASIL 200 higher than the substrate integrated circuit layer can be formed on the insulating dielectric film.
  • ASIL 200 contains a semiconductor thin film 210, and thin film transistors 299a, 299b, ... are formed thereon. These thin film transistors 299a, 299b, ... also have a gate electrode 201, a gate insulating layer 202, and a drain / source 203, which are separated from each other by a field 204. At the same time, the thin film transistors 299a, 299b, ...
  • the via hole 290al is coupled to the metal line on the ASIL 100 through the interlayer dielectric 120.
  • the interlayer connection channel holes 290al and 290a0 are collectively referred to as a contact channel hole 290a, which provides a coupling between the thin film transistor 299c on the ASIL 200 and the substrate 10. Repeat the above steps to form more layers of high-density integrated circuits.
  • Figure 2 provides another embodiment of a high density integrated circuit.
  • This embodiment is different from the previous Figure 1 in that the thin film transistor structure on the ASIL 200 is different.
  • the structures of the thin film transistors 299a, 299b, 299c, etc. are reversed, and its gate electrode 201 is under the drain I source 203 and the gate insulating layer 202.
  • This inverted thin film transistor structure is very common in the liquid crystal display industry.
  • a method of manufacturing such an inverted (inverted) thin-film transistor refer to the invention "Transistor and Manufacturing Method" with publication number CN 1108004A and publication date of September 6, 1995.
  • Another different place of this embodiment is that thin film transistors 299a ... can be formed over the via hole 206a and the metal wiring 207a of the ASIL 200. This structure can bring more convenience to the design of integrated circuits.
  • Figure 3 is a perspective view of a high-density integrated circuit containing a three-dimensional memory. It contains one substrate integrated circuit layer (SUIC) and two layers above the substrate integrated circuit layer (ASIL), both of which contain memory. Similar to Figures 1 and 2, SUIC 000 contains transistors and metal wiring that couples them to each other. In order to simplify the drawing, only one plane is used here to represent the substrate integrated circuit layer SUIC 000.
  • ASIL 200 contains memory cells 296aa 296ab ... and word lines 292a ... and bit lines 293a ... associated with them. Here, the arrangement of memory cells and word / bit lines is similar to that of a standard integrated circuit.
  • the memory cells 296aa, 296ab ⁇ may be random access memory cells (RAM) or non-volatile memory cells. It can contain active or / and passive components.
  • RAM random access memory cells
  • the structure and process of the memory cell can be found in many reference books, such as Qi Qi and others, "Principle of Microcomputer Composition" P. 193 ⁇ 199, which will not be repeated here.
  • the contact via holes 290a ... form an electrical connection between the word lines 292a ... and the substrate 10.
  • ASIL 100 contains memory cells 196aa, 196ab ... and corresponding word lines 192a ... and bit lines 193a ....
  • the arrangement of memory cells and word / bit lines is similar to standard integrated circuits.
  • the contact via holes 190a ... form an electrical connection between the word lines 192a ... and the substrate 10.
  • the memory layer may be not only two layers, but also multiple layers. Obviously, such a high-density integrated circuit that places the memory in a three-dimensional space, that is, a three-dimensional memory, can greatly increase the memory capacity.
  • Figure 4 shows a perspective view of a high-density integrated circuit metal wiring.
  • the metal wires 293a ⁇ 293h and their respective contact channel holes 290a ⁇ 290h are composed of two sub-zones, zone A: metal wires 293a ⁇ 293d and contact channel holes 290a ⁇ 290d; zone B: metal wires 293e ⁇ 293h And contact channel holes 290e ⁇ 290h.
  • the metal wires 293a to 293h are bent and extended on the ASIL 200 so that the planes formed by the contact channel holes 290a to 290d and 290e to 290h are parallel to each other, and there is a gap therebetween. This gap is called a wiring path 170a, 170b, so that the metal wires 175a to 175d under the ASIL 200 can pass through. This can be seen more clearly in Figures 5C and 5D.
  • the metal wires 293a to 293h on the ASIL 200 are straight lines and are not bent. Their respective ASIL contact points 294a2 ⁇ 294h2 form a straight line. This allows very little space for the metal wires under the ASIL 200 to pass through the plane formed by the contact channel holes 290a ⁇ 290h. Therefore, it is very likely that the metal wires 193a to 193h on the ASIL 100 must end before they reach the contact channel holes 290a to 290h. This may limit data transfer between layers.
  • the metal wires 293a to 293h are bent and extended, so their ASIL contact points 294a to 294d and 294e to 294h form two planes.
  • the distance between the planes is much larger than the width of the metal lines. Therefore, the metal wires 175a to 175d on the ASIL 100 can pass through unobstructed. Accordingly, the performance of the integrated circuit is improved.
  • the pitches of the contact channel holes 290a to 290h in FIG. 5A and FIG. The distance between the contact channel holes 290a to 290d and 290e to 290h in 5D can be arbitrarily adjusted. Therefore, the circuit design of FIGS. 5C and 5D is simpler.
  • FIG. 6 is a perspective block diagram of a high density integrated circuit.
  • the ASIL 100 contains a read-only memory (ROM), and the SUIC 000 contains a cache memory associated with the ROM.
  • the read-only memory (ROM) array on ASIL 100 includes word lines 193a, 193b ..., bit lines 192a, 192b ..., and read-only memory cells 196aa, 196ab ...
  • the read-only memory cell can have some simple structures, such as using a non-linear resistor as a read-only memory cell. In this embodiment, there are no active components on the ASIL 100, so its manufacturing process is relatively simple.
  • Sense amplifier 61a ⁇ on substrate 61 j which converts electrical signals from the ROM array into digital signals.
  • the sense amplifiers 61a to 61j are examples of analog blocks.
  • the substrate 10 further includes transfer control gates 51a to 51j and a cache memory 90. They act as a buffer for the ROM array.
  • the transmission control gates 51 a to 51 j are controlled by a control signal 50. When it allows transmission, the digital information latched on the sense amplifiers 61a to 61j is simultaneously transferred to the cache memory 90.
  • the cache memory 90 has memory cells 96aa, 96ab ..., and their associated word / bit lines 92a, 92b ..., 93a, 93b ....
  • the other parts of the high-density integrated circuit chip, such as the microprocessor 80, can read the information in the cache memory 90 through the address decoder 70.
  • the microprocessor 80 and the address decoder 70 are some examples of logical blocks. Since the contact channel openings 190a to 190j serving as a tie between the cache memory 90 and the ROM array are inside the chip, its number can be unlimited. In other words, the data transfer speed between the ROM array and the cache memory can be fast.
  • the cache memory may be a random access memory or another high-speed memory.
  • information from multiple memory cells on a word line in the ROM is transferred to the cache at the same time.
  • FIG. 7 is a perspective block diagram of a high density integrated circuit.
  • the ASIL 100 contains a thin-film transistor memory, and the SUIC 000 contains a cache memory associated with the memory. Because ASIL 100 contains active components, sense amplifiers 161a ... (analog blocks), address decoders 171 (logic blocks), and other circuits can be generated on them. They transfer data between the contact channel openings 190a ⁇ 190j and SUIC 000. Similarly, SUIC 000 may contain a cache 90 and a microprocessor 80. Since the number of contact channel openings 190a to 190j is not limited, the high-density integrated circuit using this embodiment can have a fast speed.
  • FIGS. 6 and 7 are only used as two examples to explain the method of using the cache as a buffer. In fact, the methods used as buffers in the prior art can be applied to high-density integrated circuits.
  • FIG. 8 is a block diagram of another high-density integrated circuit.
  • the ASIL 100 contains a mask-programmable read-only memory (MPROM), and the SUIC 000 contains an excess electrically-programmable read-only memory (EPR0M) array associated with the MPR0M.
  • EPR0M electrically-programmable read-only memory
  • any kind of electrically-programmable memory can be used as the redundant array.
  • MPR0M mask programming read-only memory
  • MPR0M mask programming read-only memory
  • EPR0M on line 94 of 87.
  • the row address of defective row 198 in MPR0M 197 is stored in EPR0M array 85 as a label.
  • EPR0M allows us to write the information of the redundant array after the chip test.
  • the row address 81 is first compared in the comparator 84 and each tag in the EPR0M array 85. If there is a same situation, the control signal 83 will tell the multiplexer 91 to select the output 93 of the EPR0M 87 as the output (Dout) 94. If it is not the same, the control signal 83 will select the appropriate line in MPR0M 197 and output 92 as the memory output 94.
  • any redundant array method in standard integrated circuits can be used in high-density integrated circuits. For example, any memory that can be rewritten by the user can be used as a redundant array.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un circuit intégré à haute densité comprenant une pluralité de couches intégrées dans une puce dans le sens vertical. Chaque couche présente une mémoire indépendante et des fonctions logiques et/ou analogiques. Dans ces couches sont ménagés une pluralité de trous d'interconnexions permettant de connecter ces différentes couches. L'invention concerne également un circuit intégré à haute densité amélioré comprenant une mémoire et une zone divisée par un câblage. On peut améliorer la vitesse opérationnelle en ajoutant une mémoire tampon et on peut améliorer la production en apportant un réseau mémoire à champ programmable faisant office de réseau redondant.
PCT/CN1999/000171 1998-11-09 1999-10-28 Circuit integre a haute densite WO2000028595A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU64589/99A AU6458999A (en) 1998-11-09 1999-10-28 High density integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN98121834.2 1998-11-09
CN98121834 1998-11-09

Publications (1)

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WO2000028595A1 true WO2000028595A1 (fr) 2000-05-18

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WO (1) WO2000028595A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1253652A2 (fr) 2001-03-29 2002-10-30 Kabushiki Kaisha Toshiba Mémoire à semiconducteur comprenant une cellule de mémoire et un circuit périphérique

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453952A (en) * 1991-04-23 1995-09-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having peripheral circuit formed of TFT (thin film transistor)
US5675185A (en) * 1995-09-29 1997-10-07 International Business Machines Corporation Semiconductor structure incorporating thin film transistors with undoped cap oxide layers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453952A (en) * 1991-04-23 1995-09-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having peripheral circuit formed of TFT (thin film transistor)
US5675185A (en) * 1995-09-29 1997-10-07 International Business Machines Corporation Semiconductor structure incorporating thin film transistors with undoped cap oxide layers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1253652A2 (fr) 2001-03-29 2002-10-30 Kabushiki Kaisha Toshiba Mémoire à semiconducteur comprenant une cellule de mémoire et un circuit périphérique
EP1253652A3 (fr) * 2001-03-29 2007-06-20 Kabushiki Kaisha Toshiba Mémoire à semiconducteur comprenant une cellule de mémoire et un circuit périphérique

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