Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T15/00—3D [Three Dimensional] image rendering
  • G06T15/005—General purpose rendering architectures

Definitions

• This invention relates to apparatus for the processing of images.
• the invention is particularly, though not exclusively, suitable for use in systems for the real-time rendering, texturing or shading of three-dimensional (3D) images.
• Real-time here means sufficiently quickly for the image to be displayed without appreciable perceptible delay to the viewer.
• the best known existing system for generating realtime 3D images is the Z-buffer (or depth buffer) image precision algorithm.
• the Z-buffer algorithm requires a frame buffer in which color values are stored for each pixel (elementary picture element) in an image. In addition to this it requires a Z-buffer with an entry for each pixel. In this Z-buffer, a Z value or depth value is stored for each pixel.
• polygons are rendered into the frame buffer in arbitrary order. As a subsequent polygon is entered into the frame buffer, if a point on the polygon is nearer to the viewer than the point already in the frame buffer for that pixel, then the new point's color and Z value replace the previously-stored values.
• the texturing or shading is applied to the polygon before it is rendered into the frame buffer.
• the system is fed with a list of vertices which define the polygons, and texture and shading operations are performed on each polygon before a depth test is executed.
• the performance of such systems is limited by various factors, including the input data bandwidth, the speed of texturing and shading, and the local memory interface bandwidth. It has been proposed to improve the system performance by the use of dual rendering devices, which are 'scan line interleaved'.
• the system can determine whether any surface is visible. If it is visible, that surface is then textured or shaded as desired. However if it is not visible, texturing and shading of the surface is not necessary.
• One advantage of this system over the Z-buffer is that non-visible surfaces do not have to be textured or shaded. Texturing or shading of images requires a great deal of processing power. The reduction in processing achieved by the system of the above-mentioned United States Patent is therefore very useful, and can be quite dramatic with certain types of image, particularly those having many overlapping polygons or surfaces.
• each surface is defined as being a forward surface, if it is at the front of the object and thus faces towards the observer, or a reverse surface if it forms part of the back of the object and thus faces away from the observer.
• a comparison is made of the distances from the observation point to (a) the forward surface intersection with the ray which is furthest from the observation point and (b) the reverse surface intersection with the ray which is closest to the observation point.
• the technique makes it particularly easy to apply shadows to appropriate parts of the image.
• the system is also able to deal with transparency which can take various forms.
• the technique has advantages over the Z-buffer system, but nevertheless processing requirements can still be a constraint. It is proposed in the Patent to improve performance by subdividing the image plane or screen into a plurality of sub-regions or 'tiles'.
• the tiles are conveniently rectangular (including square) .
• those objects having surfaces which could fall within the tile are first determined, and only those objects within the tile are processed, thus decreasing the number of surfaces to be processed.
• the determination of which objects could contribute to each tile may be achieved by surrounding the object with a bounding volume, namely a cuboid which fully contains the object, and comparing the tile area with the bounding volume. To do this, all the bounding volumes are projected onto the image plane and are tested against the corners of the tiles.
• this preferred embodiment of the invention takes the form of image processing apparatus for rendering (i.e. coloring, texturing or shading) an image includes a tiling device which divides the image into sub-regions or tiles. Two rendering devices are provided, and the tiles are allocated so that some are processed by one rendering device and some by the other. Polygons representing surfaces of objects to be displayed are tested against the tiles. If the surface falls into one sub-region only, the data is sent to one rendering device only. On the other hand, if the surface falls into two sub-regions being handled by the different rendering devices, then the data is sent to both rendering devices. The result is that a substantial proportion of the data need only be supplied to and processed by one rendering device, thereby speeding the operation of the apparatus. The outputs of the two rendering devices are subsequently combined by tile interleaving and image display circuitry.
• Figure 1 illustrates an portion of an image plane containing several objects and having tiles of variable sizes, taken from U.S. Patent 5,729,672,
• Figure 2 illustrates a portion of the screen containing tiles m accordance with an embodiment of the present invention
• Figure 3 is a diagram showing a bounding box around an object
• Figure 4 is a flow chart of the procedure used to determine the co-ordinates of a bounding box around an object
• Figure 5 illustrates a portion of the screen containing tiles in a modification of the embodiment of Figure 1; and Figure 6 is a block schematic diagram of hardware used in preferred image processing apparatus embodying the invention .
• FIG. 2 there is shown a portion 20 of a screen which contains twelve sub-regions or tiles 22 as shown.
• Each tile is typically 32 pixels or 64 pixels square, that is, using a conventional raster scan, 32 or 64 pixels long by 32 or 64 lines high.
• two objects are diagrammatically shown on this Figure, namely a house 24 and a bicycle 26. Each of these objects extends, for the sake of illustration, over two of the tiles 22. In the case of the house 24 these are one above the other in the image, and in the case of the bicycle they are side by side. Either way the operation is the same.
• the tiles are divided into two groups of tiles. As shown, the tiles are split into two groups in checkerboard fashion. As shown in Figure 2, alternate tiles are shaded light or dark on the figure, with each light tile 22A being surrounded by four dark tiles and each dark tile 22B being surrounded by four light tiles. The light and dark tiles thus form diagonals across the screen.
• the rendering of the objects is split between two processors which may be referred to as processor A and processor B.
• processor A and processor B Each group of tiles is associated with a respective one of the processors A and B. That is, all the light tiles 22A are associated with processor A and all the dark tiles 22B, as shown in Figure 2, are associated with processor B. All the processing of surfaces which are seen in a light tile is undertaken by processor A and all the processing of surfaces which are seen in a dark tile is undertaken by processor B.
• Complex objects can be seen to be made up of a group of several smaller polygons.
• the house 24 is made up of a triangle for the roof 28, a triangle and a square for the chimney 30, and rectangles for the main body 32 of the house, the windows 34, and the door 36.
• Those polygons which make up the roof 28, the chimney 30, and the upstairs one of the windows 34 lie entirely within a light tile 22A, and so need only be sent to processor or device A.
• the door 36 and the downstairs window 34 lie entirely within a dark tile 22B, and so need only be sent to processor or device B.
• the mam body 32 of the house overlaps two tiles. Accordingly it must be sent to both processors or devices as it affects the display m both a light tile and a dark tile.
• the polygons which make up the front wheel, the front forks and the handlebars are sent to device A only; the rear wheel, the rear forks and the saddle are sent to device B only; while the frame of the bicycle is sent to both devices. Larger objects may extend over three or more tiles, but the processing applied and its effects are the same as with objects that overlap just two tiles.
• each of the polygons which make up the complex object can be achieved by drawing a rectangle to enclose the entire polygon, and then testing the rectangle against the co-ordinates of the tiles of the screen to determine the extent of the polygon.
• This is illustrated m Figure 3, which shows an arbitrary polygon 4C.
• This polygon is shown as a re-entrant polygon and may conveniently be broken into non-re-entrant polygons for processing, if desired, but the principle of establishing the bounding box is the same.
• Polygon data is supplied to the rendering device by giving the co-ordinates of each vertex of the polygon. The co-ordinates are given in a Cartesian system which has three orthogonal axes, X, Y and Z.
• the final display screen is assumed to be in the plane of the X-Y axes, while the Z axis represents the depth of the object, as is conventional.
• the procedure used to determine the minimum values of x and y which define the corners 44 of the bounding box 42 is illustrated m Figure 4.
• a first step 52 the input values x._, y._ for the first vertex processed are initially assumed to be the desired values x m _, x_, ⁇ , y mil , y-, a • Tne next vertex is then processed in step 54.
• the new input values x ⁇ n , y ⁇ r are compared with the stored values for x ⁇ ._, x max , y m r , yêt x . If for either x or y the new input value is less than the stored minimum value then it replaces the minimum value, and if the new input value exceeds the maximum value it replaces "the maximum value.
• step 56 a check is made to see whether the last vertex defining the polygon has been processed. If not, the procedure returns to step 54 to process the next vertex. If it has, then the co-ordinates of the bounding box 42 have now been determined, and the procedure moves to step 58 where a determination is made to see whether the bounding box overlaps the screen tile which is being processed. This determination also is made by simple comparison of the XY co-ordinates of the corners 44 of the bounding box 42 with the XY co-ordinates of the corners of the tile.
• the tile size in terms of the number of pixels is preferably chosen to be a power of two, e.g. 32 or 64, which has the consequence that the screen tile test 58 reduces to a number of simple binary comparisons.
• FIG. 5 illustrates a form of division in which a large rectangle 2 contains a small rectangle 1 of shorter height and width.
• the device B is arranged to process the tiles forming the smaller rectangle 1, and the processor A is arranged to process what is left, that is rectangle 2 with rectangle 1 excluded.
• Rectangle 1 is thus defined for processor A as an inclusion rectangle and rectangle 2 as an exclusion rectangle. That is, all polygons entirely enclosed in rectangle 1 are sent to device A. Polygons outside rectangle 1 but inside rectangle 2 are sent to device B. Polygons which overlap the two areas are sent to both devices.
• the division of the screen is such that a substantial number of surfaces have to be sent only to one processor.
• the tiles are preferentially substantially square with, say, one side not more than twice or three times the length m pixels of the other, so that there is a reasonable HKelihood that a good proportion of the surfaces will fall only in one tile. In this way the processing is reduced by some surfaces having to be sent to one processor only.
• a split in which alternate scan-lines were processed by different processors would not provide any advantage because the number of surfaces which fall only on one scanlme is zero, or close to it.
• Another possible split would be in horizontal bands across the screen, but the bands would have to be sufficiently wide, e.g. the screen as a whole might be split into three or four bands.
• the tile aspect ratio is less than six to one. In any event, there will normally be at least three screen areas, with at least one of the processors being arranged to process at least two discrete separate image areas.
• Figure 6 shows in block schematic form image processing apparatus 60 embodying the invention and comprising a central processing unit (CPU) 62 connected to a main memory 64.
• a tiling device 66 defines the tiles and communicates with a local memory 68 as well as with the CPU 62.
• the tiling device effectively has two outputs to which are attached a first texturing or rendering device 70A and a second texturing or rendering device 70B.
• the outputs of the two rendering devices 68A and 68B are both applied to tile interleaving and image display circuitry 72.
• Objects are generated by the user (programmer) . They are defined by their vertices, and by texture codes which indicate the type of texturing required for each surface. This will include the color and other surface effects.
• a bounding box is generated for each surface, following the method described above.
• the bounding box is compared against the macro tiling pattern being employed, so as to determine which surfaces fall into which tiles, and hence which of the multiple rendering devices (two in this case) require the data.
• Surface vertices and texture codes are then stored in the appropriate local memory portion associated with each memory device.
• step 7 for some tiles is achieved by one processor and the same step for the other (dark) tiles is achieved by the other processor. This reduces the time required for processing by a factor less than but approaching a half.
• the outputs of the two processors are combined for application to the display buffer and subsequent display on the display screen.
• the system operates by supplying data defining a group of surfaces representing an object, e.g. the house or the bicycle in Figure 2.
• the display is subdivided into a large number of tiles, and a determination is made as to which surfaces fall into which tiles.
• the data is then applied to the two rendering devices in dependence upon which tile the various surfaces fall into.
• the data of some surfaces will be sent to one rendering device only and the data of other surfaces will be sent to both rendering devices. More particularly, when the surface falls into one tile only, e.g. the roof or the door in Figure 2, the data need only be sent to one rendering or texturing device.
• the surface data must be sent to both rendering devices .
• the invention is not limited to the use of two devices; more than two may be used if desired, in which case the screen is split up into an appropriate larger number of regions each comprising a respective group of tiles .
• the embodiments illustrated have the advantage that, assuming normal images are being processed, the processing time is reduced, due to the fact that the processors can operate simultaneously in parallel, each processor needing to process only some of the surfaces and not all the surfaces in the image.

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• 1998
  • 1998-11-06 GB GB9824406A patent/GB2343598B/en not_active Expired - Lifetime
• 1999
  • 1999-11-08 EP EP19990954179 patent/EP1125250B1/en not_active Revoked
  • 1999-11-08 DE DE69914355T patent/DE69914355T2/de not_active Expired - Lifetime
  • 1999-11-08 WO PCT/GB1999/003716 patent/WO2000028477A1/en not_active Ceased
  • 1999-11-08 AT AT99954179T patent/ATE258327T1/de not_active IP Right Cessation
  • 1999-11-08 US US09/831,386 patent/US6750867B1/en not_active Expired - Lifetime
  • 1999-11-08 JP JP2000581592A patent/JP4480895B2/ja not_active Expired - Lifetime

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