WO2000026793A1 - Systeme et procede permettant d'acceder a des donnees situees dans une memoire externe a l'aide de protocoles doubles de minutage de lecture - Google Patents

Systeme et procede permettant d'acceder a des donnees situees dans une memoire externe a l'aide de protocoles doubles de minutage de lecture Download PDF

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Publication number
WO2000026793A1
WO2000026793A1 PCT/US1999/023802 US9923802W WO0026793A1 WO 2000026793 A1 WO2000026793 A1 WO 2000026793A1 US 9923802 W US9923802 W US 9923802W WO 0026793 A1 WO0026793 A1 WO 0026793A1
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WO
WIPO (PCT)
Prior art keywords
read
signal
cycle
microcontroller
duration
Prior art date
Application number
PCT/US1999/023802
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English (en)
Inventor
Maxence Aulas
Jacko Wilbrink
Original Assignee
Atmel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corporation filed Critical Atmel Corporation
Publication of WO2000026793A1 publication Critical patent/WO2000026793A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

  • This invention relates to a method for accessing memory in a microcontroller application. More" specifically, the invention involves a method for reading memory from an external memory device.
  • FIG. 4 illustrates a typical prior art method of reading data from an external memory.
  • a CLOCK signal 10 is input to the microcontroller to pace the operation of the system.
  • the CLOCK signal is typically generated by a crystal oscillator and each instruction executed by the microcontroller requires a fixed number of clock cycles as determined by the design of the microprocessor. Each bus cycle begins when the microcontroller outputs an address 20 to select one memory location or I/O port.
  • the address is decoded by an address decoder, which generates an address select signal for each device in the system. Every I/O port and memory location has a unique address, and the address decoder ensures that only one device is selected at a time. Because all devices typically share the same data bus, when a device's address is not present on the address bus, the device must be electrically removed from the data bus. This is accomplished by drivers which become enabled by the device's CHIP SELECT signal 30. After the microcontroller outputs the address, it asserts a READ signal 40 to indicate when the addressed device should read data from the external device memory and drive it on to the data bus. The typical READ pulse cycle is active during the latter half of a clock cycle.
  • a WRITE signal 50 may also be asserted to read data from the data bus and write it to a location in the device's memory. The actual data transfer occurs ' as the READ or WRITE signal is negated to allow as much time as possible for the addressed device to decode the address and prepare to perform the read or write operation.
  • the CHIP SELECT, READ and WRITE signals are defined as being active low signals.
  • the CHIP SELECT signal 30 is asserted.
  • the READ signal 40 is asserted and data is read from memory 42 and driven on to the data bus.
  • the READ signal 40 is negated and the WRITE signal 50 is asserted during the latter half of the next clock cycle 12 and data is written into the microcontroller 52 from the data bus.
  • the length of the READ cycle and WRITE cycle is preprogrammed into the microcontroller and is typically the length of one half of the clock cycle.
  • problems can occur when the microcontroller is attempting to read data from a slower external device memory during applications involving higher frequencies. For example, assume that a user wants to run an application at a high frequency such as 40 MHz, corresponding to a clock period, Tclock, of 25 ns.
  • the external memory has an access time of 15 ns, the access time being defined as the time from the falling edge of the READ signal to the time that the data read is valid.
  • Tclock clock period
  • the above objects have been met by a method and system of accessing data from an external device memory in a microcontroller application in which the width of the read enable pulse is selectable under program control.
  • the microcontroller application program can specify which type of read pulse to use to read out a memory location. Subsequent read operations will then assert the read enable signal for the specified length of time. This permits slow memory devices to be used in a fast clock environment.
  • the present invention allows a user to operate the microcontroller using the traditional read protocol, wherein the width of the read pulse is one half of a clock cycle, but the user can also reprogram the read protocol so that the width of the read pulse is one full clock cycle, such that there is more time for the data to be accessed. To avoid bus clashes in the latter application, a wait cycle is inserted after the write cycle in order to resynchronize the read cycle with the write cycle.
  • Figs. 1 and 2 are timing diagrams, showing the waveforms of various portions of a system incorporating the protocol of the present invention.
  • Fig. 3 is a circuit diagram of the logic circuit used to implement the present invention.
  • Fig. 4 is a timing diagram showing the waveforms of various portions of a system incorporating the prior art protocol.
  • a timing diagram showing the waveforms of various portions of the system incorporating the protocol of the present invention is shown.
  • the CLOCK signal 10 is input to the microcontroller in order to pace the operation of the system.
  • the CLOCK signal is typically generated by a crystal oscillator and each instruction executed by the microcontroller requires a fixed number of clock cycles as determined by the design of the microprocessor. As shown, each low pulse width followed by high pulse width constitutes one clock cycle.
  • the READ signal 40 can be asserted at the beginning of the clock cycle rather than in the middle of the clock cycle. This extends the length of the read signal to an entire clock cycle.
  • Each bus cycle begins when the microcontroller outputs an address 20 to select one memory location or I/O port.
  • the address is decoded by an address decoder which generates an address select signal for each device in the system. Every I/O port and memory location has a unique address, and the address decoder ensures that only one device is selected at a time. Because all devices typically share the same data bus, when an address of a device is not present on the address bus, the device must be electrically removed from the data bus. This is accomplished by drivers which become enabled by the devices CHIP SELECT signal 30. After the microcontroller outputs the address, it asserts a READ signal 40 to indicate when the addressed device should read data from the external device memory and drive it onto the data bus.
  • the READ signal 40 is asserted at the beginning of a clock cycle, which will be referred to as a read cycle 13.
  • the read signal 40 is inactive and a half of the next clock cycle elapses.
  • write cycle 14 the WRITE signal 50 is asserted to read data from the data bus and write it to a location in the device's memory.
  • a wait cycle 15 is implemented following the write cycle 14.
  • a CLOCK signal 10, the CHIP SELECT signal 30, the READ signal 40, and the WRITE signal 50 operate as described above in reference to Fig. 1.
  • the address bus 20 is shown to have many addresses, each address corresponding to a memory location in the microcontroller.
  • the data bus 25 contains various data instructions and values.
  • the EARLY READ PROTOCOL signal 60 is a signal that controls the width of the read pulse of the READ signal 40. When the EARLY READ PROTOCOL signal 60 is low, the width of the READ signal 40 is one half of a clock cycle, which is the standard prior art protocol. When the EARLY READ PROTOCOL signal 60 is activated and is high, than the width of the read pulse extends to one full clock cycle in order to allow the data to be read for a full clock cycle.
  • the activation of the EARLY READ PROTOCOL signal 60 is done through software instructions that are input into the data bus.
  • the EARLY READ PROTOCOL signal 60 is set in address 24 by the data signal 27 consisting of the data value 00000017.
  • the source code is given in ARM7TDMI assembler syntax.
  • the fourth bit at address 24 indicates the read protocol that the user wishes to use to run the application.
  • the fourth bit set low indicates that the standard protocol is used.
  • the fourth bit set high indicates that the early read protocol is to be used.
  • LDR rl 0 x 00000017 SDR rl, [ro,#&24] will write the hexadecimal value 17 into the register present at address 24. Converted to binary, the value 17 would be 00010111, and since the fourth bit is set high, it will indicate to the microcontroller to change the read protocol to the early read protocol. If later the source code:
  • NAND gate 87 The output of NAND gate 87 is input into a three input NAND gate 88.
  • the other inputs of NAND gate 88 are the WAIT- EXTREG signal and the output of NOR gate 91.
  • NOR gate 91 has an input of the CLOCK signal 10 and the EARLY READ
  • PROTOCOL signal 60 The N EXTERNAL WRITE signal and the ACKNOWLEDGE signal are supplied to NAND gate 86 and the NWE-from-PAD signal and the NB-WRITE-REG signal are input into NAND gate 85. The outputs of NAND gates 86 and 85 are supplied to NOR gate 89.
  • the clock signal 10 and the N CHANGE MEMORY signal are function inputs to a 2-by-l multiplexer 95.
  • the BRES signal is the select input to the 2-by-l multiplexer 95.
  • the CS-REG-7-REG signal is inverted by inverter 71 and then input to NAND gate 82.
  • the NWE-from-PAD signal is inverted through inverter 72 and then input into NAND gate 82.
  • the EXTERNAL SELECT signal and the N-WAIT-AFTER-WRITE signal are input into NAND gate 81, and the output of NAND gate 81 is inverted by inverter 75.
  • the output of NAND gate 82 and the output of inverter 75 are input into AND gate 83.
  • the output of the 2-by-l multiplexer 95 and the output of the AND gate 83 are input into NAND gate 84, and the output of NAND gate 84 is then inverted by inverter 76.
  • the outputs of NAND gate 88, NOR gate 89 and inverter 76 are supplied to a three input NAND gate 90.
  • the output of NAND gate 90 is inverted by inverter 77 to the output 99 ' of the circuit.
  • the output of the circuit is the READ signal 40.
  • the value of the EARLY READ PROTOCOL signal 60 that is input into the circuit will determine the pulse width of the READ signal 40, and will determine under which read protocol the microcontroller will operate.

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Abstract

Système et procédé permettant l'accès à des données situées dans une mémoire externe dans une application de microcontrôleur dans laquelle la largeur de l'impulsion (40) de validation de lecture peut être choisie par commande de programme si bien qu'un protocole double d'application peut être mis en oeuvre. Le programme d'application de microcontrôleur peut spécifier quel type de fonctionnement d'impulsions (40) de lecture utiliser pour lire un emplacement de mémoire. Les opérations de lecture subséquentes reposeront ensuite sur le signal de validation de lecture pour le laps de temps spécifié. La présente invention permet à l'utilisateur de faire fonctionner le microcontrôleur à l'aide du protocole de lecture classique utilisé dans l'art antérieur, et lui donne la possibilité de modifier la largeur de l'impulsion de lecture pour que plus de temps soit consacré à l'accès à des données. Cela permet d'utiliser des dispositifs à mémoire lente dans un environnement à horloge rapide.
PCT/US1999/023802 1998-10-30 1999-10-13 Systeme et procede permettant d'acceder a des donnees situees dans une memoire externe a l'aide de protocoles doubles de minutage de lecture WO2000026793A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18361798A 1998-10-30 1998-10-30
US09/183,617 1998-10-30

Publications (1)

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WO2000026793A1 true WO2000026793A1 (fr) 2000-05-11

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PCT/US1999/023802 WO2000026793A1 (fr) 1998-10-30 1999-10-13 Systeme et procede permettant d'acceder a des donnees situees dans une memoire externe a l'aide de protocoles doubles de minutage de lecture

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753232A (en) * 1972-04-06 1973-08-14 Honeywell Inf Systems Memory control system adaptive to different access and cycle times
US5033001A (en) * 1986-12-19 1991-07-16 Fujitsu Limited Dual mode memory read cycle time reduction system which generates read data clock signals from shifted and synchronized trigger signals
US5276856A (en) * 1989-09-28 1994-01-04 Pixel Semiconductor, Inc. Memory controller flexible timing control system and method
US5394541A (en) * 1990-07-17 1995-02-28 Sun Microsystems, Inc. Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signals
US5463756A (en) * 1989-11-06 1995-10-31 Mitsubishi Denki Kabushiki Kaisha Memory control unit and associated method for changing the number of wait states using both fixed and variable delay times based upon memory characteristics
US5530944A (en) * 1991-02-27 1996-06-25 Vlsi Technology, Inc. Intelligent programmable dram interface timing controller
US5615358A (en) * 1992-05-28 1997-03-25 Texas Instruments Incorporated Time skewing arrangement for operating memory in synchronism with a data processor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753232A (en) * 1972-04-06 1973-08-14 Honeywell Inf Systems Memory control system adaptive to different access and cycle times
US5033001A (en) * 1986-12-19 1991-07-16 Fujitsu Limited Dual mode memory read cycle time reduction system which generates read data clock signals from shifted and synchronized trigger signals
US5276856A (en) * 1989-09-28 1994-01-04 Pixel Semiconductor, Inc. Memory controller flexible timing control system and method
US5463756A (en) * 1989-11-06 1995-10-31 Mitsubishi Denki Kabushiki Kaisha Memory control unit and associated method for changing the number of wait states using both fixed and variable delay times based upon memory characteristics
US5394541A (en) * 1990-07-17 1995-02-28 Sun Microsystems, Inc. Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signals
US5530944A (en) * 1991-02-27 1996-06-25 Vlsi Technology, Inc. Intelligent programmable dram interface timing controller
US5615358A (en) * 1992-05-28 1997-03-25 Texas Instruments Incorporated Time skewing arrangement for operating memory in synchronism with a data processor

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