WO2000019574A1 - Circuit de declenchement de fixation de niveau de protection contre les decharges electrostatiques - Google Patents

Circuit de declenchement de fixation de niveau de protection contre les decharges electrostatiques Download PDF

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Publication number
WO2000019574A1
WO2000019574A1 PCT/US1999/019048 US9919048W WO0019574A1 WO 2000019574 A1 WO2000019574 A1 WO 2000019574A1 US 9919048 W US9919048 W US 9919048W WO 0019574 A1 WO0019574 A1 WO 0019574A1
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WO
WIPO (PCT)
Prior art keywords
circuit
control signal
voltage
gate
reference potential
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Application number
PCT/US1999/019048
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English (en)
Inventor
Xiaoming Li
Eugene R. Worley
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Conexant Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems, Inc. filed Critical Conexant Systems, Inc.
Publication of WO2000019574A1 publication Critical patent/WO2000019574A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Definitions

  • the present invention relates to Electro-Static Discharge (ESD) protection circuits for use with semiconductor based electronic circuits. More particularly, the present invention relates to an ESD protection triggering circuit that regulates its voltage potential such that an over-voltage condition will not occur.
  • ESD Electro-Static Discharge
  • BACKGROUND ARTAND TECHNICAL PROBLEMS ESD is a physical phenomenon which is well-known in the electronics industry and in general. Many persons have felt the electrical shock which may occur when one touches a metal surface such as a lamp, television, or the like after having walked in their socks across a deep shag carpet. While these discharges commonly range between 2,000 and 4,500 volts and are discharged over a few milliseconds, they appear to the victim as a harmless, but attention-getting, electrical shock. The human body provides a high resistance to the discharge of these significant volts, thereby decreasing the associated current.
  • the Human Body Model (HBM) standard assumes that the human body has a capacitance of 100 pf and a series resistance of 1500 Ohms.
  • ESD electrospray senor
  • the peak current flow during a human body ESD is generally on the order of amps.
  • ESD may also occur when charges accumulate upon an ungrounded surface.
  • a piece of equipment, electronic circuit, or the like which is not grounded may collect charges as it is moved from one location to another.
  • ESD may occur.
  • the electric current will follow the path of least resistance (often through vital electronic circuitry) to the conductor.
  • the conductor is often a prong of an integrated circuit chip.
  • such clamping devices are transparent during normal chip operations but shunt the high current of an ESD event. This is typically accomplished by using a device which is normally "off but has a turn on threshold which is well above a chip's normal operating voltage and is also below a voltage which may damage a chip's circuit elements. Since higher power dissipations by the clamp may result in an electro-thermal failure within a circuit, the threshold is often set as close as possible to the operating voltage of the circuit.
  • NFET Field Effect Transistor
  • Figure 1 A common method of creating such a clamp on CMOS integrated circuits is to use a grounded gate NMOS Field Effect Transistor (NFET) 100 as shown in Figure 1 (wherein the figure on the left is a cross section of NFET 100, and the figure on the right is a schematic diagram).
  • NFET 100 Normally, NFET 100 is in an "off" state.
  • the drain junction 111 will often avalanche and NFET 100 will start conducting. Due to the electrostatic effects of the gate 102, the avalanche conduction normally occurs near the surface of the silicon substrate 112 at the junction of the drain 111 and the substrate 112.
  • NFET 100 As shown in Figure 3, after avalanche condition is reached at the breakdown voltage BV D, NFET 100 often results in an l-V characteristic which "snaps-back" (i.e., the current increases rapidly with little change in voltage, as shown by the region identified by bracket 215).
  • the breakdown voltage BV D necessary to trigger avalanche often occurs at a high potential which may damage NFET 100 and the underlying circuitry NFET 100 is designed to protect, it is often desirable to have NFET 100 triggered into snap-back mode at as low a voltage as is possible in the holding voltage range (bracket 116). Additionally, the holding voltage for NFET 100 in snap-back is designed to be sufficiently higher than the maximum operating voltage while also commonly providing a deeper and wider conduction path than the path generated when the NFET 100 initially enters avalanche mode. Thus, in order to shunt ESD to ground through NFET 100 it is often desirable to trigger snap-back mode as close to the holding voltage X as is possible.
  • Lower voltage triggering of snap-back may be commonly accomplished in two ways.
  • One method is to forward bias the junction between the source 113 and the substrate 112 by raising the local substrate potential. Since raising the substrate potential often results in unwanted consequences (for example, increased energy consumption), this method is not preferred. Instead the second method is commonly preferred.
  • the impact ionization electron current necessary to trigger snap-back at a lower voltage is provided by turning on NFET 100 in the conventional mode (i.e., by providing a voltage at the gate 102, a high impedance node). Since the impact ionization current of NFET 100 has an optimum bias condition, the voltage at gate 102 should be within an optimal range.
  • NFET 100 will avalanche before snap-back is triggered. If the voltage at gate 102 is too high, NFET 100 often has a low energy field in the drain 111 and a weak impact ionization current. Thus, the optimum generation of channel impact ionization current occurs when gate 102 is biased is in the middle of these extremes. For an NFET 100 with a threshold voltage around 0.6 V, an optimum voltage for generating impact ionization at gate 102 is about 1.5 V.
  • Another approach used to control the biasing of gate 102 is accomplished by placing a resistor 118 between gate 102 and ground 106, as shown in Figure 4.
  • the parasitic capacitance 120 which arises between gate 102 and drain 108, pulls the gate 102 voltage up to the desired 1.5 V.
  • the parasitic capacitance 120 is hard to predict with precision and often has process variations.
  • the parasitic capacitance 120 often is either too high or too low.
  • the gate 102 voltage may sufficiently rise under normal operating conditions such that NFET 100 provides an undesirable shunt path from drain 108 to source 104.
  • the voltage at gate 102 may be so high that low voltage triggering does not occur.
  • FIG. 5 Another approach for shunting ESD through an NFET 100 is shown in Figure 5.
  • the current needed to raise the gate 102 voltage during an ESD is accomplished via the combination of a parasitic bipolar transistor 122, capacitor 130, and resistor 118 attached to NFET 100.
  • bipolar transistor 122 is a PNP transistor, as long as the voltage at the emitter 126 is higher than the voltage at the base 128, the bipolar transistor 122 activates. Since the base 128 is effectively grounded and at 0 Volts, the high voltage at the emitter 126 activates the bipolar transistor 122. In low voltage operations, the capacitor 130 effectively operates as a diode providing a 0.8 volt drop.
  • the bipolar transistor 122 activates. Once activated, the current through the base 128 begins to charge capacitor 130. The capacitor 130 continues to charge until the potential at the capacitor 130 equals the potential at the emitter 126 - V e> at which time the bipolar transistor 122 is deactivated since the capacitor 130 ultimately debiases the base-emitter junction of the bipolar transistor 122. Thus when ESD occurs, the junction of the base 128 with the emitter 126 forward biases and thereby causes current to flow through capacitor 130. As long as the base 128 current flows, collector 124 pulls the voltage at gate 102 up in accordance the current gain multiplication factor, ⁇ . The amount of current needed to raise the voltage at gate 102 to the level necessary to initiate impact ionization is determined by resistor 118.
  • the ESD initiates the production of electron-hole pairs at the drain 108.
  • the impact ionization current triggers snap-back and activates NFET 100 which shunts the ESD to ground 106.
  • the addition of the bipolar transistor 122 effectively reduces the voltage potential at the drain 108 of the NFET 100 necessary to force NFET 100 to snap-back.
  • V D s represents the voltage necessary to make NFET 100 enter snap-back mode.
  • V D s ⁇ represents the voltage necessary to enter snap-back mode after a larger potential is applied at the gate 102.
  • V D s ⁇ is significantly less than V D s-
  • the addition of the bipolar transistor 122 allows NFET 100 to shunt ESD at a lower voltage potential, thereby reducing the possibility of over-driving and damaging the NFET 100 or the underlying circuitry.
  • ⁇ can not be precisely determined and may vary with temperature and process variations, thus the current drawn through the collector 124 often can not be precisely determined.
  • the voltage generated at the gate 102 may often vary and may not ensure NFET 100 activates during ESD events.
  • the bipolar transistor 122 in this configuration is often susceptible to latch-up and must often be laid out very carefully in order to prevent latch-up.
  • the approach shown in Figure 5 may cause a current overload in NFET 100 due to the presence of an excess voltage potential at gate 102.
  • the activation potential at the gate 102 should be less than 1.5 Volts, and optimally between 0.5-0.8 Volts.
  • NFET 100 may not enter snap-back mode; instead the high voltage may burn-out the gate 102 oxide, and result in the flow of current through the gate 102 to the source 104, thereby permanently damaging NFET 100.
  • Another problem with the approach shown in Figure 5 occurs when too little voltage is applied at the gate 102.
  • gate 102 may not trigger snap-back mode at the lower drain voltage, S(1). Instead, the voltage at drain 108 may rise until snap-back is triggered at the avalanche breakdown voltage S(0).
  • this approach like the single MOS transistor approach shown in Figure 1 , may result in a large potential arising at the drain 108 which may damage NFET 100.
  • the approach in Figure 5 may result in NFET 100 turning on during the chip's power-up cycle. Since the internal impedance of the bipolar transistor 122 may vary as the temperature and other conditions change, it can be extremely difficult to tune the RC circuit which exists between the internal resistance of the bipolar transistor 122 and the capacitor 130. As a result, the time constant associated with this RC circuit may substantially vary. As the time constant varies, the voltage potential on the gate 102 may increase and may cause NFET 100 to activate during slower duration events, such as power-up, and thereby waste power.
  • a triggering scheme for an ESD protection circuit is provided which overcomes the noted shortcomings of the prior art. Additionally, a circuit is provided which tends to activate a MOS transistor during ESD events while regulating the voltage potential across the transistor to protect the transistor from over-voltage conditions. Further, a circuit is provided which provides for the rapid shunting of ESD currents at low voltages while allowing the circuit to be tuned such that desired higher voltage conditions, such as during chip power-up, are not shunted to ground.
  • ESD protection clamp which provides an RC circuit and the additional electronic components needed to regulate the voltage upon the gate of a MOS transistor.
  • the voltage regulator is designed so the transistor tends to snap back and shunt the current at its base without creating a large voltage potential across the gate of the transistor.
  • a protection circuit in accordance with the present invention shunts ESD by providing a switch and a control circuit.
  • the control circuit detects the accumulation of charge on the chip. When a sufficient magnitude of charge has accumulated within a predetermined time period, the control circuit opens a switch which shunts the charge to a reference potential (for example, a grounding source).
  • a reference potential for example, a grounding source.
  • the switch is a MOS transistor.
  • any switch capable of shunting ESD to a reference potential is within the scope of the present invention.
  • a protection circuit combines a MOS transistor, a capacitor, a resistor, and two diodes in a circuit wherein the ESD source is connected to both the drain of the MOS transistor and the first pole of a capacitor.
  • the second pole of the capacitor is connected to the gate of the MOS transistor, a resistor, and to two diodes connected in series to ground.
  • the source of the MOS transistor and the resistor are also grounded.
  • This embodiment provides for an effective ESD triggering circuit which will operate in low voltage transistor operations, e.g., for transistors whose turn-on voltage is less than 0.8-1.0 volts.
  • the diode or diodes are replaced by a second MOS transistor.
  • the drain and gate of this second transistor are commonly connected to the node connecting the capacitor and the resistor with the gate of the first MOS transistor.
  • Figure 1 is an cross-section view and an associated electrical schematic diagram of a MOS transistor used in the prior art for ESD protection circuit.
  • Figure 2 is a cross-sectional view of a MOS transistor which has begun to leak current from a high voltage potential base to the substrate, thereby generating electron-hole pairs.
  • Figure 3 is a graph which shows the voltage and current characteristics of the MOS transistor shown in Figure 1.
  • Figure 4 is an electrical schematic diagram of a MOS transistor with a resistor separating the gate of the transistor from a grounding source.
  • Figure 5 is an electrical schematic diagram of a prior art ESD protection circuit.
  • Figure 6 is a graph showing the voltage versus current characteristics of the MOS transistor shown in Figure 5.
  • FIG. 7 is a block diagram of an ESD protection circuit of the present invention.
  • Figure 8 is an electrical schematic diagram of the preferred embodiment of the present invention wherein the time constant utilized to determine when the ESD protection circuit will activate is implemented by an RC circuit, and the voltage regulation is performed by a series of diodes.
  • Figure 9 is an electrical schematic diagram of an alternate embodiment of the present invention.
  • Figure 10 is an electrical schematic diagram of an alternative embodiment of the present invention, wherein the regulation of the gate voltage is performed by a second MOS transistor.
  • the present invention is shown and described in the context of various electronic components.
  • the exemplary circuits described herein may be realized by any number of discrete hardware components or by any number of semiconductor integrated circuit components.
  • the ESD protection circuits may be combined with the protected circuitry, and additional components may be present in a practical implementation of the present invention.
  • Circuit 500 may be employed to shunt an electro static charge to a reference potential without damaging the underlying structure of an associated circuit or component 501 which is to be protected.
  • Circuit 500 includes a control circuit 502 and a switch 504.
  • An optional voltage regulator 506 may be suitably connected to the ESD protection circuit 500 when necessary to protect the switch 504 from over voltage conditions.
  • the switch 504 and control circuit 502 are preferably electrically connected via lead 514 to the chip pin 508, and the lead 514 is subject to ESD when it or the chip pin 508 come in contact with electro-static charges.
  • the present invention is not limited to protecting only chips, any component needing protection from ESD is within the scope of the present invention
  • the control circuit 502 of the present invention protects against ESD by responding to the rate of change and level of the ESD pulse on lead 514
  • the present invention may be configured to monitor and respond to any voltage and duration of electrical charge and is not to be limited as only shunting electro static charge
  • the control circuit 502 is responsive to changes in both the magnitude and its rate of change with time
  • control circuit is not limited to any one particular embodiment
  • the scope of the present invention includes any circuit which responds to the magnitude and rate at which a charge accumulates, and generates a corresponding control signal
  • any high-pass filter, resistor-capacitor filter transistorized or micro-processor controlled circuit, or the like is within the scope of the present invention
  • the control circuit 502 When charged particles accumulate at a relatively slow rate upon the chip pin 508 (for example, during a power-up sequence), the control circuit 502 preferably does not activate the switch 504 Instead, the control circuit 502 slowly shunts the charge accumulations to a reference potential Additionally, when charges accumulate at a relatively quick rate upon the chip package 508, such as would occur during ESD, the control circuit 502 detects the rapid charge accumulation or ESD and activates the switch 504, thereby shunting the ESD to the reference or ground potential 512
  • the switch 504 may be any component capable of transferring a large charge accumulation to a grounding source without interrupting the operation of the underlying integrated circuit or generating a large voltage between the lead 514 and the grounding node 512 Therefore, it can preferably protect any circuitry between the lead and the grounding node from ESD
  • the switch is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • any suitable switch or transistor including but not limited to JFETs, MESFETs, and IGFETs are within the scope of the present invention
  • MOS switch 504 has an optimal triggering voltage of 1 0 to 1 5 Volts
  • a triggering circuit 10 which is suitably configured to shunt high currents at relatively low voltages.
  • Circuit 10 includes a NFET 100 with a drain 108, a gate 102, and a source 104.
  • drain 108 is connected to both an ESD source 11 and to a first pole 131 of a capacitor 130.
  • the gate 102 is connected to the second pole 132 of capacitor 130, a first diode 140, and resistor 118. Resistor 118 is also connected to a grounding source or reference potential 106. A second diode 160 is connected in series between first diode 140 and reference potential 106. Source 104 is connected to reference potential 106. In operation, this particular embodiment of the present invention forces an NFET
  • an RC circuit provides the voltage at the gate 102 necessary to initiate snap-back at the lower drain voltage V D s ⁇ shown in Figure 6.
  • the gate potential is regulated by a series of diodes 140 and 160. The voltage clamp formed by the diode pair ensures the optimal voltage arises at gate 102 to initiate snap-back.
  • a suitable capacitance 130 and resistance 118 are selected such that the capacitance 130 will provides a sufficient voltage potential at gate 102 to initiate snap-back when an event occurs in 50-150 nanoseconds (such as ESD), while not providing a sufficient voltage potential at gate 102 for events which occur at a slower rate, such as a power-up event (which normally lasts for several milliseconds).
  • capacitance 130 is a separate component and, unlike the prior art, does not rely upon the parasitic capacitance of NFET 100, the modeling and manufacturing difficulties presented by the prior art are avoided. Even though parasitic capacitance exists between drain 108 and gate 102, the selection of a large capacitance 130 makes the parasitic capacitance irrelevant.
  • capacitor 118 can be efficiently and precisely fabricated for a specific capacitance using conventional engineering principles. Once the desired capacitance is established, a precise RC time constant may be implemented by selecting and constructing a resistor with a specific impedance, and connecting resistor 118 to capacitor 130 and to gate 102. Thus, an RC circuit is easily constructed which allows sufficient voltage at the gate 102 upon the occurrence of an event within a predetermined time period.
  • an RC time constant in the range of 50 to 150 nanoseconds may be accomplished by utilizing a resistance between 100K and 500K ohms, and a corresponding capacitance between 1 pico and 0.1 pico farads.
  • the capacitance is preferably selected so that the parasitic capacitance which exists within a transistor is negligible. Therefore, the present invention preferably utilizes a resistance of 100K ohms and a capacitance of 1 pico farad.
  • the exemplary triggering circuit 10 also prevents gate 102 from being over-driven by providing over-voltage protection circuitry.
  • the predetermined value is 1.5 volts.
  • each of the diodes 140 and 160 operates as a short while providing a voltage drop of approximately 0.7 to 0.8 volts.
  • the maximum voltage present at the gate is maintained around 1.5 volts and prevents a high voltage from arising at the gate 102 which could damage NFET 100.
  • Figure 9 depicts an alternative embodiment of a triggering circuit 24 having a desired voltage at the gate 102 of no more than 0.8 volts. In this embodiment, diode 140 tends to shunt any voltage greater than 0.8 volts to ground.
  • a protection circuit may also control a potential at the drain 108 which may damage NFET 100 by forcing NFET 100 to snap-back at the high voltage identified in Figure 6 as V D s .
  • V D s the high voltage identified in Figure 6
  • a large voltage may accumulate at the drain 108 when the gate 102 does not receive sufficient current to force NFET 100 to snap-back at the lower drain voltage identified in Figure 6 as V D s ⁇ -
  • a protection circuit suitably prevents a high drain voltage from arising by isolating gate 102 from grounding source 106 by a high impedance resistor 118 which tends to ensure sufficient potential exists at the gate 102 to trigger snap-back at the lower threshold, Vpsi- Resistor 118 also tends to prevent NFET 100 from turning on during slower events such as power-ups.
  • the circuit can be tuned to trigger NFET 100 during ESD events.
  • the voltage at gate 102 necessary to initiate snap-back does not need to exist for very long, because snap-back usually occurs within 100 picoseconds of the application of the threshold voltage (for example, 1.5 volts).
  • the RC circuit can be tuned to provide the threshold voltage at the gate 102 for a selected set of ESD durations (for example, from 50 to 150 nanoseconds), while not providing the voltage during slower events.
  • the present invention may also be embodied in a triggering circuit 32 which utilizes a second transistor 150 to provide the voltage regulating function performed by diodes in circuits 130 and 140 (as shown in Figure 9).
  • transistor 150 clamps the voltage at gate 102 when it exceeds a predetermined threshold, in this case 1.5 volts.
  • the operation of second transistor 150 is as follows: when the voltages at gates 102 and 154 reach 0.5 to 0.8 volts, both NFET 100 and second transistor 150 will activate. More specifically, second transistor 150 is configured to shunt any voltage over 0.5 to 0.8 volts to prevent gate 102 from being over driven. Since drain 152 directly connected to gate 154, second transistor 150 is not driven into snap-back mode (i.e., does not act as a bi-polar transistor).

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un circuit de décharge d'une charge électrostatique s'étant accumulée sur un boîtier à semi-conducteur (puce) à un potentiel de référence sans détériorer le circuit se trouvant dans la puce. Le noeud de drain d'un transistor MOS est connecté à une puce, le noeud de source est mis à la terre et le noeud de porte est connecté à un circuit de déclenchement. Le circuit de déclenchement comprend une résistance et un condensateur formant une constante de temps RC et permet au transistor MOS de s'activer lorsqu'un potentiel électrique s'élève au niveau du noeud de drain dans la constante de temps RC prédéterminée. Le circuit de déclenchement protège de préférence la porte du transistor MOS contre un état de surtension par connexion d'une pluralité de diodes en parallèle au transistor MOS de manière que des tensions de porte supérieures à une valeur de seuil soient dérivées vers la masse. Dans un autre mode de réalisation, la porte est protégée contre un état de surtension par un second transistor MOS connecté en parallèle au premier transistor MOS. Le drain et la porte du second transistor MOS sont connectés de manière que lorsqu'une tension supérieure à un seuil prédéterminé s'élève au niveau de la porte du premier transistor MOS, le second transistor MOS soit activé et la tension excédentaire soit dérivée vers la masse.
PCT/US1999/019048 1998-09-25 1999-08-23 Circuit de declenchement de fixation de niveau de protection contre les decharges electrostatiques WO2000019574A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16115798A 1998-09-25 1998-09-25
US09/161,157 1998-09-25

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WO2000019574A1 true WO2000019574A1 (fr) 2000-04-06

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109831195A (zh) * 2019-01-29 2019-05-31 维沃移动通信有限公司 按键控制电路和移动终端

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0435047A2 (fr) * 1989-12-19 1991-07-03 National Semiconductor Corporation Protection contre des décharges électrostatiques pour circuits intégrés
US5173755A (en) * 1989-05-12 1992-12-22 Western Digital Corporation Capacitively induced electrostatic discharge protection circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173755A (en) * 1989-05-12 1992-12-22 Western Digital Corporation Capacitively induced electrostatic discharge protection circuit
EP0435047A2 (fr) * 1989-12-19 1991-07-03 National Semiconductor Corporation Protection contre des décharges électrostatiques pour circuits intégrés

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109831195A (zh) * 2019-01-29 2019-05-31 维沃移动通信有限公司 按键控制电路和移动终端
CN109831195B (zh) * 2019-01-29 2023-12-12 维沃移动通信有限公司 按键控制电路和移动终端

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