WO2000019574A1

WO2000019574A1 - Triggering circuit for esd protection clamp

Info

Publication number: WO2000019574A1
Application number: PCT/US1999/019048
Authority: WO
Inventors: Xiaoming Li; Eugene R. Worley
Original assignee: Conexant Systems, Inc.
Priority date: 1998-09-25
Filing date: 1999-08-23
Publication date: 2000-04-06

Abstract

A circuit for discharging an Electro-Static charge which has accumulated upon a semiconductor package (chip) to a reference potential without damaging the circuitry within the chip is disclosed. The drain node of a Metal Oxide Semiconductor (MOS) transistor is connected to a chip, the source node is grounded, and the gate node is connected to a triggering circuit. The triggering circuit includes a resistor and a capacitor which form an RC time constant and allow the MOS transistor to activate when an electrical potential arises at the drain node within the predetermined RC time constant. The triggering circuit preferably protects the gate of the MOS transistor from an over voltage condition by connecting a plurality of diodes in parallel with the MOS transistor such that gate voltages higher than a threshold are shunted to ground. In an alternative embodiment, the gate is protected from an over voltage condition by a second MOS transistor connected in parallel with the first MOS transistor. The drain and gate of the second MOS transistor are connected so that when a voltage greater than a predetermined threshold arises at the gate of the first MOS transistor, the second MOS transistor is activated and the excess voltage is shunted to ground.

Description

TRIGGERING CIRCUIT FOR ESD PROTECTION CLAMP

TECHNICAL FIELD The present invention relates to Electro-Static Discharge (ESD) protection circuits for use with semiconductor based electronic circuits. More particularly, the present invention relates to an ESD protection triggering circuit that regulates its voltage potential such that an over-voltage condition will not occur.

BACKGROUND ARTAND TECHNICAL PROBLEMS ESD is a physical phenomenon which is well-known in the electronics industry and in general. Many persons have felt the electrical shock which may occur when one touches a metal surface such as a lamp, television, or the like after having walked in their socks across a deep shag carpet. While these discharges commonly range between 2,000 and 4,500 volts and are discharged over a few milliseconds, they appear to the victim as a harmless, but attention-getting, electrical shock. The human body provides a high resistance to the discharge of these significant volts, thereby decreasing the associated current. The Human Body Model (HBM) standard assumes that the human body has a capacitance of 100 pf and a series resistance of 1500 Ohms. Thus, the peak current flow during a human body ESD is generally on the order of amps. ESD may also occur when charges accumulate upon an ungrounded surface. For example, a piece of equipment, electronic circuit, or the like which is not grounded may collect charges as it is moved from one location to another. When the charged equipment touches an electrical conductor, ESD may occur. The electric current will follow the path of least resistance (often through vital electronic circuitry) to the conductor. In microelectronic systems, the conductor is often a prong of an integrated circuit chip.

The prevalent use of sensitive semiconductor chips in today's industrial and commercial products has made ESD a major concern in the design, layout, fabrication, and protection of chips. Unlike the human body which can easily dissipate ESD, chips are extremely sensitive to ESD. Depending on the technology utilized in a chip, the maximum safe voltage the internal circuit elements can tolerate varies anywhere from several volts to nearly 20 volts. As such, the mere touching of a chip by a non-grounded person or tool may result in ESD which can damage the delicate electronic structures in an unprotected chip. To prevent ESD from damaging semiconductor circuits, various protective schemes may be employed. Large scale protective schemes often protect system level equipment; these schemes include: grounding cases and external surfaces of the electrical equipment, grounding technicians via wrist bands, using specialized shipping containers, and the like. Additionally, small scale, chip specific, approaches may be utilized. Often high current clamping devices are placed on the pins of a chip so that the high currents associated with an ESD are safely shunted without a large and damaging charge build up on the pins of the chip.

Ideally, such clamping devices are transparent during normal chip operations but shunt the high current of an ESD event. This is typically accomplished by using a device which is normally "off but has a turn on threshold which is well above a chip's normal operating voltage and is also below a voltage which may damage a chip's circuit elements. Since higher power dissipations by the clamp may result in an electro-thermal failure within a circuit, the threshold is often set as close as possible to the operating voltage of the circuit.

A common method of creating such a clamp on CMOS integrated circuits is to use a grounded gate NMOS Field Effect Transistor (NFET) 100 as shown in Figure 1 (wherein the figure on the left is a cross section of NFET 100, and the figure on the right is a schematic diagram). Normally, NFET 100 is in an "off" state. However, if a positive charge accumulation of sufficient potential arises between the drain 108 and source 104 terminals, the drain junction 111 will often avalanche and NFET 100 will start conducting. Due to the electrostatic effects of the gate 102, the avalanche conduction normally occurs near the surface of the silicon substrate 112 at the junction of the drain 111 and the substrate 112. Once the avalanche process begins, electron-hole pairs are generated in the depletion region of the drain 111. The electrons 114 then conduct to the N+ diffusion 111 while the holes 115 conduct to the P substrate 112, as shown in Figure 2. Commonly, enough holes 115 conduct such that the junction of the source 113 with the substrate 112 forward biases. After the substrate forward biases, the close proximity of the drain 111 often results in a parasitic bipolar conduction occurring between the drain 111 and the source 113. The base current Isub can sustain such parasitic bipolar conduction even below the avalanche voltage due to the impact ionization of the drain (or "collector") electron current. As shown in Figure 3, after avalanche condition is reached at the breakdown voltage BV_D, NFET 100 often results in an l-V characteristic which "snaps-back" (i.e., the current increases rapidly with little change in voltage, as shown by the region identified by bracket 215).

Since the breakdown voltage BV_D necessary to trigger avalanche often occurs at a high potential which may damage NFET 100 and the underlying circuitry NFET 100 is designed to protect, it is often desirable to have NFET 100 triggered into snap-back mode at as low a voltage as is possible in the holding voltage range (bracket 116). Additionally, the holding voltage for NFET 100 in snap-back is designed to be sufficiently higher than the maximum operating voltage while also commonly providing a deeper and wider conduction path than the path generated when the NFET 100 initially enters avalanche mode. Thus, in order to shunt ESD to ground through NFET 100 it is often desirable to trigger snap-back mode as close to the holding voltage X as is possible.

Lower voltage triggering of snap-back may be commonly accomplished in two ways. One method is to forward bias the junction between the source 113 and the substrate 112 by raising the local substrate potential. Since raising the substrate potential often results in unwanted consequences (for example, increased energy consumption), this method is not preferred. Instead the second method is commonly preferred. In the second method, the impact ionization electron current necessary to trigger snap-back at a lower voltage is provided by turning on NFET 100 in the conventional mode (i.e., by providing a voltage at the gate 102, a high impedance node). Since the impact ionization current of NFET 100 has an optimum bias condition, the voltage at gate 102 should be within an optimal range. If the voltage at gate 102 is too low, current will not flow through the channel, impact ionization will not occur, and NFET 100 will avalanche before snap-back is triggered. If the voltage at gate 102 is too high, NFET 100 often has a low energy field in the drain 111 and a weak impact ionization current. Thus, the optimum generation of channel impact ionization current occurs when gate 102 is biased is in the middle of these extremes. For an NFET 100 with a threshold voltage around 0.6 V, an optimum voltage for generating impact ionization at gate 102 is about 1.5 V.

Many different approaches exist for controlling the gate voltage of an NFET used to shunt ESD. As shown in Figure 1 , one approach is to attach the drain 108 to the chip's lid 110 and the source 104 and gate 102 to ground 106. While simple to fabricate, this approach provides no means of controlling the activation voltage for the transistor. As voltage is applied to the drain 108, the leakage current easily flows through the gate 102 to ground 106. The lack of resistance between the ground 106 and gate 102 often prevent a high enough potential from accumulating at the gate 102 to activate the transistor. As a result, a very large potential may arise at the drain 108, which eventually causes a high current to be discharged to ground 106 through NFET 100, thereby potentially damaging the unprotected circuitry. Another approach used to control the biasing of gate 102 is accomplished by placing a resistor 118 between gate 102 and ground 106, as shown in Figure 4. During ESD, the parasitic capacitance 120 which arises between gate 102 and drain 108, pulls the gate 102 voltage up to the desired 1.5 V. However, the parasitic capacitance 120 is hard to predict with precision and often has process variations. Thus, under this approach, the parasitic capacitance 120 often is either too high or too low. When the parasitic capacitance 120 is too high, the gate 102 voltage may sufficiently rise under normal operating conditions such that NFET 100 provides an undesirable shunt path from drain 108 to source 104. Also, the voltage at gate 102 may be so high that low voltage triggering does not occur. When the parasitic capacitance 120 is too low, a sufficient gate 102 voltage may not arise, and snap-back may be triggered by a high voltage (such as the avalanche voltage), and damage to NFET 100 or other components may occur. Therefore, while this approach commonly alleviates the problem of the gate 102 never reaching a high enough potential to activate the transistor, it presents other difficulties, which may lead to damage of the chip or unnecessary shunting to ground of electrical signals.

Another approach for shunting ESD through an NFET 100 is shown in Figure 5. In this approach the current needed to raise the gate 102 voltage during an ESD is accomplished via the combination of a parasitic bipolar transistor 122, capacitor 130, and resistor 118 attached to NFET 100. Since bipolar transistor 122 is a PNP transistor, as long as the voltage at the emitter 126 is higher than the voltage at the base 128, the bipolar transistor 122 activates. Since the base 128 is effectively grounded and at 0 Volts, the high voltage at the emitter 126 activates the bipolar transistor 122. In low voltage operations, the capacitor 130 effectively operates as a diode providing a 0.8 volt drop. Thus, as long as the voltage at the drain 108 is greater than 0.8 volts, the bipolar transistor 122 activates. Once activated, the current through the base 128 begins to charge capacitor 130. The capacitor 130 continues to charge until the potential at the capacitor 130 equals the potential at the emitter 126 - V _e> at which time the bipolar transistor 122 is deactivated since the capacitor 130 ultimately debiases the base-emitter junction of the bipolar transistor 122. Thus when ESD occurs, the junction of the base 128 with the emitter 126 forward biases and thereby causes current to flow through capacitor 130. As long as the base 128 current flows, collector 124 pulls the voltage at gate 102 up in accordance the current gain multiplication factor, β. The amount of current needed to raise the voltage at gate 102 to the level necessary to initiate impact ionization is determined by resistor 118.

Simultaneous with the flow of current from the emitter 126 through the base 128, the ESD initiates the production of electron-hole pairs at the drain 108. Upon the bipoiar transistor 122 activating and the collector 124 raising the voltage at gate 102, the impact ionization current triggers snap-back and activates NFET 100 which shunts the ESD to ground 106.

As shown in Figures 5 and 6, the addition of the bipolar transistor 122 effectively reduces the voltage potential at the drain 108 of the NFET 100 necessary to force NFET 100 to snap-back. In Figure 6, V_Ds represents the voltage necessary to make NFET 100 enter snap-back mode. V_Dsι represents the voltage necessary to enter snap-back mode after a larger potential is applied at the gate 102. V_Dsι is significantly less than V_Ds- Thus, the addition of the bipolar transistor 122 allows NFET 100 to shunt ESD at a lower voltage potential, thereby reducing the possibility of over-driving and damaging the NFET 100 or the underlying circuitry. However, β can not be precisely determined and may vary with temperature and process variations, thus the current drawn through the collector 124 often can not be precisely determined. Thus, the voltage generated at the gate 102 may often vary and may not ensure NFET 100 activates during ESD events. Additionally, the bipolar transistor 122 in this configuration is often susceptible to latch-up and must often be laid out very carefully in order to prevent latch-up.

Additionally, the approach shown in Figure 5 may cause a current overload in NFET 100 due to the presence of an excess voltage potential at gate 102. The activation potential at the gate 102 should be less than 1.5 Volts, and optimally between 0.5-0.8 Volts. When too much voltage is applied at the gate 102, NFET 100 may not enter snap-back mode; instead the high voltage may burn-out the gate 102 oxide, and result in the flow of current through the gate 102 to the source 104, thereby permanently damaging NFET 100. Another problem with the approach shown in Figure 5 occurs when too little voltage is applied at the gate 102. As shown in Figure 6, when the voltage at gate 102 does not reach the activation voltage of the NFET 100, gate 102 may not trigger snap-back mode at the lower drain voltage, S(1). Instead, the voltage at drain 108 may rise until snap-back is triggered at the avalanche breakdown voltage S(0). Thus, this approach, like the single MOS transistor approach shown in Figure 1 , may result in a large potential arising at the drain 108 which may damage NFET 100.

Additionally, the approach in Figure 5 may result in NFET 100 turning on during the chip's power-up cycle. Since the internal impedance of the bipolar transistor 122 may vary as the temperature and other conditions change, it can be extremely difficult to tune the RC circuit which exists between the internal resistance of the bipolar transistor 122 and the capacitor 130. As a result, the time constant associated with this RC circuit may substantially vary. As the time constant varies, the voltage potential on the gate 102 may increase and may cause NFET 100 to activate during slower duration events, such as power-up, and thereby waste power.

SUMMARY OF THE INVENTION

In accordance with the present invention, a triggering scheme for an ESD protection circuit is provided which overcomes the noted shortcomings of the prior art. Additionally, a circuit is provided which tends to activate a MOS transistor during ESD events while regulating the voltage potential across the transistor to protect the transistor from over-voltage conditions. Further, a circuit is provided which provides for the rapid shunting of ESD currents at low voltages while allowing the circuit to be tuned such that desired higher voltage conditions, such as during chip power-up, are not shunted to ground.

The above and other advantages may be carried out by a triggering circuit for an

ESD protection clamp which provides an RC circuit and the additional electronic components needed to regulate the voltage upon the gate of a MOS transistor. The voltage regulator is designed so the transistor tends to snap back and shunt the current at its base without creating a large voltage potential across the gate of the transistor.

A protection circuit in accordance with the present invention shunts ESD by providing a switch and a control circuit. The control circuit detects the accumulation of charge on the chip. When a sufficient magnitude of charge has accumulated within a predetermined time period, the control circuit opens a switch which shunts the charge to a reference potential (for example, a grounding source). For the preferred embodiment of the present invention, the switch is a MOS transistor. However, any switch capable of shunting ESD to a reference potential is within the scope of the present invention. More particularly, a protection circuit according to various aspects of the present invention combines a MOS transistor, a capacitor, a resistor, and two diodes in a circuit wherein the ESD source is connected to both the drain of the MOS transistor and the first pole of a capacitor. The second pole of the capacitor is connected to the gate of the MOS transistor, a resistor, and to two diodes connected in series to ground. The source of the MOS transistor and the resistor are also grounded. One advantage of this embodiment of the present invention is that by suitably selecting and combining the capacitance and the resistance, the circuit can be tuned such that the MOS transistor shunts current within a range of specific magnitude and duration. This feature allows the circuit to shunt ESDs while not shunting normal power-up charges. In another embodiment of the present invention, one of the two diodes is removed.

This embodiment provides for an effective ESD triggering circuit which will operate in low voltage transistor operations, e.g., for transistors whose turn-on voltage is less than 0.8-1.0 volts.

In an alternative embodiment of the present invention, the diode or diodes are replaced by a second MOS transistor. The drain and gate of this second transistor are commonly connected to the node connecting the capacitor and the resistor with the gate of the first MOS transistor.

BRIEF DESCRIPTION OF THE DRAWING FIGURES The present invention is hereinafter described in conjunction with the appended drawing figures, wherein like numerals generally denote like elements, and:

Figure 1 is an cross-section view and an associated electrical schematic diagram of a MOS transistor used in the prior art for ESD protection circuit.

Figure 2 is a cross-sectional view of a MOS transistor which has begun to leak current from a high voltage potential base to the substrate, thereby generating electron-hole pairs.

Figure 3 is a graph which shows the voltage and current characteristics of the MOS transistor shown in Figure 1. Figure 4 is an electrical schematic diagram of a MOS transistor with a resistor separating the gate of the transistor from a grounding source.

Figure 5 is an electrical schematic diagram of a prior art ESD protection circuit.

Figure 6 is a graph showing the voltage versus current characteristics of the MOS transistor shown in Figure 5.

Figure 7 is a block diagram of an ESD protection circuit of the present invention.

Figure 8 is an electrical schematic diagram of the preferred embodiment of the present invention wherein the time constant utilized to determine when the ESD protection circuit will activate is implemented by an RC circuit, and the voltage regulation is performed by a series of diodes.

Figure 9 is an electrical schematic diagram of an alternate embodiment of the present invention.

Figure 10 is an electrical schematic diagram of an alternative embodiment of the present invention, wherein the regulation of the gate voltage is performed by a second MOS transistor.

DETAILED DESCRIPTION OF PREFERRED EXEMPLARY EMBODIMENTS The present invention is shown and described in the context of various electronic components. The exemplary circuits described herein may be realized by any number of discrete hardware components or by any number of semiconductor integrated circuit components. Furthermore, the ESD protection circuits may be combined with the protected circuitry, and additional components may be present in a practical implementation of the present invention.

Referring now to Figure 7, a preferred embodiment of the present invention is realized by an exemplary ESD protection circuit 500. Circuit 500 may be employed to shunt an electro static charge to a reference potential without damaging the underlying structure of an associated circuit or component 501 which is to be protected. Circuit 500 includes a control circuit 502 and a switch 504. An optional voltage regulator 506 may be suitably connected to the ESD protection circuit 500 when necessary to protect the switch 504 from over voltage conditions. The switch 504 and control circuit 502 are preferably electrically connected via lead 514 to the chip pin 508, and the lead 514 is subject to ESD when it or the chip pin 508 come in contact with electro-static charges. However, the present invention is not limited to protecting only chips, any component needing protection from ESD is within the scope of the present invention

The control circuit 502 of the present invention protects against ESD by responding to the rate of change and level of the ESD pulse on lead 514 As such, the present invention may be configured to monitor and respond to any voltage and duration of electrical charge and is not to be limited as only shunting electro static charge Preferably, the control circuit 502 is responsive to changes in both the magnitude and its rate of change with time

The control circuit, however, is not limited to any one particular embodiment The scope of the present invention includes any circuit which responds to the magnitude and rate at which a charge accumulates, and generates a corresponding control signal Thus, any high-pass filter, resistor-capacitor filter transistorized or micro-processor controlled circuit, or the like is within the scope of the present invention

When charged particles accumulate at a relatively slow rate upon the chip pin 508 (for example, during a power-up sequence), the control circuit 502 preferably does not activate the switch 504 Instead, the control circuit 502 slowly shunts the charge accumulations to a reference potential Additionally, when charges accumulate at a relatively quick rate upon the chip package 508, such as would occur during ESD, the control circuit 502 detects the rapid charge accumulation or ESD and activates the switch 504, thereby shunting the ESD to the reference or ground potential 512

The switch 504 may be any component capable of transferring a large charge accumulation to a grounding source without interrupting the operation of the underlying integrated circuit or generating a large voltage between the lead 514 and the grounding node 512 Therefore, it can preferably protect any circuitry between the lead and the grounding node from ESD For the preferred embodiment, the switch is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) However, any suitable switch or transistor including but not limited to JFETs, MESFETs, and IGFETs are within the scope of the present invention

If the switch is voltage sensitive, such that the activation signal from the control circuit 502 upon lead 516 may damage the switch 504, a voltage regulator 506 may be included which regulates the control signal upon lead 516 such that it may be less than a predetermined threshold In a preferred embodiment, MOS switch 504 has an optimal triggering voltage of 1 0 to 1 5 Volts Referring now to Figure 8, the preferred embodiment of the present invention may be realized by a triggering circuit 10 which is suitably configured to shunt high currents at relatively low voltages. Circuit 10 includes a NFET 100 with a drain 108, a gate 102, and a source 104. Preferably, drain 108 is connected to both an ESD source 11 and to a first pole 131 of a capacitor 130. The gate 102 is connected to the second pole 132 of capacitor 130, a first diode 140, and resistor 118. Resistor 118 is also connected to a grounding source or reference potential 106. A second diode 160 is connected in series between first diode 140 and reference potential 106. Source 104 is connected to reference potential 106. In operation, this particular embodiment of the present invention forces an NFET

100 into snap-back mode at a lower voltage by providing a triggering voltage at the gate 102. Thus, during operation of NFET 100, a large potential appears at drain 108 which is converted into a voltage at gate 102 sufficient to trigger snap-back at the lower drain voltage V_Dsι instead of the higher drain voltage V_Ds as shown in Figure 6. However, unlike the prior art approach shown in Figure 5 which relies upon a bi-polar transistor 122, in the preferred embodiment an RC circuit provides the voltage at the gate 102 necessary to initiate snap-back at the lower drain voltage V_Dsι shown in Figure 6. Additionally, the gate potential is regulated by a series of diodes 140 and 160. The voltage clamp formed by the diode pair ensures the optimal voltage arises at gate 102 to initiate snap-back. Since ESD normally occurs within a time period on the order of 50 - 150 nano-seconds, a suitable capacitance 130 and resistance 118 are selected such that the capacitance 130 will provides a sufficient voltage potential at gate 102 to initiate snap-back when an event occurs in 50-150 nanoseconds (such as ESD), while not providing a sufficient voltage potential at gate 102 for events which occur at a slower rate, such as a power-up event (which normally lasts for several milliseconds). Since capacitance 130 is a separate component and, unlike the prior art, does not rely upon the parasitic capacitance of NFET 100, the modeling and manufacturing difficulties presented by the prior art are avoided. Even though parasitic capacitance exists between drain 108 and gate 102, the selection of a large capacitance 130 makes the parasitic capacitance irrelevant.

Additionally, capacitor 118 can be efficiently and precisely fabricated for a specific capacitance using conventional engineering principles. Once the desired capacitance is established, a precise RC time constant may be implemented by selecting and constructing a resistor with a specific impedance, and connecting resistor 118 to capacitor 130 and to gate 102. Thus, an RC circuit is easily constructed which allows sufficient voltage at the gate 102 upon the occurrence of an event within a predetermined time period. For the present invention, an RC time constant in the range of 50 to 150 nanoseconds may be accomplished by utilizing a resistance between 100K and 500K ohms, and a corresponding capacitance between 1 pico and 0.1 pico farads. The capacitance is preferably selected so that the parasitic capacitance which exists within a transistor is negligible. Therefore, the present invention preferably utilizes a resistance of 100K ohms and a capacitance of 1 pico farad.

The exemplary triggering circuit 10 also prevents gate 102 from being over-driven by providing over-voltage protection circuitry. The addition of two diodes 140 and 160 to second pole 132 of capacitor 130, as shown in Figure 8, preferably maintains the voltage at gate 102 below a predetermined value. In this embodiment, the predetermined value is 1.5 volts. Whenever a voltage greater than about 1.5 volts is present at gate 102, each of the diodes 140 and 160 operates as a short while providing a voltage drop of approximately 0.7 to 0.8 volts. Thus, the maximum voltage present at the gate is maintained around 1.5 volts and prevents a high voltage from arising at the gate 102 which could damage NFET 100. For a typical MOS transistor, 1.5 volts is the optimal gate voltage necessary to trigger snap-back. The maximum voltage allowed at the gate 102 can be regulated, as necessary, by the addition or subtraction of additional diodes or the like to achieve the optimal snap-back of NFET 100. The protection circuit may be implemented to facilitate the regulation of any gate voltage desired, and may be modified as necessary to regulate any voltage. For example, Figure 9 depicts an alternative embodiment of a triggering circuit 24 having a desired voltage at the gate 102 of no more than 0.8 volts. In this embodiment, diode 140 tends to shunt any voltage greater than 0.8 volts to ground.

A protection circuit according to various aspects of the present invention may also control a potential at the drain 108 which may damage NFET 100 by forcing NFET 100 to snap-back at the high voltage identified in Figure 6 as V_Ds_. As previously discussed, a large voltage may accumulate at the drain 108 when the gate 102 does not receive sufficient current to force NFET 100 to snap-back at the lower drain voltage identified in Figure 6 as V_Dsι- In accordance with various aspects of the present invention, a protection circuit suitably prevents a high drain voltage from arising by isolating gate 102 from grounding source 106 by a high impedance resistor 118 which tends to ensure sufficient potential exists at the gate 102 to trigger snap-back at the lower threshold, Vpsi- Resistor 118 also tends to prevent NFET 100 from turning on during slower events such as power-ups. By selecting an appropriate resistor 118 and capacitor 130, the circuit can be tuned to trigger NFET 100 during ESD events. The voltage at gate 102 necessary to initiate snap-back does not need to exist for very long, because snap-back usually occurs within 100 picoseconds of the application of the threshold voltage (for example, 1.5 volts). Thus, the RC circuit can be tuned to provide the threshold voltage at the gate 102 for a selected set of ESD durations (for example, from 50 to 150 nanoseconds), while not providing the voltage during slower events.

Turning now to Figure 10, the present invention may also be embodied in a triggering circuit 32 which utilizes a second transistor 150 to provide the voltage regulating function performed by diodes in circuits 130 and 140 (as shown in Figure 9). In this embodiment, transistor 150 clamps the voltage at gate 102 when it exceeds a predetermined threshold, in this case 1.5 volts. The operation of second transistor 150 is as follows: when the voltages at gates 102 and 154 reach 0.5 to 0.8 volts, both NFET 100 and second transistor 150 will activate. More specifically, second transistor 150 is configured to shunt any voltage over 0.5 to 0.8 volts to prevent gate 102 from being over driven. Since drain 152 directly connected to gate 154, second transistor 150 is not driven into snap-back mode (i.e., does not act as a bi-polar transistor).

Although the present invention has been described in conjunction with the appended drawing figures, the invention is not so limited. Various additions, deletions, substitutions, and rearrangement of parts may be made in the design and implementation of an ESD protection circuit without departing from the spirit and scope of the present invention, as set forth more particularly in the appended claims.

Claims

1 A circuit for transferring a charge having a magnitude varying with time from a source to a reference potential, comprising a control circuit configured to receive the charge from the source, wherein said control circuit generates a control signal according to both the charge magnitude and the rate at which the charge magnitude varies, and a switch connected to the control circuit and responsive to the control signal, wherein said switch selectively connects said source to said reference potential when said control signal exceeds a selected threshold

2 The circuit of claim 1 wherein said charge is an electro-static charge

3 The circuit of claim 1 wherein said source is the lead on the package of an electronic component

4 The circuit of claim 1 wherein said source is the build-up of ionized particles which occur upon a surface being transferred within a non-vacuum

The circuit of claim 1 wherein said source is an electrical generator

6 The circuit of claim 1 wherein said control circuit further comprises a high pass filter which outputs a control signal indicative of a change in magnitude within a predetermined time period in the electrical potential sensed by said control circuit

7 The circuit of claim 6 wherein said change in magnitude is greater than 1 5 volts

8 The circuit of claim 6 wherein said predetermined time period is within

50 - 150 nanoseconds

9 The circuit of claim 1 wherein said switch is a transistor

10. The circuit of claim 9 wherein said transistor is selected from the group of field effect transistors (FETs) consisting of junction FETs, metal-Schottky FETs, insulated gate FETs, and metal oxide semiconductor FETs.

11. The circuit of claim 1 wherein said control circuit further comprises a Resistor - Capacitor (RC) circuit wherein said capacitor has a first and a second capacitor terminal, and said resistor has a first and a second resistor terminal; wherein said first capacitor terminal is configured to receive said charge from said source, said second capacitor terminal is connected to said first resistor terminal, and said second resistor terminal is connected to said reference potential; said control signal arising at the junction of said second capacitor terminal and said first resistor terminal.

12. The circuit of claim 11 wherein said RC circuit has a time constant within the range of 50 - 150 nanoseconds.

13. The circuit of claim 11 wherein said resistor has a resistance within the range of 100K to 500K Ohms.

14. The circuit of claim 11 wherein said capacitor has a capacitance within the range of 0.2 pico to 1.0 pico farads.

15. The circuit of claim 1 wherein said control circuit further comprises a voltage regulator which regulates the voltage level of said control signal and provides a closed circuit between said control signal and said reference potential when the voltage of said control signal exceeds a predetermined threshold.

16. The circuit of claim 15 wherein said predetermined threshold is 1.6 volts.

17. The circuit of claim 15 wherein said voltage regulator further comprises two diodes in series which provide a closed circuit between said control signal and said reference potential when the magnitude of said control signal exceeds a predetermined threshold, and at all other times provides an open circuit.

18. The circuit of claim 15 wherein said voltage regulator comprises a single diode which provides a closed circuit between said control signal and said reference potential when the magnitude of said control signal exceeds a predetermined threshold, and at all other times provides an open circuit.

19. The circuit of claim 18 wherein said predetermined threshold is 0.8 volts.

20. The circuit of claim 15 wherein said voltage regulator further comprises a switch which selectively connects said control signal to said reference potential when the voltage of said control signal exceeds a predetermined threshold.

21. The circuit of claim 20 wherein said switch is a transistor.

22. The circuit of claim 21 wherein said transistor is a MOSFET which further comprises a drain terminal, a gate terminal, and a source terminal; wherein said drain and gate terminals are connected and are responsive to said control signal, and said source terminal is connected to said reference potential, such that the presence of said control signal at a voltage greater than said predetermined threshold activates said MOSFET and closes the circuit between said control signal and said reference potential.

23. A circuit for transferring an electro-static charge from the package of an electronic component to a reference potential, comprising: a control circuit configured to receive said electro-static charge from said package, wherein said control circuit generates a control signal according to both the magnitude of said electro-static charge and the rate at which said electro-static charge accumulates upon said package; and a switch connected to said control circuit and responsive to said control signal, wherein said switch selectively connects said electro-static charge to said reference potential when said control signal exceeds a selected threshold.