WO2000016279A1 - Microcircuit de badge hf a plages d'interconnexions imprimees - Google Patents

Microcircuit de badge hf a plages d'interconnexions imprimees Download PDF

Info

Publication number
WO2000016279A1
WO2000016279A1 PCT/US1999/020312 US9920312W WO0016279A1 WO 2000016279 A1 WO2000016279 A1 WO 2000016279A1 US 9920312 W US9920312 W US 9920312W WO 0016279 A1 WO0016279 A1 WO 0016279A1
Authority
WO
WIPO (PCT)
Prior art keywords
radio frequency
frequency identification
identification tag
layer
circuit chip
Prior art date
Application number
PCT/US1999/020312
Other languages
English (en)
Inventor
Noel H. Eberhardt
Original Assignee
Motorola Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc. filed Critical Motorola Inc.
Priority to AU57044/99A priority Critical patent/AU5704499A/en
Publication of WO2000016279A1 publication Critical patent/WO2000016279A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Definitions

  • the present invention relates generally to radio frequency identification tags and radio frequency identification tag circuit chips including, but not limited to, radio frequency identification tag circuit chips having printed interconnection pads.
  • Radio frequency identification tags and radio frequency identification tag systems are known, and find numerous uses. For example, radio frequency identification tags are frequently used for personal identification in automated gate sentry applications protecting secured buildings or areas. Information stored on the radio frequency identification tag identifies the person seeking access to the secured building.
  • a radio frequency identification tag system conveniently provides for reading the information from the radio frequency identification tag at a small distance using radio frequency (RF) data transmission technology. Most typically, the user simply holds or places the radio frequency identification tag near a base station that transmits an excitation signal to the radio frequency identification tag powering circuitry contained on the radio frequency identification tag. The circuitry, responsive to the excitation signal, communicates the stored information from the radio frequency identification tag to the base station, which receives and decodes the information.
  • RF radio frequency
  • radio frequency identification tags are capable of retaining and, in operation, transmitting a substantial amount of information - sufficient information to uniquely identify individuals, packages, inventory and the like.
  • the radio frequency identification tag is also capable of receiving and storing information.
  • the base station is not only capable of sending an excitation signal and receiving a response from the radio frequency identification tag, but it is also capable of sending a data, or write, signal to the radio frequency identification tag.
  • the radio frequency identification tag receives the write signal, which may contain data to be stored within the tag, a code or a command. Depending on the type of write signal, the radio frequency identification tag responds accordingly, such as by storing the data or acting upon the command.
  • the tag To couple either the inductive or electrostatic signals between the base station and the radio frequency identification tag, the tag necessarily includes an antenna having at least one and frequently two antenna elements.
  • a tag circuit chip and the antenna are electrically coupled and bonded to a tag substrate.
  • the tag may also include additional components, for example, resistors, capacitors, inductors, etc. that must also be electrically coupled to the tag circuit chip and/or the antenna.
  • Conventional tag design provides conductive traces formed on a substrate with the tag circuit chip, components and antenna bonded to the substrate and electrically coupled to the conductive traces. Wire bonding is a common technique for providing an electrical couple between the interconnection pads on the tag circuit chip and/or the component and the conductive traces.
  • “flip” chip technology provides raised conductive regions ("bumped pads") on the tag circuit chip (and similarly on the electrical components).
  • the "flip” chip during assembly, is inverted and positioned to the substrate with the bumped pads aligning with and electrically coupling to the conductive traces.
  • a conductive adhesive may be used between the bumped pads and the conductive traces to ensure a good electrical couple as well as to supplement the mechanical adhesion of the tag circuit chip to the substrate.
  • larger interconnection pads on the tag circuit chip provide more area for coupling between the tag circuit chip and the conductive traces.
  • larger interconnection pads on the tag circuit chip makes aligning the tag circuit chip with the conductive traces easier.
  • large interconnection pads are expensive.
  • plating whether electrode or electrode-less
  • similar metalization techniques to form larger interconnection pads can range in cost from $50 to $150 per chip wafer. This equates to a cost of about 2 - 5 cents per tag circuit chip when separated from the wafer.
  • the radio frequency identification tag In a number of radio frequency identification tag applications, the radio frequency identification tag is designed as a single use, disposable device. For example, in electronic article surveillance applications, a radio frequency identification tag is attached to and remains with each item in inventory being tracked. Hundreds of millions of items are tracked using electronic article surveillance technology in shops, stores and warehouses around the world. It is also proposed to use radio frequency identification tag technology in mail and package delivery tracking applications. The United States Postal Service alone handles over 600 million pieces of mail each day. At even the lowest estimate of approximately 2 cents per radio frequency identification tag circuit chip, increasing the size of the interconnection pads using known plating techniques is excessively cost prohibitive.
  • FIG. 1 is a perspective view in exploded assembly of a radio frequency identification tag circuit chip in accordance with a preferred embodiment of the present invention.
  • FIG. 2 is a plan view of the radio frequency identification tag circuit chip shown in FIG. 1.
  • FIG. 3 is a cross-section view taken along line 3-3 of FIG. 2.
  • FIG. 4 is a plan view of a radio frequency identification tag incorporating a radio frequency identification tag circuit chip in accordance with a preferred embodiment of the present invention.
  • FIG. 5 is a cross-section view taken along line 5-5 of FIG. 4.
  • FIG. 6 is a plan view of a portion radio frequency identification tag incorporating a radio frequency identification tag circuit chip in accordance with another alternate preferred embodiment of the present invention.
  • FIG. 7 is a cross-section view taken along line 7-7 of FIG. 6.
  • FIG. 8 is a cross-section view, similar to FIG. 7, and illustrating a portion of a radio frequency identification tag according to an alternate preferred arrangement of the present invention.
  • a radio frequency identification tag circuit chip 10 is constructed from a circuit chip 11 manufactured in accordance with known techniques from a silicon wafer. Circuit chip 11 is further formed to include at least one interconnection pad, and a first interconnection pad 12 and a second interconnection pad 14 are shown. First interconnection pad 12 and second interconnection pad 14 are formed substantially co-planar with a surface 18. It will be appreciated that first interconnection pad 12 and second interconnection pad 14 may be formed recessed into or protruding from surface 18 without departing from the fair scope of the present invention. Circuit chip 11 further includes at least one side surface, and a first side surface 20 and a second side surface 22, oriented substantially perpendicular to surface 18 are shown.
  • a layer 24 of insulating material is deposited on surface 18 and about first interconnection pad 12 and second interconnection pad 14. That is, layer 24 is formed with a first aperture 21 and a second aperture 23 surrounding first interconnection pad 12 and second interconnection pad 14, respectively. In this manner, layer 24 substantially covers surface 18 while leaving first interconnection pad 12 and second interconnection pad 14 exposed.
  • Layer 24 may be formed in separate layers spaced apart on surface 18, and or multiple layers respectively applied onto surface 18.
  • layer 24 is print deposited onto surface 18 using screen, stencil, pad transfer or similar printing techniques.
  • Layer 24 is preferably formed from a material selected from the group of materials including a non-conductive polymer, a non-conductive ink and a non-conductive adhesive.
  • Deposited on layer 24 is at least one layer of conductive material, and a first layer 26 of conductive material and a second layer 28 of conductive material are shown deposited on layer 24.
  • First layer 26 includes a portion 25 extending into aperture 21 and coupling to first interconnection pad 12.
  • First layer 26 also extends over layer 24 for virtually the entire length of circuit chip 11.
  • layer 28 includes a portion 27 extending into aperture 23 and coupling to second interconnection pad 14.
  • Second layer 26 too extends over layer 24 for virtually the entire length of circuit chip 11.
  • the conductive material forming layer 26 and layer 28 is a material selected from the group of materials including conductive ink, conductive polymer and conductive adhesive, and is print deposited on layer 24 using screen, stencil, pad transfer or similar printing techniques.
  • conductive ink conductive ink
  • conductive polymer and conductive adhesive is print deposited on layer 24 using screen, stencil, pad transfer or similar printing techniques.
  • layer 24 need be only as large as to ensure that first layer 26 and second layer 28 may be formed insulated from
  • insulating layer 24 elevates the first layer 26 and second layer 28 away from the circuit chip 11 so as to minimize capacitive coupling therebetween.
  • insulating layer 24 provides an additional barrier minimizing the chance of shorting first layer 26 or second layer 28 to circuit chip 11.
  • First layer 26 and second layer 28 define at least one printed interconnection pad on circuit chip 11 , and correspond, respectively, to a first printed interconnection pad and a second printed interconnection pad. Moreover, first layer 26 and second layer 28 form enlarged, as compared to interconnection pad 12 and interconnection pad 14, interconnection pads on circuit chip 11 for coupling, for example, to a radio frequency identification tag antenna. It is contemplated that a greater than 20:1 increase in interconnection pad area may be obtained using the present invention. It is estimated that the increase in interconnection pad area may be obtained at less than 1 cent per circuit chip.
  • a radio frequency identification tag 100 includes a substrate 30 formed to include an antenna 32 on a surface 34 thereof.
  • antenna 32 includes a first antenna element 36 including a first coupling region 38 and a second antenna element 40 including a second coupling region 42.
  • Radio frequency identification tag circuit chip 24 is secured to surface 34 and positioned between first coupling region 38 and second coupling region 42.
  • first layer 26 is coupled to first coupling region 38 via a layer 44 of conductive material
  • second layer 28 is coupled to second coupling region 42 by a layer 46 of conductive material.
  • first layer 26 and second layer 28 each may be formed at substantially less cost than forming enlarged metalized interconnection pads on circuit chip 11 using photomask, plating and similar technologies. It is believed that first layer 26 and second layer 28 may be formed at a cost of less than 1 cent per circuit chip. Thus a substantial increase in interconnection pad area is obtained at a substantial cost reduction when compared to using existing technologies to form enlarged metalized pads.
  • Radio frequency identification tag 102 is of similar construction as radio frequency identification tag 100 and includes an antenna formed on a substrate 104.
  • the antenna includes one or more antenna elements, and as shown, further includes a first coupling region 106 and second coupling region 108.
  • Radio frequency identification tag circuit chip 110 is secured to substrate 104 and between coupling region 106 and coupling region 108.
  • Radio frequency identification tag circuit chip 110 includes a circuit chip 111 formed to include a first interconnection pad 112 and a second interconnection pad 114 on a surface 118 thereof.
  • Circuit chip 111 further includes a first side surface 120 and a second side surface 122, arranged substantially perpendicular to surface 118.
  • a first insulating layer 124, including an aperture 125 surrounding first interconnection pad 112 is formed on circuit chip 111.
  • First insulating layer 124 extends over surface 118 and down first side surface 120 for substantially the entire length of circuit chip 111.
  • Second insulating layer 126 including an aperture 127 surrounding second interconnection pad 114 is formed on radio frequency identification tag circuit chip 110. Second insulating layer 126 extends over surface 118 and down second side surface 122 for substantially the entire length of circuit chip 111.
  • first layer 128 of conductive material Formed on each of first insulating layer 124 and second insulating layer 126 is a first layer 128 of conductive material and a second layer 130 of conductive material.
  • First layer 128 includes a portion 129 extending through aperture 125 and coupling to first interconnection pad 112.
  • First layer 128 also includes a portion 132 covering first insulating layer 124 over surface 118 and a portion 134 extending over first side surface 120.
  • Second layer 130 includes a portion 131 extending through aperture 127 and coupling to second interconnection pad 114.
  • Second layer similarly includes a portion 136 covering second insulating layer 126 over surface 118 and a portion 138 extending over second side surface 122.
  • radio frequency identification tag circuit chip 110 As best seen in FIG. 7, with radio frequency identification tag circuit chip 110 secured to substrate 104, portion 134 and portion 138 are aligned adjacent to first coupling region 106 and second coupling region 108, respectively. A layer 140 of conductive material and a layer 142 of conductive material are printed deposited and respectively coupling portion 134 with first coupling region 106 and portion 138 with second coupling region 108. In this manner, radio frequency identification tag circuit chip 110 is effectively, and efficiently, coupled to the antenna formed on substrate 104. With reference now to FIG. 8, radio frequency identification tag circuit chip 110 is shown coupled to a substrate 204 arranged in accordance with an alternate preferred embodiment. Substrate 204 includes a surface 206 upon which an antenna (not shown) is formed.
  • Substrate 204 is formed to include a recess 208 into which radio frequency identification tag circuit chip 110 is secured.
  • the antenna is formed to include a first coupling region 210 and a second coupling region 212.
  • Each of first coupling region 210 and second coupling region 212 extend into recess 208 and adjacent to portion 134 and portion 138, respectively.
  • a channel 214 and a channel 216 is thereby created between portion 134 and first coupling region 210 and between portion 138 and second coupling region 212, respectively.
  • a layer 218 of conductive material and a layer 220 of conductive material is deposited into channel 214 and channel 216, respectively. Layer 218 couples portion 134 with first coupling region 210, and layer 220 couples portion 138 with second coupling region 212.
  • a preferred conductive material includes one of the group of materials including conductive ink, conductive polymer and conductive adhesive.
  • Conductive adhesive advantageously provides, in addition to electrical coupling of radio frequency identification tag circuit chip 110 to the antenna, added mechanical strength for retaining radio frequency identification tag circuit chip 110 in recess 208.
  • Preferably recess 208 is also formed to a depth such that radio frequency identification tag circuit chip is disposed below surface 206 thus providing protection to radio frequency identification tag circuit chip 110 from becoming dislodged from substrate 204.
  • Recess 208 also eliminates or reduces any bumps created by the circuit chip in a covering layer and reduces stress on the circuit chip during subsequent lamination procedures.
  • Recess 208 is preferably formed by providing a localized compressed portion of substrate 204. Such a localized compressed portion may be formed by stamping or coining.
  • Recess 208 may also be formed by providing a laminate secured to substrate 204 and the laminate formed to include an aperture.
  • a radio frequency identification tag circuit chip 10 includes a circuit chip 11 having a surface 18 and at least one interconnection pad, shown as interconnection pad 12 and interconnection pad 14, formed in the surface 18.
  • a layer 24 of insulting material is deposited on the surface and about the at least one interconnection pad, and a layer of conductive material 26 is deposited on the insulating material and coupling to the interconnection pad.
  • a radio frequency identification tag 100 includes a radio frequency identification tag circuit chip 10 secured to a substrate 30.
  • the substrate 30 is formed to include an antenna 32, and the radio frequency identification tag circuit chip 10 is formed to include at least one printed interconnection pad.
  • the printed interconnection pad is a layer 26, 28 of conductive material print deposited on a surface 18 of a circuit chip 11 and coupling to an interconnection pad 12, 14 formed in the surface 18 and to the antenna 32.
  • a radio frequency identification tag 102 includes a radio frequency identification tag circuit chip 110 secured to a substrate 104.
  • the substrate 104 is formed to include an antenna
  • the radio frequency identification tag circuit chip 110 is formed to include at least one printed interconnection pad.
  • the printed interconnection pad is a layer 128, 130 of conductive material print deposited on a surface 118, 120, 122) of a circuit chip 111 and coupling to an interconnection pad 112, 114 formed on the circuit chip 111.
  • the printed interconnection pad is further coupled to the antenna.
  • a radio frequency identification tag 202 includes a radio frequency identification tag circuit chip 110 secured within a recess 208 formed in a substrate 204.
  • the substrate 204 is formed to include an antenna
  • the radio frequency identification tag circuit chip 110 is formed to include at least one printed interconnection pad.
  • the printed interconnection pad is a layer 128, 130 of conductive material print deposited on a surface 118, 120, 122 of a circuit chip 111 and coupling to an interconnection pad 112, 114 formed on the circuit chip.
  • the printed interconnection pad is further coupled to the antenna.
  • the printed interconnection pads provide a substantially larger coupling area for a radio frequency identification tag.
  • conductive polymer or conductive adhesive advantageously allows the area of the interconnection pad to be increased without substantially increasing the cost of the circuit chip.
  • printed interconnection pads formed in accordance with the preferred embodiments of the present invention may be formed for less than about 1 cent per circuit chip.
  • the larger printed interconnection pads as compared to metalized pads produced using known technologies, also simplify the manufacturing process.
  • the larger pads are easily aligned with, for example, antenna elements formed on a substrate material.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Details Of Aerials (AREA)
  • Burglar Alarm Systems (AREA)

Abstract

La présente invention concerne un microcircuit de badge HF (10) comprenant un microcircuit (11) se distinguant par une face (18) sur laquelle est réalisée au moins une plage d'interconnexions (12, 14). Une couche (24) de matériau isolant est déposée sur cette face et autour de la plage d'interconnexions (12, 14). En outre, une couche de matériau électroconducteur (26) déposée sur le matériau isolant assure le couplage avec la plage d'interconnexions (12, 14).
PCT/US1999/020312 1998-09-11 1999-09-03 Microcircuit de badge hf a plages d'interconnexions imprimees WO2000016279A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU57044/99A AU5704499A (en) 1998-09-11 1999-09-03 Radio frequency identification tag circuit chip having printed interconnection pads

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9991398P 1998-09-11 1998-09-11
US60/099,913 1998-09-11

Publications (1)

Publication Number Publication Date
WO2000016279A1 true WO2000016279A1 (fr) 2000-03-23

Family

ID=22277221

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/020312 WO2000016279A1 (fr) 1998-09-11 1999-09-03 Microcircuit de badge hf a plages d'interconnexions imprimees

Country Status (4)

Country Link
AU (1) AU5704499A (fr)
MY (1) MY117193A (fr)
TW (1) TW455826B (fr)
WO (1) WO2000016279A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6693541B2 (en) 2001-07-19 2004-02-17 3M Innovative Properties Co RFID tag with bridge circuit assembly and methods of use
US8455954B2 (en) 2005-03-08 2013-06-04 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and electronic appliance having the same
US8698262B2 (en) 2004-09-14 2014-04-15 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and manufacturing method of the same
CN112163659A (zh) * 2020-09-09 2021-01-01 北京智芯微电子科技有限公司 微型电子标签以及微型电子标签的制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262226A (en) * 1990-03-16 1993-11-16 Ricoh Company, Ltd. Anisotropic conductive film
US5495250A (en) * 1993-11-01 1996-02-27 Motorola, Inc. Battery-powered RF tags and apparatus for manufacturing the same
US5528222A (en) * 1994-09-09 1996-06-18 International Business Machines Corporation Radio frequency circuit and memory in thin flexible package
US5640052A (en) * 1993-03-10 1997-06-17 Nec Corporation Interconnection structure of electronic parts
US5654693A (en) * 1996-04-10 1997-08-05 X-Cyte, Inc. Layered structure for a transponder tag

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262226A (en) * 1990-03-16 1993-11-16 Ricoh Company, Ltd. Anisotropic conductive film
US5640052A (en) * 1993-03-10 1997-06-17 Nec Corporation Interconnection structure of electronic parts
US5495250A (en) * 1993-11-01 1996-02-27 Motorola, Inc. Battery-powered RF tags and apparatus for manufacturing the same
US5528222A (en) * 1994-09-09 1996-06-18 International Business Machines Corporation Radio frequency circuit and memory in thin flexible package
US5654693A (en) * 1996-04-10 1997-08-05 X-Cyte, Inc. Layered structure for a transponder tag

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6693541B2 (en) 2001-07-19 2004-02-17 3M Innovative Properties Co RFID tag with bridge circuit assembly and methods of use
US8698262B2 (en) 2004-09-14 2014-04-15 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and manufacturing method of the same
US8455954B2 (en) 2005-03-08 2013-06-04 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and electronic appliance having the same
CN112163659A (zh) * 2020-09-09 2021-01-01 北京智芯微电子科技有限公司 微型电子标签以及微型电子标签的制备方法

Also Published As

Publication number Publication date
TW455826B (en) 2001-09-21
AU5704499A (en) 2000-04-03
MY117193A (en) 2004-05-31

Similar Documents

Publication Publication Date Title
US6246327B1 (en) Radio frequency identification tag circuit chip having printed interconnection pads
US6091332A (en) Radio frequency identification tag having printed circuit interconnections
US5528222A (en) Radio frequency circuit and memory in thin flexible package
EP1884889B1 (fr) Dispositif semi-conducteur
AU740252B2 (en) Circuit chip mounted card and circuit chip module
US5574470A (en) Radio frequency identification transponder apparatus and method
US9177191B2 (en) Fingerprint sensing assemblies and methods of making
US7078304B2 (en) Method for producing an electrical circuit
US7277017B2 (en) RFID tag
JP4108779B2 (ja) 回路チップ搭載カードおよび回路チップモジュール
AU750290B2 (en) Radio frequency identification tag having a printed antenna and method
EP1117067A1 (fr) Carte a circuit integre
KR20010052681A (ko) 아티클 일체형 안테나를 가진 무선 주파수 식별 태그
WO2006019587A1 (fr) Étiquette de surveillance électronique ayant une antenne à couplage inductif
WO1998029263A1 (fr) Carte a puces et module de puces
WO2000026856A2 (fr) Systeme d'identification par frequences radioelectriques
NZ328217A (en) Attaching an integrated circuit to at least one electrical conductor on a flexible substrate and rfid tag comprising the substrate
AU2003243162A2 (en) Method for producing an electrical circuit
US20010046126A1 (en) Flip-chip RF-ID tag
WO2000016279A1 (fr) Microcircuit de badge hf a plages d'interconnexions imprimees
WO2001003188A1 (fr) Procede de fixation de circuit integre et dispositif correspondant
JP2001043341A (ja) チップカード
JP2000276567A (ja) 非接触ｉｃカード
KR20000062306A (ko) 회로칩 탑재 카드 및 회로칩모듈
MXPA00012138A (es) Tarjeta de identificacion de radiofrecuencia que tiene una antena integrada a un articulo

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase