Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • H03M13/2771—Internal interleaver for turbo codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • H03M13/2735—Interleaver using powers of a primitive element, e.g. Galois field [GF] interleaver

Definitions

• This invention relates to the field of electronic communications systems and, more
• AWGN additive white Gaussian noise
• error channels can be found, for example, in the code division multiple access (CDMA)
• turbo codes The key innovation of turbo codes is an interleaver which permutes the original
• the error may be recoverable with the use of error correcting algorithms in the
• a conventional interleaver collects, or frames, the signal points to be transmitted into
• the interleaver is emptied by sequentially reading
• constraining the size of the interleaver limits the separation of the time-diverse
• interleaving pattern i.e. a pseudo-irregular interleaving
• FC finite code words
• FC output sequences can occur in the output stream of a uniform-interleaving turbo coder.
• uniform interleaving does not sufficiently de-correlate the output of the two
• the minimum distance is increased to much higher values than for
• the data frame includes a memory configured to receive and store the data frame. Once received, the data
• the predetermined column size equals the predetermined size of the data frame.
• a processor is coupled to the memory and used for separating the data frame into a
• the processor also is used for generating a permuted sequence of the
• n is an integer in the range of 1 through and including P,-l, and where ⁇ , is a root of P,.
• This algorithm enables i](n,) to be a unique number between 1 and the predetermined row
• the processor is also configured to generate a permuted sequence of the plurality of
• i 2 (n 2 ) i 2 (n 2 ) to be a unique number between 1 and the predetermined column size.
• FIG. 1 is a diagram of a typical turbo encoder.
• FIGS. 2a and 2b are flowchart diagrams illustrating the operation of the improved
• FIG. 3 is a flow chart diagram illustrating another embodiment of the improved
• the present invention is an apparatus and method for interleaving codes.
• interleaver takes each incoming data frame of N data bits and rearranges them in a pseudo ⁇
• This invention can be used in
• the interleaver sorts the bits in a manner that lacks any apparent order.
• N on the order of a few thousand. This is accomplished by obtaining more diverse
• FIG. 1 depicts a standard turbo encoder. It
• the encoders 10 and 20 are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are identical to each other. They are of two encoders 10 and 20 and an interleaver 30. The encoders 10 and 20 are identical to each other components.
• the output of the first encoder 10 is a low- weight code 50 and the output of the second
• encoder 20 is a high-weight code 60. These outputs may go to a device such as a code
• the output of the interleaver 70 may also be transmitted directly to the
• the first embodiment will be referred to
• ASIC application specific integrated circuits
• PLC programmable logic arrays
• the Galya interleaver the information bit matrix has N, rows
• N are respectively greater than N, and N 2 (i.e. P, > N, and P 2 > N 2 ). It is preferred that these
• prime numbers should be the lowest prime numbers greater than N, andN 2 , respectively, but
• FIGS. 2a and 2b show the implementation of the above embodiment in either software
• step 200 defines a parameter representing block length N,.
• bit sequence is defined (step 210) to size N, and initialized.
• a prime number P is
• Step 220 which is greater than N
• Step 230 defines the initial root of N, called ⁇ ,.
• a counter n is defined and initialized to one (step 240) and incremented (step 270) for each
• step 260 the counter determines when to break out of a loop
• step 250 which calculates (step 250) the bit sequence, i ⁇ n,), for each symbol in the data frame.
• loop is conditioned to break when the entire data frame has been permuted.
• the loop can also
• step 400 defines a parameter representing block length N 2 .
• bit sequence is defined (step 410) to size N 2 and initialized.
• a prime number is defined (step 410) to size N 2 and initialized.
• Step 430 defines the initial root of N 2 called
• a counter n 2 is defined and initialized to one (step 440) and incremented (step 470) for
• step 460 the counter determines when to break out of a loop
• step 450 which calculates (step 450) the bit sequence, i 2 (n 2 ), for each symbol in the data frame.
• loop is conditioned to break when the entire data frame has been permuted.
• the loop can also
• the FH interleaver assume that the block length (or data
• prime number should be the lowest prime number greater than N, but it is
• bit sequence generation for the FH interleaver is defined by the
• FIG. 3 is an implementation of the above embodiment in either software or hardware.
• Step 300 defines a parameter representing block length N.
• Step 320 which is greater than N.
• Step 330 defines the initial root of N called .
• n is defined and initialized to one (step 340) and incremented (step 370) for each pass of the
• step 360 the counter determines when to break out of a loop which
• step 350 calculates (step 350) the bit sequence, i(n), for each symbol in the data frame.
• the loop is conditioned to break when the entire data frame has been permuted.
• the loop can be adjusted
• initialization data can consist of zeros, ones, twos, etc., or a template may be created with
• n, n, and n 2 can be any integer and the loop break conditions
• n ⁇ N, nj ⁇ N,, and n 2 ⁇ N 2 can be adjusted accordingly and still be within the scope of this
• the disclosed interleavers are compatible with existing turbo codes structure and are
• turbo codes is also well known in the art. As such they are not further discussed herein.
• a de-interleaver corresponding to the first embodiment can be constructed using
• a de-interleaver corresponding to the second embodiment can

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• Physics & Mathematics (AREA)
• Probability & Statistics with Applications (AREA)
• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Error Detection And Correction (AREA)
• Detection And Prevention Of Errors In Transmission (AREA)
• Detection And Correction Of Errors (AREA)

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Citations (5)

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• 1998
  • 1998-11-19 US US09/196,461 patent/US6347385B1/en not_active Expired - Lifetime
• 1999
  • 1999-08-02 WO PCT/IB1999/001369 patent/WO2000008770A1/en not_active Ceased
  • 1999-08-02 MX MXPA01000897A patent/MXPA01000897A/es active IP Right Grant
  • 1999-08-02 BR BRPI9912670-2A patent/BR9912670B1/pt not_active IP Right Cessation
  • 1999-08-02 JP JP2000564307A patent/JP4309586B2/ja not_active Expired - Lifetime
  • 1999-08-02 CN CNB998093084A patent/CN1140060C/zh not_active Expired - Lifetime
  • 1999-08-02 EP EP99931422A patent/EP1103102B1/en not_active Expired - Lifetime
  • 1999-08-02 DE DE69905255T patent/DE69905255T2/de not_active Expired - Lifetime
  • 1999-08-02 CA CA002337916A patent/CA2337916C/en not_active Expired - Lifetime

Patent Citations (5)

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