WO1999057802A2

WO1999057802A2 - Device for regulating rotational speed

Info

Publication number: WO1999057802A2
Application number: PCT/DE1999/001340
Authority: WO
Inventors: Thomas Köhler; Jörg Fischer
Original assignee: Heidelberger Druckmaschinen Ag
Priority date: 1998-05-05
Filing date: 1999-05-04
Publication date: 1999-11-11
Also published as: JP2002514040A; EP1076926A1; DE19819956A1; WO1999057802A3

Abstract

The invention relates to a device for regulating the rotational speed of a motor (9). The inventive device comprises a tachogenerator (10) for measuring the rotational speed and a regulating element which is configured as a parallel connection of a phase-locked loop (1) and of a frequency-locked loop (2). A time delay element (5, 6) is connected in outgoing circuit to the phase-locked loop (1) and to the frequency-locked loop (2). An adder (7) is situated between the time delay elements (5, 6) and the motor (9) in order to combine the output signals of the time delay elements (5, 6).

Description

Device for speed control

The invention relates to a device for controlling the speed of a motor, in which an actual speed value is detected by a speed sensor and fed to a control element and in which an output signal of the control element is supplied to the motor as a control signal via a delay element.

Such devices for speed control have, for example, phase locked loop control loops (PLL control loops) or frequency locked loop control loops (FLL control loops) as control loops. With FLL control loops, it is usually necessary to insert a PI element (proportional / integral element) in the control loop in order to ensure a minimal control deviation. A digital tachometer signal is often used as the actual speed value.

A disadvantage of such control loops is a remaining small control deviation, which results from an offset of the PI element, which is usually of analog design. A high-precision setting of the speed according to a predetermined target frequency is therefore not possible, or only via corrected default values.

To avoid such a residual control deviation, it is known to use the PLL control loops already mentioned. Control loops of this type are supplemented by inserting a proportional / differential element, abbreviated to PD, or a proportional / integral / differential element, abbreviated to PID, in such a way that system-technical stability and sufficient decay of a control deviation is achieved. However, the implementation of the required D component is problematic due to the control limits of the operational amplifiers normally used. This applies in particular to low sampling rates and a high amplification occurring in the analog circuit part. A damping-optimized design of the speed control loop is therefore not possible if practical boundary conditions are taken into account. A device for speed control of an engine is described for example in DE 42 21 619 A1. The phase difference between a reference signal and an engine speed is detected by a phase comparator. The phase comparator generates an output signal that is proportional to the fixed phase difference. The output signal is fed to a controller and the controller controls the motor via a control circuit. The phase comparator is connected to a sample / hold G ed.

The object of the present invention is to improve a device for speed control of an engine in such a way that the control deviations are reduced as much as possible and an optimal damping behavior is achieved.

According to the invention, this object is achieved by the features of claim 1.

Advantageous further developments and refinements of the invention are specified in the subclaims.

The invention is explained in more detail below with reference to FIGS. 1 and 2.

Show it:

Fig. 1 is a basic block diagram of the device for speed control and

Fig. 2 is a block diagram in which electronic components are given for further illustration.

1 shows a basic block diagram of the device for speed control of an engine, which essentially has a PLL circuit (1) and an FLL circuit (2). The output (3) of the PLL circuit (1) and the output (4) of the FLL circuits (2) are each connected to delay elements of the first order (5, 6), hereinafter referred to as PT1 elements. The outputs of the PT1 elements (5, 6) are connected to an adder (7). The adder (7) is connected to a motor (9) to be controlled via a correction element (8) in order to optimally design the damping behavior of the control loop. The correction element (8) can be designed as an analog proportional element (P element) or as an analog proportional / integral element (PI element).

The actual speed value (n) of the motor (9) is converted in a tachogenerator (10) into an actual clock sequence (T _Ω , _st ) representing the actual frequency value (Ω _{| St} ), which both the PLL circuit (1) and the FLL Circuit (2) is supplied. In addition, the PLL circuit (1) and the FLL circuit (2) are supplied with a set clock sequence (T _ΩSoN ) representing the frequency setpoint (Ω _So ) on a line (11).

The PLL circuit (1) has a pulse length modulator (12), the output of which corresponds to the output (3) of the PLL circuit (1). The input of the pulse length modulator (12) is connected to the output of an adder (13) which represents a comparison circuit. The Isttaktfolge (T _{Ω [st)} is in an integrator (14) in a corresponding Phasenistwert (Φ _is) representing Signalistwert (S _{φ | St)} implemented and applied to one input of the adder (13). The set clock sequence (T _ΩSo n) on the line (11) is divided in the programmable divider (15) and converted in a downstream integrator (16) into a signal set value (S _ΦSoN ) representing the corresponding phase setpoint (Φ _SoN ). The signal setpoint (S _ΦSo n) is fed to the second input of the adder (13). In the adder (13) by comparing the actual signal value (S _{φ | St} ) and

Signal setpoint (S _Φ s ₀ n) determined the phase difference (ΔΦ). The pulse length modulator (12) generates as the first controlled variable at the output (3) one of the fixed set phase difference (ΔΦ) length-modulated phase difference output pulse (l _φ ), which is converted digital / analog in the PT1 element (5).

The FLL circuit (2) also has a pulse length modulator (17), the output of which forms the output (4) of the FLL circuit (2). The pulse length modulator (17) is connected to the output of an adder (18) forming a comparison circuit, the input of which is supplied with the actual clock sequence (T _ΩSoN ).

The set clock sequence (T _ΩSoN ) on the line (11) is counted in a programmable counter (9) and the count result is given as a signal setpoint (S _ΩSoN ) to the other input of the adder (18). The frequency difference (ΔΩ) is determined in the adder (18) by comparing the period of the actual clock sequence (T _Ω , _st ) with the signal setpoint (S _ΩSoπ ). The pulse length modulator (17) generates as a second controlled variable at the output (4) a frequency difference output pulse (l _Ω ) which is length-modulated by the determined frequency difference (ΔΩ) and is converted digitally / analogously in the PT1 element (6). The programmable counter (19) can be clocked by an edge of the pulse-shaped tachometer signal (S _Ω ).

The digital / analog converted output pulses (l _Ω ; l _φ ) are combined in the adder (7) to form an overall controlled variable and fed to the correction element (8).

The parallel connection of the PLL circuit and the FLL circuit advantageously represents a control which has a PI component both to avoid control deviations and which also makes it possible to shift the required differentiation out of the analog part. The differentiation can thus be carried out in the digital domain. The PLL circuit works as a digital integrator without a disturbing frequency offset. Fig. 2 shows the device for speed control of an engine as a detailed block diagram. In the FLL circuit (2), the programmable counter (19) is designed as a 16-bit counter and is supplied by a shift register (20) with a data width of 24 bits, the data being transmitted with a word width of 16 bits. The output of the shift register (20) is connected to a control logic (21). The data transmission to the control logic (21) takes place with a word length of 8 bits. The programmable counter (19) is clocked by the target clock sequence (T _ΩSo , _| ) on line (11). A clock sequence (T.,) on a line (23) clocks the shift register (20).

The programmable divider (15) of the PLL circuit (1) is designed with a word length of 16 bits and is fed by a shift register (25). The shift register (25) has a word width of 24 bits and transmits data with a word width of 16 bits to the divider (15). The shift register (25) is also clocked by the clock sequence (T.,). The output of the shift register (25) is connected to a control logic (26) with a word length of 8 bits. The set clock sequence (T _ΩSo n) on line (11) is also applied to the programmable divider (15).

The PT1 elements (5, 6) are designed as operational amplifiers. The PT1 element (6), which is arranged in the branch of the FLL circuit (2), is followed by a further operational amplifier (27) which is designed as a P element. The correction element (8), which is designed, for example, as a PI element, likewise consists of an operational amplifier. The motor (9) is controlled via a power amplifier (28). The tachometer generator (10) can be designed such that a pulse of the tachometer signal (S _Ω ) is generated per revolution of the motor (9).

The divider (15) and the counter (19) are programmed in such a way that different setpoints for the PLL circuit (1) and the FLL circuit (2) are present. This can compensate for nonlinearities in the gain, which result from the fact that both the PLL circuit (1) and the FLL circuit (2) have finite cutoff frequencies. The non-linearities would have an effect in particular in the case of narrow output pulses which are generated when there are small differences between the target values and the actual values. For this purpose, the PLL circuit (1) is programmed with a divider factor corresponding to the real target speed. The counter reading for the FLL circuit (2) deviates slightly from the setpoint. The error of the FLL circuit (2) generates a differential pulse of a width which is compensated for by a phase deviation due to the integration of the PLL circuit (1).

When the correction element (8) is implemented as a PI element, the PLL circuit (1) operates independently of the analog offset and the motor load with a constant phase difference in accordance with the differential programming of the FLL circuit (2).

The essential features of the invention are the parallel connection of a programmable digital PLL circuit (1) and a programmable digital FLL circuit (2), the circuits (1, 2) being differential programmed in such a way that a digital offset for linearizing the gain is achieved becomes.

The speed control device is used in particular in electronic reproduction technology for driving rotating light deflectors in imagesetters or recorders.

Claims

claims

1. Device for speed control of an engine, in which a speed list value is detected by a speed sensor and fed to a control element and in which an output signal of the control element is fed to the engine as a control signal as a control signal, characterized in that

- The speed sensor is designed as a tachometer generator (10),

- The control element is designed as a parallel connection of a PLL circuit (1) and an FLL circuit (2),

- That both the PLL circuit (1) and the FLL circuit (2) is followed by a delay element (5, 6) and

- To summarize the output signals of the delay elements (5, 6) between the delay elements (5, 6) and the motor (9) an adder (7) is connected.

2. Device according to claim 1, characterized in that a correction element (8) is arranged between the adder (7) and the motor (9).

3. Device according to claim 2, characterized in that the correction element (8) is designed as a proportional element.

4. The device according to claim 2, characterized in that the correction element (8) is designed as a proportional / integral element.

5. Device according to one of claims 1 to 4, characterized in that the PLL circuit (1) has a programmable divider (15), an integrator (16), an adder (13) and a pulse length modulator (12) in series.

6. The device according to claim 5, characterized in that a further integrator (14) is connected between the tachometer generator (10) and the adder (13).

7. Device according to one of claims 1 to 6, characterized in that the FLL circuit (2) has a programmable counter (19), an adder (18) and a pulse length modulator (17) in series.