JP2002514040A - Speed controller - Google Patents

Abstract

(57) [Summary] The present invention relates to a motor (9) having a control element composed of a tachometer (10) for detecting a rotation speed and a parallel circuit of a PLL circuit (1) and a FLL circuit (2). Related to a rotation speed control device. Delay elements (5, 6) are connected downstream of the PLL circuit (1) and the FLL circuit (2), respectively. An adder (7) is provided between the delay elements (5, 6) and the motor (9) to collect the output signals of the delay elements (5, 6).

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to an apparatus for controlling the number of rotations of a motor, in which an actual value of the number of rotations is detected by a rotation number sensor and supplied to a control element, and an output signal of the control element is provided as an adjustment signal via a delay element. Supplied to the motor.

[0002] The rotation speed control device as described above has a control loop, for example, a phase lock loop control loop (PLL control loop) or a frequency lock loop control loop (FL).
L control loop). In the FLL control loop, a PI element (proportional / integral element) is often inserted in the control loop to guarantee a minimum control deviation. A digital tachometer signal is often used as the actual rotational speed.

A disadvantage of such a control loop is a slight residual control deviation, which is often due to an offset of the analog PI element. Therefore, it is not possible to precisely adjust the rotational speed according to the predetermined target frequency, for example, only by correcting the set value.

It is known to use the previously described PLL control loop to avoid such residual control deviations. Such a control loop is supplemented by inserting a proportional / differential element, abbreviated as a PD element, or a proportional / integral / differential element, abbreviated as a PID element, to improve the technical stability of the system. And a sufficient damping of the control deviation. However, realizing the required D component is problematic due to the control limits of the commonly used operational amplifiers. This is especially the case when the sampling rate is low and when the amplification occurring in the analog circuitry is high. Thus, the formation of a speed control loop with optimized damping is not possible by taking into account the actual boundary conditions.

[0005] A motor speed control device is described, for example, in DE 422 1619 A1.
Here, the phase difference between the reference signal and the motor speed is detected by the phase comparator. This phase comparator produces an output signal proportional to the fixedly adjusted phase difference. This output signal is supplied to a controller, which controls the motor via a control circuit. The phase comparator is connected to the sampling and holding device.

An object of the present invention is to improve a motor rotation speed control device so that a control deviation is reduced as much as possible and an optimum damping characteristic is obtained.

This object is achieved according to the invention by a configuration according to the characterizing part of claim 1.

[0008] Advantageous developments and embodiments of the invention are set out in the dependent claims.

The present invention will be described below in detail with reference to FIGS. 1 and 2.

Here, FIG. 1 shows a principle block circuit diagram of a rotation speed control device, and FIG. 2 shows a block circuit diagram in which electronic members are shown for further explanation.

FIG. 1 shows a principle block diagram of a motor rotation speed control device. This control device substantially has a PLL circuit 1 and a FLL circuit 2. The output 3 of the PLL circuit 1 and the output 4 of the FLL circuit 2 are each connected to primary delay elements (5, 6), hereinafter referred to as PT1 elements. The output sides of the PT1 elements 5, 6 are connected to an adder 7. The adder 7 is connected via a correction element 8 to a motor 9 to be controlled in order to optimize the damping characteristic of the control loop. The correction element 8
It can be configured as an analog proportional element (P element) or an analog proportional / integral element (PI element).

The actual rotational speed n of the motor 9 is converted into an actual clock train T _{Ω Ist} representing an actual frequency Ω _Ist in the tachometer 10 and supplied to the PLL circuit 1 and the FLL circuit 2. In addition, the PLL circuit 1 and the FLL circuit 2 are supplied on line 11 with a target clock train T _{Ω Soll} representing a frequency target value Ω _Soll .

The PLL circuit 1 has a pulse width modulator 12 whose output side is the PLL circuit 1
Corresponds to the output side 3. The input side of the pulse width modulator 12 is an adder which is a comparison circuit.
13 is connected to the output side. Actual clock train T_{Ω Ist}Is in the integrator 14
And the corresponding phase actual value Φ_IstSignal actual value S representing_{Φ Ist}To the adder 13
Is supplied to one input side. Target clock train T of line 11_{Ω Soll}Is a program
The frequency is divided by a frequency divider 15 which can be programmed, and a corresponding integrator 16 is connected downstream.
Phase target value Φ_SollTarget value S representing_{Φ Soll}Is converted to Signal target value S_{Φ Soll} Is supplied to the other input side of the adder 13. In the adder 13, the actual signal value S_{Φ Ist} And signal target value S_{Φ Soll}Is determined, the phase difference ΔΦ is determined.
The pulse width modulator 12 outputs a first control amount to the output 3 based on the determined phase difference ΔΦ.
Output pulse I whose length has been modulated_ΦIs formed in the PT1 element 5.
Digital / analog conversion.

The FLL circuit 2 also has a pulse width modulator 17, and its output side is FL
The output side 4 of the L circuit 2 is configured. The pulse width modulator 17 forms a comparison circuit
The output of the adder 18 is connected to one input of the clock train T. _{Ω Soll} Is supplied. Target clock train T of line 11_{Ω Soll}Is programmable
The signal is counted by a counter 19, and the counting result is used as a signal target value S._{Ω Soll}Adder 18 as
Is supplied to the other input side. In the adder 18, the actual clock train T_{Ω Ist}Cycle of
And the signal target value S_{Ω Soll}Is compared with the frequency difference ΔΩ.
The pulse width modulator 17 outputs the determined frequency difference Δ to the output 4 as a second control amount.
Frequency difference output pulse I width-modulated by Ω_ΩTo form a PT1 element 6
Digital / analog conversion. Pulse programmable counter 19
Tachometer signal S_ΩCan be clocked by the edge of
You.

The digital / analog converted output pulses I _Ω and I _Φ are combined into a total control amount in an adder 7 and supplied to a correction element 8.

A parallel circuit of a PLL circuit and a FLL circuit is an advantageous control unit, which has a PI component to avoid control deviations and can also move the required derivative from the analog unit. This allows differentiation to be performed in the digital domain.
Here, the PLL circuit operates like a digital integrator without a frequency offset which is a hindrance.

FIG. 2 is a detailed block circuit diagram of the motor rotation speed control device. FL
In the L circuit 2, the programmable counter 19 is configured as a 16-bit counter, and the shift register 20 gives a data width of 24 bits. Here, data transmission is performed with a word width of 16 bits. Shift register 20
Is connected to the control logic 21. Data transmission to the control logic 21 is performed with a word width of 8 bits. The programmable counter 19 is connected to the line 11
_Is clocked by the target clock train T _{Ω Soll} . A clock is supplied to the shift register 20 by the clock train T _{1 on the} line 23.

The programmable frequency divider 15 of the PLL circuit 1 has a word width of 16 bits and is supplied by a shift register 25. The shift register 25
It has a word width of 24 bits, and the data having a word width of 16 bits
5 is transmitted. Shift register 25 is also clocked similarly by the clock sequence T _1. The output of the shift register 25 is connected to the control logic 26 with a word width of 8 bits. The target clock train T _{Ω Soll of the} line 11 is also supplied to a programmable frequency divider 15.

The PT1 elements 5, 6 are configured as operational amplifiers. Another operational amplifier 27 is connected after the PT1 element 6 arranged on the circuit branch of the FLL circuit 2 as a P element. For example, a correction element 8 configured as a PI element
Also comprises an operational amplifier. The control of the motor 9 is performed via a power amplifier 28. Tachogenerator 10, 1 tachometer signal S _Omega for each rotation of the motor 9
The pulse can be configured to be formed.

The frequency divider 15 and the counter 19 are programmed so that different target values can be obtained for the PLL circuit 1 and the FLL circuit 2. Thereby, the PLL circuit 1 and the FLL
It is possible to compensate for non-linearity in amplification due to the circuit 2 having a finite limit frequency. This non-linearity can occur, in particular, when the width of the output pulse is small, which is formed when the difference between the target value and the actual value is small. PL
The L circuit 1 is programmed for this purpose with a dividing factor corresponding to the actual target speed. The counting state for the FLL circuit 2 deviates only slightly from the target value. A difference pulse is formed by the error of the FLL circuit 2 and its width is
Is compensated by the phase deviation due to the integration of

When the correction element 8 is implemented as a PI element, the PLL circuit 1 operates with a constant phase difference according to the differential programming of the FLL circuit 2 without depending on the analog offset and the motor load.

A substantial feature of the present invention resides in a parallel circuit of a programmable digital PLL circuit 1 and a programmable digital FLL circuit 2, where these circuits 1
2 is differentially programmed, which results in a digital offset to linearize the amplification.

The rotational speed control according to the invention applies in particular to electronic duplication technology and is used for driving a rotating beam deflector of an illuminator or recorder.

[Brief description of the drawings]

FIG. 1 is a principle block circuit diagram of a rotation speed control device.

FIG. 2 is a block circuit diagram in which electronic components are shown for further explanation.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] February 16, 2000 (2000.2.16)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

The present invention relates to a motor rotation speed control device.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005] DE-A-422 16 191 already describes a motor speed control device. Here, the phase difference between the reference signal and the motor speed is detected by the phase comparator. This phase comparator produces an output signal proportional to the fixedly adjusted phase difference. This output signal is supplied to a controller, which controls the motor via a control circuit. The phase comparator is connected to the sampling and holding device. From EP-A-0249465 a rotational speed control device is known, in which the control element is already configured as a parallel circuit of a PLL circuit and a FLL circuit in order to reduce the control deviation, and the output side of these circuits is Connected to adder.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

An object of the present invention is to improve a motor rotation speed control device so that an optimal damping characteristic can be obtained.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

Advantageously, the PLL circuit and the FLL circuit 2 comprise a programmable digital circuit 1,
2 wherein these circuits 1 and 2 are differentially programmed to provide a digital offset to linearize the amplification.

──────────────────────────────────────────────────の Continuation of the front page (71) Applicant Kurfuersten-Anlage 52-60, Heidelberg, Federal Republic of Germany F term (reference) 5H550 GG07 HB16 JJ12 JJ22 JJ24 LL03 LL33 LL33

Claims (7)

[Claims] 1. A motor speed control, wherein an actual speed value is detected by a speed sensor and supplied to a control element, and an output signal of the control element is supplied to the motor as an adjustment signal via a delay element. In the apparatus, the rotation speed sensor is configured as a tachogenerator (10), the control element is configured as a parallel circuit of a PLL circuit (1) and a FLL circuit (2), and the PLL circuit (1). ) And the FLL circuit (2), a delay element (5, 6) is connected downstream of the delay element (5, 6). A rotation speed control device, wherein an adder (7) is connected between the rotation speed control device and the rotation speed control device. 2. A correction element (8) between said adder (7) and said motor (9).
The device according to claim 1, wherein 3. The device according to claim 2, wherein the correction element (8) is configured as a proportional element. 4. The device according to claim 2, wherein the correction element (8) is configured as a proportional / integral element. 5. The PLL circuit (1) includes a frequency divider (15) programmable by a serial circuit, an integrator (16), an adder (13), and a pulse width modulator (12).
The device according to any one of claims 1 to 4, comprising: 6. The apparatus according to claim 5, wherein another integrator (14) is connected between the tachogenerator (10) and the adder (13). 7. The FLL circuit (2) comprises a serial circuit programmable counter (19), an adder (18), and a pulse width modulator (17). The apparatus according to claim 1.