WO1999040492A1 - Procede et dispositif de traitement de donnees selon une fonction de traitement donnee a l'aide d'un circuit logique programmable - Google Patents

Procede et dispositif de traitement de donnees selon une fonction de traitement donnee a l'aide d'un circuit logique programmable Download PDF

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Publication number
WO1999040492A1
WO1999040492A1 PCT/DE1999/000167 DE9900167W WO9940492A1 WO 1999040492 A1 WO1999040492 A1 WO 1999040492A1 DE 9900167 W DE9900167 W DE 9900167W WO 9940492 A1 WO9940492 A1 WO 9940492A1
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WO
WIPO (PCT)
Prior art keywords
logic circuit
programming
programmable logic
data
processing operations
Prior art date
Application number
PCT/DE1999/000167
Other languages
German (de)
English (en)
Inventor
Ludwig Schweiger
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to CA002320079A priority Critical patent/CA2320079A1/fr
Priority to EP99907270A priority patent/EP1053513A1/fr
Publication of WO1999040492A1 publication Critical patent/WO1999040492A1/fr

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/056—Programming the PLC

Definitions

  • the present invention relates to a method for processing data according to a predetermined processing function with the aid of a programmable logic circuit, the processing function being able to be represented as a combination of several groups of partial operations. Furthermore, the present invention relates to a corresponding device for performing this method.
  • circuitry functions can be implemented in terms of both hardware and software. This means that, for example, digital filters, algorithms, complex arithmetic logic units and the like can either be implemented by a hardware circuit or can be simulated by appropriate software.
  • Possible hardware solutions are, for example, integrated circuits (ICs), application-specific integrated circuits (Application Specific Integrated Circuits, ASICs) or user-programmable gate arrays (Field Programmable Gate Arrays, FPGAs).
  • ICs integrated circuits
  • ASICs Application Specific Integrated Circuits
  • FPGAs Field Programmable Gate Arrays
  • Hardware solutions achieve high data throughput, but require a large chip area, which increases the costs for the selected hardware accordingly.
  • the hardware solutions are generally limited to only one functionality, i. H. the hardware solutions cannot be used for different functionalities and are therefore inflexible.
  • the present invention therefore has for its object to provide a method for processing data to provide in accordance with a specified differently surrounded processing function (functionality) and a corresponding device, while through the use of hardware, a high throughput and a high speed to provide a high flexibility in terms of functionality is guaranteed.
  • this object is achieved by a method having the features of claim 1 and an apparatus having the features of claim 10.
  • a programmable logic circuit in particular a field programmable gate array (FPGA) is used to carry out a predetermined processing function, ie to carry out a specific functionality.
  • This logic circuit can be reprogrammed, ie reconfigured.
  • functionality blocks of this programmable logic circuit are changed during operation, ie during the execution of a predetermined processing function, by successive reprogramming of the logic circuit. If a certain functionality block has been programmed, the group of operations corresponding to this functionality block is first carried out and, if necessary, intermediate results are stored. A new functionality block is then programmed, the previously determined intermediate results and possibly further data being processed in accordance with a group of operations corresponding to this new functionality block.
  • the programmable logic circuit can be reprogrammed several times to carry out a plurality of functionality blocks, the individual functionality blocks being matched to one another in such a way that they result in the desired processing function in combination, so that after the programming of the last functionality block and execution of the corresponding last group of processing 4 processing operations are output by the programmable logic circuit data which correspond to the input data of the logic circuit processed according to the predetermined processing function.
  • the structure of digital filters, algorithms or complex arithmetic-logic microprocessor units is predestined for the application of this new technology.
  • the present invention corresponds to a combination of the two approaches described at the outset, since the reprogramming of the programmable logic circuit to achieve different functionality blocks is preferably computer-controlled, depending on the corresponding stored programming data.
  • the programmable logic circuit By using the programmable logic circuit as a hardware element, a high data throughput and a high processing speed with relatively low chip costs are guaranteed. Since the reprogramming of the programmable logic circuit is advantageously carried out under software control, a sufficiently high degree of flexibility is also ensured, since the programming data required in this case for reprogramming can be easily changed or adapted depending on the functionalities desired in each case.
  • Fig. 2 shows the exemplary structure of a digital filter
  • FIG. 1 shows illustrations for realizing the digital filter function shown in FIG. 2 when using the method according to the present invention.
  • a programmable logic circuit 1 shown in FIG. 1 is proposed, which is reprogrammed in order to carry out different functionalities, each of which corresponds to specific groups of processing operations.
  • Programmable components or logic circuits have been known for a long time.
  • a group of such logic circuits that can be programmed for specific applications are so-called field programmable gate arrays (FPGAs).
  • FPGAs field programmable gate arrays
  • Logic circuits of this type have an internal structure with a large number of primitive cells, which consist of logic gates, flip-flops and in some cases also of simple programmable components (programmable logic devices, PLDs).
  • FPGAs can have several 100 connections or pins and several 1000 gate equivalents and are therefore suitable for the implementation of very complex circuits and for the execution of correspondingly complex processing functions or functionalities.
  • the FPGAs consist of a large number of primitive cells. Depending on the desired function of the logic circuit, these primitive cells must be wired accordingly, ie the connections between the individual cells must be defined. This is done with the aid of programming, the desired configuration of the wiring generally being stored in a random access memory (RAM) on the FPGA chip. Depending on the configuration thus saved, the logic circuit then carries out the desired functionality.
  • RAM random access memory
  • FIG. 1 also shows the programming device 3 for programming the logic circuit 1 and the RAM memory 21 for storing the wiring configuration of the logic circuit 1 that is currently specified by the programming device 3.
  • the programmable logic circuit 1 is configured such that it to a certain number of input data x ⁇ a pre-added functionality or processing function, z. B uses a digital filter function. This functionality can be seen as a combination of several groups of processing operations, e.g. B. multiplications and additions are shown. Accordingly, according to FIG.
  • the programming device 3 is controlled by a central control device 2, which is generally formed by a computer, in such a way that the programming device 3 in the memory 21 successively defines wiring configurations for the programmable logic circuit 1, which assign the successive groups of processing operations or processing procedures.
  • the device shown in FIG. 1 has storage means in which, depending on the individual operations to be carried out, the respectively required wiring configurations are stored. These storage means can be configured, for example, in the form of configuration files 4, so that the programming device 3 simply by loading the corresponding stored wiring configuration (download) and storing this wiring configuration in the memory 21 is the prerequisite for carrying out the corresponding functionality block or appropriate processing operations creates.
  • a further memory 5 for. B. a read-only memory (ROM) is possible, in which the respectively required wiring configurations or the corresponding programming data are stored.
  • ROM read-only memory
  • the input or reception data x are to be processed in accordance with a specific processing function (functionality).
  • the programmable logic circuit 1 can 7 undergo digital data x a digital filter function, so that the output data output by the logic circuit 1 y correspond to the filtered input data x.
  • the Lo ⁇ gikscrien 1 functionality to be performed is made up of a combination of several groups of Swisssoperatio ⁇ NEN or partial functionalities together, which are known to the controller.
  • the central control device 2 controls the programming device 3 such that it successively reads programming data by accessing the memory means 4, 5 in order to program the logic circuit 1 in such a way that the aforementioned individual groups of processing operations are carried out in succession (or also in parallel) become. This is done by storing corresponding configuration data in the memory 21, so that the logic circuit 1 initially has, for example, a first partial functionality, such as, for. B. performing multiplications, and then a second sub-functionality, such as. B. performing additions. After a partial functionality has been carried out, the logic circuit 1 stores intermediate results in a buffer memory 6, so that these are available for the subsequent partial functionalities or processing operations of the logic circuit 1. After the control device 2 has activated the programming device 3 for programming the logic circuit 1 in accordance with the last functionality to be executed, the logic circuit 1 outputs the desired output data y.
  • the buffer memory 6 can also be designed in the form of a corresponding memory area within the logic circuit 1, which is indicated by dashed lines in FIG. 1, the content of this memory area being adaptable by reprogramming the logic circuit, which increases the speed and the data throughput .
  • the input data x in the form of Jerusalemeinan ⁇ of the following samples. This means that the previously described optimizations Umprogra the logic circuit 1 for each ⁇ each sample are carried out, each environmental programming must be performed within a sampling period of the input data x.
  • the reprogramming or reconfiguration speed of the programmable logic circuit 1 determines its maximum sampling rate. This means that smaller circuit configurations are advantageous for high data throughput. Accordingly, digital filters, in particular, can be implemented very well with the aid of the device according to the invention due to its simple structure.
  • the memory means 4/5 preferably contain all programming or configuration data that are required for carrying out certain functionalities or partial functionalities of the logic circuit 1.
  • the central control device 2 can accordingly set different overall functionalities or overall processing functions of the logic circuit 1 by correspondingly controlling the programming device 3.
  • the control device 2 can reprogram the programmable logic circuit 1 with the aid of the programming device 3 in order to implement different digital filter functions with different filter coefficients. That is, not only can the logic circuit 1 be reprogrammed during the execution of a specific processing function, but the overall functionality of the programmable logic circuit 1 can also be variable. This change in the overall functionality of the logic circuit 1 can take place in particular as a function of a corresponding control signal s which is supplied to the control device 2.
  • FIG. 2 shows an example of the structure of a recursive digita ⁇ len second order filter.
  • the filter shown in Figure 2 to ⁇ summarizes two shift registers 15, 16, three adders 12 to 14 and five multipliers 7 - 11.
  • the digital filter shown in Figure 2 is associated with the following transfer function G (z).:
  • the digital filter function shown in FIG. 2 is carried out using the method according to the invention as shown in FIGS. 3a and 3b.
  • the programmable logic circuit which is to implement the digital filter function shown in FIG. 2 is first activated in such a way that the logic circuit performs the multiplications for the calculation of the corresponding output value, ie the logic circuit is programmed in such a way that for example, the multiplier circuit shown in FIG. 3a is generated with the coefficients a 0 - b 2 .
  • Registers 17, 18 are provided for the forward branch, while only one shift register 19 is provided for the feedback branch.
  • the logic circuit 1 shown in FIG. 1 is designed such that output values y A calculated by it are always stored in the buffer memory 6, so that, according to FIG.
  • Multiplier circuit can also be modified such that the function of the shift register 19 by one of the two shift 10 registers 17 and 18 is perceived.
  • the shift registers 17-19 according to FIG. 3a fulfill the function of the shift registers 15 and 16 shown in FIG. 2.
  • the multipliers 9-11 correspond to the multipliers shown in FIG. 2, the output data of these multipliers being stored in the buffer memory 6 as an intermediate result become.
  • the logic circuit shown in FIG. 1 is then reconfigured or reprogrammed in such a way that the logic circuit 1 performs the function of an adder for adding the data stored in the buffer memory 6.
  • This functionality of the logic circuit 1 is shown in Fig. 3b.
  • the intermediate results of the individual multipliers 7-11, which are stored in the memory 6 in FIG. 3a, are individually fed to an adder 20, which delivers the corresponding output value ⁇ as the output signal, where:
  • y 1 ao * x 1 + a ⁇ * x i - ⁇ + a 2 * x 1 - 2 + b ⁇ * y i - ⁇ + b 2 * y x - 2 .
  • the output value of the adder 20 is at the same time stored again in the buffer memory 6, so that it is available for subsequent multiplication operations when a new sample value x 1 + i is present for the multiplier circuit shown in FIG. 3a.
  • the digital filter function shown in FIG. 2 is accordingly implemented in that the overall functionality of the logic circuit 1 is divided into two sub-functionalities, namely on the one hand the execution of multiplication operations and on the other hand the implementation of addition operations. These two sub-functionalities are coordinated with one another in such a way that after the last sub-functionality has been carried out, ie according to FIG. 11 on, processed input data are output as output data y.
  • the present invention can of course also be used to implement any other functionalities or processing functions.
  • a special application is the implementation of encryption or decryption functions.
  • completely different (encryption or decryption) algorithms can be carried out by suitable programming of the programmable logic circuit, which algorithms are executed either sequentially or in parallel in the logic circuit 1.
  • the control device 2 shown in FIG. 1 can be supplied with a key code via the control signal s, which tells the control device 2 in what order the individual parallel or serial conversions are to be processed.
  • corresponding reprogramming of the programmable logic circuit 1 can be used to carry out encryption or decryption corresponding to the respective key code s, which are composed by combining the individual partial functionalities of the programmable logic circuit 1, which in turn depend on the programmable logic circuit 1 of the configuration data stored in the memory 21 by the programming device 3.
  • the present invention is also suitable for realizing complex arithmetic logic functions.
  • Arithmetic-logical microprocessor units ALUs
  • ALUs Arithmetic-logical microprocessor units
  • These can be arithmetic integer operations, logical operations, comparison operations, or shift operations, etc.
  • RISC processors Reduced Instruction Set Computer
  • CISC processors Complex Instruction Set Computer
  • a programmable logic circuit which is reprogrammed during the execution of the desired processing function to process different groups of processing operations, parts of the ALU or the entire ALU can be optimized with regard to one processing operation or several processing operations.
  • ALUs, additions, multiplications etc. occur analogously to the example of digital filter functions described above.
  • the programmable logic circuit can thus first be programmed to carry out this functionality in such a way that the logic circuit functions as an adder and stores the intermediate result (internal or external).
  • the programmable logic circuit is then reprogrammed such that it performs the function of a multiplier.
  • the logic circuit accesses the temporarily stored results and possibly further data or parameters and carries out the desired multiplication.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne un procédé et un dispositif de réalisation d'une fonction de traitement ou d'une fonctionnalité déterminée devant être appliquée aux données à traiter (x). La fonction de traitement respective peut être représentée sous forme de combinaison de plusieurs groupes d'opérations de traitement ou fonctionnalités partielles. Un circuit logique (1) programmable, notamment un prédiffusé programmable, est programmé plusieurs fois de suite de telle façon que les différents groupes d'opérations de traitement puissent être exécutés séparément par le circuit logique (1) programmable et soient combinés de telle façon que le dernier groupe exécuté des fonctions de traitement donne finalement le résultat souhaité, c'est-à-dire les données traitées (x) selon la fonction de traitement sous forme de données de sortie (y).
PCT/DE1999/000167 1998-02-06 1999-01-22 Procede et dispositif de traitement de donnees selon une fonction de traitement donnee a l'aide d'un circuit logique programmable WO1999040492A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002320079A CA2320079A1 (fr) 1998-02-06 1999-01-22 Procede et dispositif de traitement de donnees selon une fonction de traitement donnee a l'aide d'un circuit logique programmable
EP99907270A EP1053513A1 (fr) 1998-02-06 1999-01-22 Procede et dispositif de traitement de donnees selon une fonction de traitement donnee a l'aide d'un circuit logique programmable

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19804827.0 1998-02-06
DE19804827 1998-02-06

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432719A (en) * 1989-07-28 1995-07-11 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distribution memory
DE4425388A1 (de) * 1994-07-19 1996-01-25 Bosch Gmbh Robert Steuergerät
EP0499695B1 (fr) * 1991-02-22 1996-05-01 Siemens Aktiengesellschaft Automate logique programmable
DE19541816A1 (de) * 1994-11-09 1996-05-15 Fuji Heavy Ind Ltd Diagnosesystem für ein Kraftfahrzeug
DE19722365A1 (de) * 1996-05-28 1997-12-04 Nat Semiconductor Corp Rekonfigurierbares Rechenbauelement

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432719A (en) * 1989-07-28 1995-07-11 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distribution memory
EP0499695B1 (fr) * 1991-02-22 1996-05-01 Siemens Aktiengesellschaft Automate logique programmable
DE4425388A1 (de) * 1994-07-19 1996-01-25 Bosch Gmbh Robert Steuergerät
DE19541816A1 (de) * 1994-11-09 1996-05-15 Fuji Heavy Ind Ltd Diagnosesystem für ein Kraftfahrzeug
DE19722365A1 (de) * 1996-05-28 1997-12-04 Nat Semiconductor Corp Rekonfigurierbares Rechenbauelement

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EP1053513A1 (fr) 2000-11-22
CA2320079A1 (fr) 1999-08-12

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